DE1215759B - Circuit arrangement for the separate evaluation of temporally overlapping arriving information elements and for displaying information elements that overlap completely or almost completely - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. CL:

H03k

German KL: 21 al - 36/20

Number; 1215759

File number; S 91725 VIII a / 21

Filing date: June 26, 1964

Opening day: May 5, 1966

To prevent the simultaneous actuation of two keys on a typewriter or teletypewriter keyboard so-called ball locks are known. For this purpose, a wedge-shaped projection is provided on each key, which, when the key is pressed, turns into one below the keys Ball chain penetrates. The balls are stored with so much play that there is just a wedge along the entire row can be placed between two balls, but the remaining balls are firmly pressed together. With such an arrangement, a second key can only be pressed when the first key has already been pressed is released.

With regard to keyboards with electrical evaluation, there is sometimes a need for and the need for multiple key presses that have occurred consecutively and overlapped in to be evaluated separately in a consistent order. By such keyboards with the possible time Overlapped actuation of the keys is accelerated by a bound notation of writing possible.

The invention is based on the object of creating a circuit arrangement which ensures a separate, consistent evaluation of information elements arriving via individual inputs with a temporal overlap and also recognizes if a subsequent information element is within a time period T, calculated from the beginning of the preceding information element η n + 1 occurs. It is irrelevant whether it is information elements that reach the new circuit via mechanically operated or electronic switches.

The object is achieved in that a switching means is assigned to each input and all these switching means are activated in the idle state by a criterion which is canceled by an incoming information element at the assigned switching means , be queried at the beginning of the information element via a control element applied timer after a certain time T , and that a control circuit is arranged, which checks the buffer after the certain time, whether more than one output signal is available. This means that a switching means and a buffer are assigned to each input. The beginning of an information element present at the input is registered in the buffer memory. With the storage, a circuit arrangement for the separate evaluation of temporally overlapping arriving and for
Display of completely or almost completely overlapping information elements

Applicant:

Siemens & Halske Aktiengesellschaft,
Berlin and Munich,
Munich 2, Wittelsbacherplatz 2

Named as inventor:

Dipl.-Ing. Erwin Buxmeyer, Bad-Vilbel

Switching means and thus also buffering a common timing element is stimulated which, after the time Γ has elapsed, triggers a control that checks whether (within the time period T) an information element is switched on at more than one input. If the result is positive, the message in the buffer is evaluated.
According to a further development of the invention, a separate intermediate storage device and part of the circuit complexity can be saved in that each switching means is used at the same time as an intermediate storage device for the assignment of the inputs. Furthermore, the common timing element can send an interrogation pulse to all switching means after the specified time T has elapsed, and an error display can be made if more than one read pulse occurs.
When entering information elements through a keyboard, the time Γ is dimensioned, for example, in such a way that under no circumstances can two keys be deliberately actuated within this period of time. If, on the other hand, it is a matter of evaluating information elements arriving via separate lines, the time Γ is set in such a way that, taking into account a certain safety distance, a clear evaluation of two overlapped characters can still be carried out to evaluate four temporally overlapping information elements individually one after the other and also to fully

609 567/461

3 4

Constantly covering characters as an error, the control circuit Ks blocking the excretion. In addition, there is also an error message rating Aw. At the same time, a display Az becomes possible if, for example, the four information items are switched. Under the evaluation A w example elements are entered through a keyboard and wise a coding circuit through which a fifth key is pressed as long as the four 5 preceding information stored in the buffer Zs are still printed. Another is implemented in code.
The advantage of using it on a keyboard is that, in FIG. 2, a further development of the invention is based on the fact that bruises on the keys are shown. With the Ts key open, d. that is, am are eliminated. Switching means no information element is present, flows

The invention is based on the figures at Aus io from the source El via the resistor El, the

management examples from magnetic core technology er diode D, winding W3 of core K and over

purifies. the resistor R2 a current II. The current / 1

Magnetic cores can be used as switching means with the right-hand flow generated in the core K , the working angular hysteresis loop or, for example, also point after point A on the positive branch of the flip-flops or diode gates. 15 hysteresis loop. The kernel K is thus inscribed

1 shows a symbolic embodiment only. If the Ti key is closed, the

borrowed for an input in which the application of a voltage from the source E 2 across the resistor R1,

Information element closing a work button Ts, winding Wl of the core K and over the

contact is equivalent, resistor R3 a current 12, which through his

F i g. 2 a further development of the embodiment according to size and direction generates a flow that

F i g. 1, the working point after point B on the negative

Fig. 3 can jump a further embodiment with more branch of the hysteresis loop. The cons

other inputs, states Al, R2, R3 are selected so that when

4 shows an illustration of the key Ts used in FIG.

Deten assembly Ag ₁ ■ ² 5 ⁰ P It i ^{st> which} means that the source only by El

5 shows an exemplary embodiment with "a small reverse current of the diode is loaded,

gear, in which the, creation of an information- Exactly as in the case of the deletion shown in Fig. 1

element is equivalent to opening a normally closed contact, also according to the circuit arrangement in

is significant, Fig. 2 with the closing of the button Ts in winding

6 shows a further development of the circuit arrangement 3o W2 induces a voltage pulse which

tion according to Fig. 5 with several inputs. closed transistor Tr to the intermediate

The invention is based on exemplary embodiments and memory for the control device of the timing element

explained, in the case of which 'magnetic cores with rectangular arrives.

Hysteresis loop can be used as switching means. A further development, in particular by the DC voltage source El in Fig. 1 is so-35 circuit moderate effort is reduced is that shown in switches, with an open key Ts over the Wick- FIG. 3. In this solution, Wl of the core K a current / 1 flows. The limited switching means is, as in those described above, the current 71 through the resistors Rl and solutions, a magnetic core with a rectangular hysteresis R2. The flow generated by the current / 1 in the reseschleife. In Fig. 3, the switching means with Kl core K sets the operating point on the positive branch 40 to Kn . By winding Wl all of the hysteresis loop in the points. If the cores are now and a current flows through the resistor Rg ■ key Ti is closed, which is equivalent to the / 1, which is a magnetic bias voltage applying an information element to the cores; so drives so that the working point to A on the voltage source E 2 with suitable dimensioning migrates the positive branch of the hysteresis loop, the resistors Al, R2 and R3 via the 45. If the button TsI is now closed, a flows through winding Wl Current 12, which is opposite to the current Zl, the winding W2 of the core Kl and across the counter. The current / 2 is so large that Al was a current / ZjI to the control element Ag, which stimulates the operating point after point B to the negative one through ITsI, controls the timing element Zg , and the branch of the hysteresis loop jumps. As a result, like the control element Ag for all switching means, a voltage pulse er 50 is present in common in the winding W2. The flow generated by the current / TiI im, the flow through which is caused to control the connected core Kl , is used in such a way that transistor Tr is used. directs that the working point from A to B in the

At the collector of the transistor Tr are migrated in the positive remanence point, which practically point χ an associated, for example as a core is equivalent to a storage of the fact that memory built-up intermediate storage Zs and the key TiI has been closed via 55, or generally a control device Ag Common to all switching means is that at the input of the switching means K 1 the same timing element Zg, for example a monostable, an information element has been applied. After tipping stage, connected. The timing element Zg can be understood as the expiry of a period of time T , the timing element Zg sends a synchronization circuit, for the duration t a current / 2 which, after a time T syn- 60 series, is passed through the windings W 3 which are in their task the cores Kl to chron a pulse Kn and flows through the resistor RZg with a predetermined cycle. To be sent out at the beginning. After a time T has elapsed, the current / 2 jumps in the kernel to the memory. The output signal of the timing element Zg queries all intermediate points on the hysteresis loop from B to C. A control circuit 65 connected to the outputs of the intermediate cores K2 to Kn from A to B. This means that control circuit 65 connected to the intermediate memory Zs is that only at Kl at the winding W 4 a voltage Ks, which can be based on a current measurement, is induced that the W4 connected Tranchecks whether a sistorTrl is controlled from more than one buffer memory. The change in the magne signal is coming. If such a case occurs, the flow in the nuclei K2 to Kn is too small,

in order to allow a sufficiently large control voltage to arise in the associated windings W 4 for the connected transistors Tr 2 to Tr η. The connected control circuit Ks has the same task as the control circuits of FIG. 1 and 2. The mode of operation of the control circuit is basically the same, for example, as that of the core ZV in FIG. 4th

At the end of the current / 2, the working point of Z1 lies at point D, which represents the negative remanence position; at the cores K 2 to Kn it goes back to point A. If another key Ts is now pressed, for example Ts 2, the operating point in K 2 moves to B. After the time T has elapsed, the operating point in core K 2 moves from B to C, caused by the current 72 transmitted by the timer Zg , in the core Kl, since the key TsI was still pressed, from D to C and in the case of the cores K 3 to Kn from A to B. This means that an output pulse is only generated with the switching means K 2. As has been shown, it is thus possible in this way to evaluate message elements arriving at a time overlapping one after the other and to discard characters that overlap completely or within the time T as errors.

In the present application of the solution described, for example up to four information elements arriving at a time overlapping can be evaluated individually one after the other. In addition, an erroneous display Aζ is possible if, for example, the information elements are entered through a keyboard and a fifth key is pressed while the four previous ones are still pressed. Another advantage of using it on a keyboard is that it eliminates the bruising of the keys. Flip-flops or diode gates can also be used as switching means.

In the case of the solution shown in FIG. 3, only one voltage source is required, and the simultaneous use of the switching means as a memory eliminates the need for special intermediate storage. In addition, only one resistor is required individually for each switching device, and only one current II flows in the idle state.

On the basis of FIG. 4, which shows the circuit of the in box Ag in FIG. 3 shows the control element shown, its mode of operation will be explained. The five toroidal cores ZI to KV shown are magnetic cores with a rectangular hysteresis loop. Each core carries three windings, which are labeled Wl, W 2, W 3. As shown in FIG. 4, the windings Wl of the cores ZI to KV and the windings fF2 of the cores Kl to KV are each connected in series, while the series connection of the winding W 3, which is a read winding, is limited to the core Kl to KlV . A transistor TrI or Tr 2 is connected to the series connection of the windings W 3 of the cores Kl to ZIV and to the winding W 3 of the core ZV.

If the number of turns of the winding PFl in the core is ZI η, the corresponding number of turns for the core ZII is 3 η, for the core ZIII 5 η, etc. The number of turns m of the windings W 2 and the number of turns ρ of the windings W 3 are the same for all cores. A quiescent current IX flows through the windings Wl.

Due to the different numbers of turns, the operating point for the cores ZI to ZV is on the magnetization shown below. curve at different points, namely Al, A2, A3, A4 and AS.

The sum of the ¹ key currents ITs is carried through the windings W 2 . If a key is depressed, all the working points migrate as a result of the current ITs by an equal amount on the magnetization curve to the left, namely Al to Bl, AE2 to B 2, A 3 B 3 after the flux change, etc. By

ίο in ZI a voltage is induced in W 3 by the core ZI, which controls the connected transistor TrI, which thereby excites the timing element Zg.

If a second key is now pressed while key 1 is still pressed, a voltage is now induced in winding W3 of the core ZII which controls the transistor TrI. The working points shift from B1 to C1, from 52 to C2, etc. If a fifth key is pressed, although four others are still pressed, so

ao, a voltage is induced in winding W 3 of the core ZV, which in turn controls the connected transistor Tr 2 , which serves as a criterion for a false display Az .
When overlapped operating up to a maximum of four buttons is therefore quite independent of the state of the timer Zg, issued by the transistor TrI a drive signal to the connected timer Zg. If this signal falls within the time span T, however, it has no effect on the timer and is recognized by Zs as an error at the end of T.

With the in the Fi g. 1, 2 and 3, the creation of an information element was always identical to the actuation of a normally open contact. The task at hand can also be achieved if, instead of a normally open contact, a normally closed contact is used or a switch that functions in the same way as such. Fig. 5 shows in principle such a solution for only one input.
As long as no information is present, that is, as long as TsI is closed, the winding Wl flows via the resistor Rl, Zl of the core and the key TsI a current ITSI, which acts so that the operating point at the point A is located. By opening the Ts 1 key, which is equivalent to creating information, / TsI = O. The operating point then coincides with the positive remanence point B. At the moment TsI opens , a timing element Zg is switched on via a control element Ag which, after a time T has elapsed, sends out a current / 2 for the duration t via the series-connected windings W 2 of all cores and the resistor R2. A signal is only generated in the core Z1 through the effect of / 2 in W 3, since here the operating point jumps from B to D , while in the other cores it only jumps from A to C. A control circuit Ks connected to the outputs of the switching means (in the exemplary embodiment according to FIG. 5 the collector of the transistor TrI connected to the winding W 3) takes on the function of the control circuits already described with reference to FIGS.

A disadvantage of this in FIG. 5 is that, as long as no information is available, an individual current flows in all switching means.

With a large number of such switching devices, the continuous load on the power supply devices is high. It is cheaper if you have a powerful switch S, the number of individual switching currents

medium lets flow impulsively. Such a solution is shown in FIG. 6 shown.

The following requirements must be met for this circuit to function properly:

1. The switch S must not be closed if the timer for the duration t the

■ Emits current / 2.

2. The switching frequency of switch S must be such that the switching

: ter S is closed during a key actuation and between two possible actuations of a key.

: 3. The control element AgI is to be expanded by an upstream logic circuit.
. The invention is not restricted to the exemplary embodiments described and illustrated. For example, the simultaneous actuation and separate and consistent evaluation is not limited to four keys, but could easily be expanded to ten keys with regard to the ten-finger writing system.

Claims (7)

Patent claims: 1. Circuit arrangement for the separate, consistent evaluation of overlaps in time several individual inputs incoming ■ information elements and for displaying · .. completely or almost completely overlapping information elements, characterized in that a switching means (Kl to Kn) is assigned to each input (1 to n) . and all these switching means are activated in the idle state by a criterion which is canceled by an incoming information element at the associated switching means that. Temporary memories (Zs) are provided for registering this process, which are queried by a common timing element (Zg) applied at the beginning of the information element via a control element (Ag ) after a certain time (T) , and that a control circuit (Ks) is arranged is, which after the specified time (Γ) checks the buffer, whether more than one output signal is available (Fig. 1, 3, 5 and 6). 2. Circuit arrangement according to claim 1, characterized in that the switching means (if I to Kn) simultaneously represent intermediate storage for the assignment of the inputs (Fig. 3 and 6). 3. Circuit arrangement according to claim 1 and 2, characterized in that the common timing element (Zg) emits an interrogation pulse to all switching means after the specified time (T) has elapsed and an error display occurs when more than one read pulse occurs (Figs. 3 and 6 ). 4. Circuit arrangement according to Claims 1 to 3, characterized in that magnetic cores with a rectangular hysteresis loop are used as switching means (Kl to Kn) , which are in the idle state due to a common bias in the saturation region. 5. Circuit arrangement according to claims 1 to 4, characterized in that a pulse generator composed of magnetic cores (KI to KY) is provided as the control element (Fig. 4). 6. Circuit arrangement according to claim 5, characterized in that when the information X + 1 is received, when the preceding information 1 to X are still pending, an error display occurs. 7. Circuit arrangement according to claim 1, characterized in that an evaluation. arrangement (A w) is provided to which the output signals obtained are fed separately and amplified by transistors and which converts these .. signals into a code. For this purpose 2 sheets of drawings 609 567/461 4.66 © Bundesdruckerei Berlin