DE10116875B4 - Method for producing an integrated ferroelectric memory - Google Patents

Abstract

method for producing an integrated ferroelectric memory according to the stack cell principle, whereby transistors are formed on a wafer, subsequently one first intermediate oxide (2) deposited and on this first intermediate oxide (2) ferroelectric capacitors (1) made over the entire surface and then be structured in one step and over the structured ferroelectric Capacitors (1) a hydrogen diffusion barrier (10; 11) deposited is, wherein the ferroelectric capacitors (1) with its lower Electrode (4) by an underlying electrically conductive Plug (8) with a corresponding transistor electrode of a selection transistor and after structuring of the ferroelectric Capacitors (1) a second intermediate oxide layer covering them (3) applied and then is polished down to the upper capacitor electrode (6) and about that one covering the exposed upper capacitor electrode (6) and electrically contacting common plate (11) is formed, characterized characterized in that the hydrogen diffusion barrier (10) formed at least one layer of a non-conductive material and over the common plate (11) is applied, the hydrogen diffusion barrier (10) the common plate ...

Description

The invention relates to a method for producing an integrated ferroelectric memory according to the stack cell principle, wherein transistors formed on a wafer, then deposited a first intermediate oxide and on this first intermediate oxide ferroelectric capacitors over the entire surface and then structured in one step and on the structured ferroelectric capacitors, a hydrogen diffusion barrier is deposited, wherein the ferroelectric capacitors are connected to its lower electrode through an underlying electrically conductive plug with a corresponding transistor electrode of a selection transistor. Such a procedure is over US 6 198 652 B1 known.

Either the stack principle as well as the offset principle are for the production of ferroelectric memory cells process steps necessary to structure the lower and upper capacitor electrode. The Structuring of new electrode materials also in microelectronics such as platinum for highly integrated memory modules are predominantly plasma processes using a photoresist mask. The material removal in the unmasked areas on the disk are made by sputtering under fire with chlorine and argon ions. To finest structures realize true to size to be able to It is necessary to change the structure of the resist mask without changes critical dimensions (CD = Critical Dimension) to be structured Transfer platinum layer. The sputtering attack of the ions leads However, especially with reactive gases to faceting, the is called bevel the lacquer mask and thus to a corresponding faceting when Structure transfer into the platinum. This faceting limits the smallest in platinum structuring achievable feature sizes. Out It is known from literature that pure chloroplasmas are the most powerful faceting cause.

With increasing argon content in the chlorine-argon gas mixture, however, increases the flank angle, i. the slope of the obtained platinum structures at. The use of pure inert gas as a process gas leads in plasma etching to virtually no faceting of the resist mask. As a consequence, the obtained etching edge and the speech positions (fences) the best possible angle (> 80 °) and you will find only a minimal Expansion. If one structures oxygen barrier, lower electrode, Ferroelectric and upper electrode in one step (One Step Etch), This is how high fences are formed.

Around an oxidation of the polysilicon or tungsten plug To prevent it between the plug and the lower capacitor electrode formed an oxygen barrier. Previous experiments have shown that with gradual structuring of the capacitor module, the is called a structuring of lower electrode, oxygen barrier, Ferroelectric and upper electrode of the capacitor in different Steps, the oxygen barrier from the side in an oxygen anneal (Annealing in oxygen atmosphere) is oxidized and thus the electrical connection of the lower Capacitor electrode is destroyed with the plug. Have more experiments shown a corresponding planar, unstructured oxygen barrier in the above mentioned Resists annealing process in oxygen atmosphere. How to get on showed is the overlap the lower capacitor electrode over the underlying oxygen barrier of great Importance. The larger this overlap The lower the oxygen barrier is oxidized from the side and the more capacitors work. From the literature, Technical Digest IEDM, 609 (1997), Technical Digest IEDM, 801 (1999) and Technical Digest IEDM, 617 (1997) it is known to deliver the whole capacitor, by applying all the precipitates and anneals used to make the ferroelectric Capacitor required be, on full-surface Layers executed be, in which case a maximum overlap between the lower capacitor electrode and oxygen barrier.

Out performed by the inventors Experiments and from the literature it is known that processes, in which hydrogen is released or used, leads to a degradation lead the ferroelectric, such as in depositions of CVD and PECVD oxides, tungsten CVD or forming gas annealing. To such a degradation of the ferroelectric To avoid hydrogen diffusion barriers (English: EBL = Encapsulation Barrier Layer).

Just few manufacturers structure the oxygen barrier, the lower one Capacitor electrode, the ferroelectric and the upper capacitor electrode in one step (OSSI = One Step Etch Stack Integration). After this one-step structuring is usually using the upper capacitor electrode connected to a tungsten / aluminum metallization.

According to EP 0 920 054 A1 the capacitor module is also structured one-step, which corresponds to the OSSI principle mentioned above. The so-called "protective film" consists for example of SiO ₂ or Si ₃ N ₄ . At least the latter material acts as a hydrogen diffusion barrier and in this document is applied directly over the upper capacitor electrode and sidewalls of the ferroelectric capacitor structure.

Also in JP 11-054718 A accordingly US 6,144,060 the OSSI principle is used to make a ferroelectric capacitor. Here, a buffer layer of aluminum oxide is used as a hydrogen diffusion barrier, which is difficult to etch.

DE 198 29 300 A1 shows in 2 a diffusion preventing layer also formed directly on the upper capacitor electrode and on the sidewalls of the ferroelectric capacitors. In column 4 in the second paragraph of this document, it is stated with respect to this diffusion prevention layer that oxide layers, a silicon nitride layer, TiO ₂ , SiO ₂ etc. can be used for this purpose. Of these materials, silicon nitride acts as a hydrogen diffusion barrier.

A similar process in which a hydrogen diffusion barrier is deposited directly over the ferroelectric capacitor will be discussed with reference to FIG 1 explained.

According to 1 is based on the OSSI principle one-step structuring of a ferroelectric capacitor module 1 directly above the condenser 1 a non-conductive hydrogen diffusion barrier 10 deposited. This hydrogen diffusion barrier (or EBL) may consist of one or more layers. Above the hydrogen diffusion barrier 10 is then a (for example) made of silicon oxide (second) intermediate oxide (ZOx) 3 applied. This layer system is then polished down with a stop on platinum, so that the upper platinum electrode of the capacitor module 1 exposed. It should be noted that the ferroelectric capacitor module 1 from the upper capacitor electrode 6 , the ferroelectric 5 and the lower capacitor electrode 4 consists. Between an underlying polysilicon plug 8th , for the electrical connection of the lower capacitor electrode 4 with an electrode (not shown) of a selection transistor through a first intermediate oxide layer 2 made of SiOx, and the lower capacitor electrode 4 lies an oxygen diffusion barrier 7 , From the selection transistor, a gate electrode G Darge is. In OSSI etching, it is not possible to overlap the lower capacitor electrode 4 over the oxygen diffusion barrier 7 to produce at each capacitor. However, by having the O ₂ anneal done before the capacitors are patterned with OSSI etch, the overlap is still maximal, as large as the wafer.

Alternatively, for polishing off the second intermediate oxide 3 and the hydrogen diffusion barrier 10 existing layer system with stop on the noble metal, such as platinum upper capacitor electrode 6 (see arrows P), it is also possible to polish down only down to the hydrogen diffusion barrier and then with the help of a litho plane and an etch the connection to the upper capacitor electrode 6 to open. It has to be mentioned that the precious metal platinum is given by way of example only for a noble metal / metal oxide. There are alternative methods in which the electrodes eg consist of IrOx.

Now a common plate (not shown) consisting of platinum can be deposited, followed by a post-anneal (PoA) for conditioning the hydrogen diffusion barrier 10 be performed.

Indeed The post-anneal (PoA) may also be prior to the deposition of the common plate carried out become. This can be for The Common Plate use other materials that do not have oxygen at 500 to 800 ° C withstand and at the same time are permeable to it. examples for Such materials are Al, Cu, Ti, TiON, TaSiN, which is advantageous the use of Ti, TiON, TaSiN is, as these themselves barrier properties to hydrogen exhibit.

In the preamble of claim 1 disclosing document US 6 198 652 B1 shows in particular 39 and the related description describes a method for manufacturing a stacked-cell integrated ferroelectric memory in which the plate electrode 20 TiN is what is a hydrogen diffusion material. The same applies to the embodiment of 41 This document in which the plate electrode also contains a Ti layer.

It It is an object of the invention to provide a generic manufacturing method for integrated Specify ferroelectric semiconductor memory, which has the advantages a one-step structuring of the capacitor modules (OSSI structuring) with a process-technically favorable and in terms of their hydrogen diffusion barrier properties secure integration of such an EBL layer connects.

These Task is solved according to the claim.

Characterized in that according to the invention, the hydrogen diffusion barrier is formed from at least one layer of a non-conductive material and applied over the common plate, the hydrogen diffusion barrier, the common plate and the second intermediate oxide layer over the entire surface covered, and then over the hydrogen diffusion barrier over the entire surface of a third intermediate oxide layer is divorced and an opening is formed by the third intermediate oxide layer and by the hydrogen diffusion barrier for producing an electrical contacting of the common plate with a metallization to be formed over the third intermediate oxide layer, a process-technically simple and in terms of their hydrogen diffusion barrier properties safe hydrogen diffusion barrier layer is integrated into the manufacturing process.

The Hydrogen diffusion barrier according to the invention (EBL) consists of at least one layer of a non-conductive Material. However, the hydrogen diffusion barrier can also be made out consist of several such layers. Subsequently, a post-anneal (PoA) for conditioning the hydrogen diffusion barrier. But the post-anneal can also be before deposition of the common plate carried out will. This will make the use of other materials for the common plate allows which do not withstand an oxygen anneal at 500 to 800 ° C and thereby at the same time for the Oxygen permeable are. examples for suitable materials for the common plates are Al, Cu, Ti, TiON, TaSiN, and other materials. Advantageous is the use of Ti, TiON, Ta-SiN, as these themselves barrier properties across from Have hydrogen.

If the common plate itself does not consist of a hydrogen diffusion barrier existing material or is small-scale, on the common plate a hydrogen diffusion barrier layer are applied. For that both can conductive than also non-conductive Materials are used.

in the Trap that over the common plate formed a non-conductive hydrogen diffusion barrier layer the latter must be etched through when the via between Common Plate and the following Etched metallization becomes. In case of a conductive Hydrogen diffusion barrier layer this is not required however, an interruption of this hydrogen diffusion barrier layer outside of the cell field to shorts in the periphery to avoid.

The inventive method is in one embodiment Referring to the accompanying drawings explained in more detail.

1 shows a schematic sectional view of a non-invention computed comparative example of OSSI structuring of a ferroelectric capacitor with a directly over deposited dielectric hydrogen diffusion barrier layer

2 shows an embodiment of a manufacturing method according to the invention, in which a hydrogen diffusion barrier layer is formed over a common plate, which was applied for contacting the upper capacitor electrode with a metallization (not shown).

In 2 is in a similar sectional view as in 1 a basic embodiment of a ferroelectric capacitor formed by the manufacturing method according to the invention illustrated. Again, a ferroelectric memory cell has been fabricated in a stacked fashion, with transistors (not shown) formed on a wafer being formed from an SiOx layer 2 are covered. A lower capacitor electrode over a transistor electrode (not shown) 4 a structured according to the OSSI principle in one step ferroelectric capacitor module 1 is an electrically conductive oxygen barrier 7 through a conductive polysilicon plug 8th in communication with said transistor electrode.

At the in 2 shown embodiment is the deposition of a hydrogen diffusion barrier directly above the capacitor module 1 has been dispensed with. Instead, a hydrogen diffusion barrier is EBL 10 with at least one non-conductive layer on the common plate 11 applied. It can be used for the hydrogen diffusion barrier 10 both conductive and non-conductive materials are used. The non-conductive hydrogen diffusion barrier layer 10 must together with a same covering (third) intermediate oxide layer 12 be etched through when the Via 13 for making a conductive connection between the common plate 11 and a metallization level (not shown).

1

ferroelectric capacitor module

2

first intermediate oxide

3

second intermediate oxide

4

lower capacitor electrode

5

ferroelectric

6

upper capacitor electrode

7

oxygen barrier

8th

Polyplug

10

Hydrogen diffusion barrier layer

11

Common Plate

12

third intermediate oxide

13

Via

P

polishing step

G

gate electrode

Claims (3)

Method for producing an integrated ferroelectric memory according to the stack cell principle, wherein transistors are formed on a wafer, then a first intermediate oxide ( 2 ) and deposited on this first intermediate oxide ( 2 ) ferroelectric capacitors ( 1 ) and then structured in one step and over the structured ferroelectric capacitors ( 1 ) a hydrogen diffusion barrier ( 10 ; 11 ) is deposited, wherein the ferroelectric capacitors ( 1 ) with its lower electrode ( 4 ) by an underlying electrically conductive plug ( 8th ) are connected to a corresponding transistor electrode of a selection transistor, and after the structuring of the ferroelectric capacitors ( 1 ) a second intermediate oxide layer covering this ( 3 ) and then up to the upper capacitor electrode ( 6 ) is polished and above it an exposed upper capacitor electrode ( 6 ) covering and electrically contacting common plate ( 11 ), characterized in that the hydrogen diffusion barrier ( 10 ) formed from at least one layer of a non-conductive material and above the common plate ( 11 ), the hydrogen diffusion barrier ( 10 ) the common plate ( 11 ) and the second intermediate oxide layer ( 3 ) and then over the hydrogen diffusion barrier ( 10 ) over the entire surface a third intermediate oxide layer ( 12 ) and an opening ( 13 ) through the third intermediate oxide layer ( 12 ) and the hydrogen diffusion barrier ( 10 ) for producing an electrical contacting of the common plate ( 11 ) with one above the third intermediate oxide layer ( 12 ) is formed to be formed metallization. Manufacturing method according to claim 1, characterized in that the common plate ( 11 ) consists of Ti or TiON or TaSiN. Manufacturing method according to one of claims 1 or 2, characterized in that further comprises a between the lower capacitor electrode ( 4 ) and the plug ( 8th ) oxygen barrier ( 7 ) in the structuring of the ferroelectric capacitors ( 1 ) is formed.