DE10116875A1 - Production of an integrated ferroelectric storage device comprises depositing an intermediate oxide, forming ferroelectric capacitor module on intermediate oxide, structuring, and depositing hydrogen diffusion barrier on structured module - Google Patents

Abstract

Production of an integrated ferroelectric storage device comprises depositing an intermediate oxide (2); forming a ferroelectric capacitor module (1) on the intermediate oxide; structuring; and depositing a hydrogen diffusion barrier (10) on the structured module. Preferred Features: An oxygen barrier lying between the lower capacitor electrode (4) and the plug (8) of the module is formed during the structuring of the capacitor. The hydrogen diffusion barrier is made from a non-conducting material.

Description

The invention relates to a method for producing a integrated ferroelectric memory according to the stack cell len principle, with transistors formed on a wafer, then deposited and on a first intermediate oxide this first intermediate oxide, the ferroelectric condensate door modules are manufactured using their lower electrical de by an underlying electrically conductive plug with a corresponding transistor electrode of a selection transistor are connected.

Both with the stack principle and with the offset cell principle are used to manufacture ferroelectric memory cells Process steps necessary to get the lower and upper condensate structure gate electrode. The structuring of the too new electrode materials in microelectronics, such as Example platinum for highly integrated memory modules follows with plasma processes predominantly using one Photoresist mask. The material removal in the unmasked Areas on the disc are done by sputtering under Bombardment with chlorine and argon ions. The finest structures To be able to realize true to size, it is necessary to Structure of the paint mask without changing the critical. dimen solutions (CD = critical dimension) on the structure to be structured Transfer platinum layer. The sputter attack of the ions leads to a facet, especially with reactive gases tion, that means beveling the paint mask and thus too a corresponding faceting in the structural transfer into Platinum. This faceting limits that of platinum structuring the smallest achievable structure sizes. From the Literature is known to be pure chloroplasmic the strongest Cause faceting.  

As the proportion of argon in the chlorine-argon gas mixture increases the flank angle, on the other hand. H. the steepness of the he holding platinum structures. The use of pure Noble gas as a process gas leads to practical use in plasma etching no faceting of the paint mask. As a consequence, the preserved etching edge and the speech positions (fences) the best possible angle (<80 °) and you find only a minimal one Expansion. If one structures the oxygen barrier, lower one Electrode, ferroelectric and top electrode in one Step (One Step Etch), so high fences are formed.

To prevent oxidation of the plug made of polysilicon or tungsten, an oxygen barrier is formed between the plug and the lower capacitor electrode. Experiments to date have shown that with step-by-step structuring of the capacitor module, that is to say structuring of the lower electrode, oxygen barrier, ferroelectric and upper electrode of the capacitor in different steps, the oxygen barrier from the side in the case of an oxygen anneal (tempering in an oxygen atmosphere) is oxidized and thus the electrical connection of the lower capacitor electrode to the plug is destroyed. Further tests have shown that a corresponding planar, unstructured oxygen barrier withstands the tempering process mentioned above in an oxygen atmosphere. As has further been shown, the overlap of the lower capacitor electrode over the underlying oxygen barrier is of great importance. The greater this overlap, the less the oxygen barrier is oxidized from the side and the more capacitors work. It is known from the literature, Technical Digest IEDM, 609 ( 1997 ), Technical digest IEDM, 801 ( 1999 ) and Technical Digest IEDM, 617 ( 1997 ) to produce the entire capacitor in only one etching step. All depositions and tempering that are required to manufacture the ferroelectric capacitor are carried out on layers covering the entire surface, in which case there is a maximum overlap between the lower capacitor electrode and the oxygen barrier.

From experiments carried out by the inventors and from It is known in the literature that processes in which water becomes free or is used for degradation of the ferroelectric lead, for example in the case of deposition of CVD and PECVD oxides, tungsten CVD or forming gas Tempering. To such a degradation of the ferroelectric to avoid accumulation, hydrogen diffusion barriers (English: Encapsulation Barrier Layer) used.

Few manufacturers structure the oxygen barrier, the lower capacitor electrode, the ferroelectric and the upper capacitor electrode in one step (OSSI = One Step Etch stack integration). According to this one-step structure is usually the upper capacitor electrode connected with a tungsten / aluminum metallization.

All currently commercially available products with ferroe Electrical layers are based on the offset cell principle built up and have an integration density of only a few Kilobytes up to a megabyte. The integration of after the ferroelectric memory cell based on the stack principle len, for example using the OSSI principle in an argonate made with a protective hydrogen barrier is not yet known.

It is therefore an object of the invention, a generic Manufacturing process for integrated ferroelectric half to specify the main memory that has the advantages of a single step structure of the capacitor modules (OSSI structure tion) with a process-technically favorable and in terms of  secure their hydrogen diffusion barrier properties Integration of such an EBL layer connects.

This task is solved according to the requirements.

The fact that according to the invention the capacitor modules with ih rer lower and upper electrode and the intermediate Ferroelectric manufactured over the entire surface and subsequently in one Be structured step and then via the structured ferroelectric capacitors all over a water diffusion barrier is deposited, a pro technically simple and in terms of their hydrogen diffusion barrier properties secure hydrogen diffuser barrier layer integrated into the manufacturing process. The above-mentioned integration possibility of the EBL over one ferroelectric capacitor module can be used in various apply process variants of capacitor structuring, for example with OSSI structuring with argon or with Hot OSSI method, that is, hard mask etching with hot ß cathode, with no fences.

If there is an oxygen barrier between the lower condensate gate electrode and the plug is applied, the one gradual structuring of the ferroelectric capacitor modules cause the lower capacitor electrode to Oxygen barrier evenly overlapped.

The hydrogen diffusion barrier (EBL) according to the invention be consists of at least one layer, for example non-conductive material. The hydrogen diffusion However, the barrier can also consist of several layers. If a conductive dimension for the hydrogen diffusion barrier material must be selected if it is directly above the structure dated capacitor module is deposited under the lead a layer of hydrogen diffusion barrier trical layer to be short-circuited  between the upper and lower capacitor electrodes prevent.

The method described here shows two embodiments play on. In the first embodiment, according to the Structuring the capacitor module directly above the condenser a non-conductive hydrogen diffusion barrier deposited and on it, for example made of silicon oxide existing intermediate oxide applied (second intermediate oxide layer). This layer system is then stopped on Pla tin (the material of the upper capacitor electrode) polished so that the upper capacitor electrode is exposed.

There is also the possibility of only up to the hydrogen dif to polish down the fusion barrier and then with With the help of a litho level and an etching structure the An to open the top capacitor electrode. Well now a common plate consisting of platinum is deposited and then a post-anneal (PoA) for conditioning the hydrogen diffusion barrier. The Post-anneal can also take place before the common plate is deposited be carried out. This will prevent other Ma materials for the common plate, which enables a sour Fabric withstand at 500 to 800 ° C and not are permeable to oxygen at the same time. Examples suitable materials for the common plate are then A1, Cu, Ti, TiON, TaSiN, and other materials. It is advantageous the use of Ti, TiON, TaSiN, since these themselves are Barrie have re-properties towards hydrogen.

So if the Common Plate is a hydrogen diffuser onsbarriere acting material can be selected with a second embodiment on the deposition of a what Hydrogen diffusion barrier directly above the capacitor module waived and instead only the Common Plate as Serve as a hydrogen diffusion barrier. It should, however  the common plate should be as large as possible to ensure the best possible Ensure shielding against hydrogen.

Furthermore, if the common plate itself is not attached to a existing material as a hydrogen diffusion barrier stands or is small, on the common plate a what Hydrogen diffusion barrier layer can be applied. Therefore can both conductive and non-conductive materia lien are used.

In the event that a non-conductive over the common plate Hydrogen diffusion barrier layer must be formed the latter can be etched through if the via between Com mon plate and the subsequent metallization level etched becomes. In the case of a conductive hydrogen diffusible This is not necessary, but a sub-layer refraction of this hydrogen diffusion barrier layer except half of the cell field to prevent short circuits in the periphery avoid.

The method according to the invention is based on two principles Embodiments with reference to the accompanying Drawing explained in more detail.

Fig. 1 shows a schematic sectional view of a first embodiment of an OSSI structure of a ferroelectric capacitor with a directly deposited dielectric hydrogen diffusion barrier layer and

Fig. 2 shows a second embodiment of a manufacturing method according to the invention, in which a hydrogen diffusion barrier layer is formed over a common plate, which was brought to contact with the upper capacitor electrode with a (not shown) metallization level.

First embodiment

According to FIG. 1, a non-conductive hydrogen diffusion barrier 10 is deposited directly over the capacitor 1 according to the one-step structuring of a ferroelectric capacitor module 1 based on the OSSI principle. This hydrogen diffusion barrier (or EBL) can consist of one or more layers. A (second) intermediate oxide (ZOx) 3, for example consisting of silicon oxide, is then brought over the what diffusion barrier 10 . This layer system is then polished down with a stop on platinum, so that the upper platinum electrode of the capacitor module 1 is exposed. It should be noted that the ferroelectric capacitor module 1 consists of the upper capacitor electrode 6 , the ferroelectric 5 and the lower capacitor electrode 4 . Between an underlying polysilicon plug 8 , which leads to the electrical connection of the lower capacitor electrode 4 to an electrode (not shown) of a selection transistor through a first intermediate oxide layer 2 made of SiOx, and the lower capacitor electrode 4 is an oxygen diffusion barrier 7 . A gate electrode G is shown from the selection transistor. In the OSSI etching it is not possible to produce an overlap of the lower capacitor electrode 4 over the oxygen diffusion barrier 7 for each capacitor. However, because the O ₂ annealing takes place before the capacitors are patterned with OSSI etching, the overlap is still at a maximum, namely as large as the wafer.

Alternatively to the polishing down of the second inter mediate oxide 3 and the hydrogen diffusion barrier 10 existing layer system with stop on the made of precious metal, for. B. platinum existing upper capacitor electrode 6 (see arrows P), there is alternatively also the possibility to polish down only to the hydrogen diffusion barrier and then open the connection to the upper capacitor electrode 6 with the aid of a litho level and an etching. It has to be mentioned that the precious metal platinum is only given as an example for a precious metal / metal oxide. There are alternative methods in which the electrodes e.g. B. consist of IrOx.

Now a z. B. existing platinum (not shown) common plate and then a post-anneal (PoA) for conditioning the hydrogen diffusion barrier 10 are performed.

However, the post-anneal (PoA) can also be done before the parting common plate. Let it through other materials are used for the common plate, which cannot withstand oxygen at 500 to 800 ° C and are permeable to it at the same time. Examples for such materials are A1, Cu, Ti, TiON, TaSiN, where the use of Ti, TiON, TaSiN is advantageous because these themselves have barrier properties against hydrogen exhibit.

FIG. 2 shows a second basic embodiment of a ferroelectric capacitor formed with the manufacturing method according to the invention in a sectional view similar to that in FIG. 1. Again, a ferroelectric memory cell has been manufactured according to the stack principle, with transistors (not shown) formed on a wafer being covered by an SiOx layer 2 . A lower capacitor electrode 4 of a ferroelectric capacitor module 1, which is structured in one step according to the OSSI principle, lies above a transistor electrode (not shown) and is connected to said transistor electrode via an electrically conductive oxygen barrier through a conductive polysilicon plug 8 .

In the exemplary embodiment shown in FIG. 2, the deposition of a hydrogen diffusion barrier directly above the capacitor module 1 has been dispensed with. Instead, a hydrogen diffusion barrier EBL 10 is applied to the common plate 11 . Both conductive and non-conductive materials can be used for the hydrogen diffusion barrier 10 . In the case of a non-conductive hydrogen diffusion barrier layer 10 , this must be etched through together with a (third) intermediate oxide layer 12 covering the same, if the via 13 is produced to produce a conductive connection between the common plate 11 and a metallization layer (not shown). In the case of a conductive Wasserstoffdif fusion barrier layer 10, this etching is not erforder Lich while observing the hydrogen diffusion barrier layer 10 then outside the cell array interrupted in order to avoid short circuits in the periphery.

If, in a variant similar to that in FIG. 2, in which the common plate itself forms a hydrogen diffusion barrier, the deposition of an additional hydrogen diffusion barrier 10 is dispensed with, the common plate 11 should be as large as possible in order to ensure the best possible shielding against hydrogen ,

LIST OF REFERENCE NUMBERS

1

ferroelectric capacitor module

2

first intermediate oxide layer

3

second intermediate oxide layer

4

lower capacitor electrode

5

ferroelectric

6

upper capacitor electrode

7

oxygen barrier

8th

Polyplug

10

Hydrogen diffusion barrier layer

11

Common plate

12

third intermediate oxide layer

13

Via
P polishing step
G gate electrode

Claims (12)

1. A method for producing an integrated ferroelectric memory according to the stack-cell principle, wherein transistors are formed on a wafer, then a first intermediate oxide ( 2 ) is deposited and the ferroelectric capacitor modules ( 1 ) are produced on this first intermediate oxide their lower electrode ( 4 ) are connected by an underlying electrically conductive plug ( 8 ) to a corresponding transistor electrode of a selection transistor, characterized in that the ferroelectric capacitor modules ( 1 ) are produced over the whole area and then structured in one step, and that after that the structured ferroelectric capacitors ( 1 ) a hydrogen diffusion barrier ( 10 ) is deposited. 2. Manufacturing method according to claim 1, characterized in that a further between the lower capacitor de ( 4 ) and the plug ( 8 ) lying oxygen barrier ( 7 ) is formed during the structuring of the ferroelectric capacitors ge. 3. Manufacturing method according to claim 1 or 2, characterized in that the hydrogen diffusion barrier ( 10 ) is formed from at least one layer of a non-conductive material. 4. Manufacturing process according to one of the preceding claims, characterized in that
that the hydrogen diffusion barrier ( 10 ) is formed before the deposition of an electrically conductive common plate ( 11 ) connecting the upper capacitor electrodes ( 6 ),
that the hydrogen diffusion barrier (10), the upper electrode (6) and the side surfaces of the patterned capacitor modules and the first intermediate oxide (2) covered and that a second intermediate oxide layer (3) material diffusion barrier above the water (10) is deposited directly. 5. Preparation process according to claim 4, characterized in that the second intermediate oxide layer (3) and the hydrogen diffusion barrier (10) then to the upper-condensing sator electrode (6) are polished down to the upper Kon densatorelektrode (6) to expose. 6. Manufacturing method according to claim 4, characterized in that the second intermediate oxide layer ( 3 ) is polished down to the hydrogen diffusion barrier ( 10 ) and the hydrogen diffusion barrier is opened with a litho level and subsequent etching via the upper capacitor electrode ( 6 ). 7. Manufacturing method according to one of claims 5 or 6, characterized in that the upper capacitor electrode ( 6 ) contacting common plate is then deposited over the upper capacitor electrode and the second intermediate oxide ( 3 ). 8. The production method according to claim 1 or 2, characterized in that a ferecelectric capacitor modules ( 1 ) covering second intermediate oxide layer ( 3 ) is applied and then polished down to the upper capacitor electrode ( 6 ) and above that an exposed upper capacitor electrode ( 6 ) covering and electrically contacting common plate ( 11 ) is formed. 9. The production method according to claim 8, characterized in that the common plate ( 11 ) on all sides protrudes beyond the lateral limit of the upper capacitor electrode ( 6 ) and itself forms a hydrogen diffusion barrier by consisting of a conductive material acting as a barrier against hydrogen diffusion. 10. The production method according to claim 9, characterized in that the common plate ( 11 ) consists of Ti or TiON or TaSiON. 11. The production method according to claim 8, characterized in that the hydrogen diffusion barrier ( 10 ) is formed over the entire surface over the common plate ( 11 ) and the second intermediate oxide. 12. Production method according to one of claims 8 to 11, characterized in that a third intermediate oxide layer ( 12 ) is deposited over the entire area over the hydrogen diffusion barrier ( 10 ) and an opening ( 13 ) through the third intermediate oxide layer ( 12 ) and the hydrogen diffusion barrier ( 10 ) for the production an electrical contacting of the common plate ( 11 ) is formed with a metallization to be formed over the third intermediate oxide layer.