DE102004001853B3 - Fabrication of connection contacts of semiconductors for future nanotechnologies including deposition of contact layer on masking layer during later back polishing stage - Google Patents

Abstract

The invention provides a method for producing contacting connections comprising the steps of: a) providing a substrate (101) with electronic circuit units (102a, 102b) arranged thereon, wherein an intermediate layer (103) fills a gap between the electronic circuit units (102a, 102b) ; an insulating layer (104) is deposited on the electronic circuit units (102a, 102b) and deposited on the intermediate layer (103), a masking layer (105) is deposited on the insulating layer (104); and the masking layer (105) is patterned with a via structure (106); b) patterning a contacting region by means of the masking layer (105), wherein a contacting hole (112) is etched through the insulating layer (104) and the intermediate layer (103) to the substrate (101), wherein a portion of the substrate (101) corresponding to Via structure (106) is exposed; c) filling the contacting hole (112) with a via material (108); d) re-polishing the cover layer (107) deposited on the masking layer (105) to the masking layer (105); e) depositing a contacting layer (109) on the masking layer (105) and the via material, wherein the contacting layer (109) is electrically contacted with the via material (108); and f) structuring the contacting layer (109) together with the ...

Description

The The present invention relates to a method for producing Contacting connections in a semiconductor device that in particular application in a transition a currently deployed 110 nanometer technology to future 90 Nanometer or 70 nanometer technology finds.

From the US 6,008,123 It is known to form on an insulation layer of TEOS an etching mask of polysilicon layers for contact holes. The contacts are formed with barriers of Ti / TiN and tungsten and polished back with CMP until the etch mask is exposed. Then, the etch mask or the polishing stop is removed, and a metal layer and thereon an anti-reflection layer for subsequent lithography steps are formed. Such a method corresponds to the preamble of claim 1.

The EP 0 764 974 A1 teaches fabricating hard masks for RIE from polysilicon layers which are reduced in aperture radius, these hard masks being removed prior to deposition of the conductive layers. Furthermore, this document discloses that an almost flat surface is achieved by reflow of the BPSG layer.

The US 5,523,633 teaches the formation of a polysilicon layer on an insulating layer having a contact hole with which contact holes are formed as RIE hardmask. In these holes, contacts of Ti / TiN / W are formed, which are polished until the polysilicon layer is exposed. The insulation layer of BPSG is here subjected to a CMP to achieve a planar surface.

From the US 5,534,462 It is known that an adhesion layer of aluminum nitride, which has served as RIE mask or CMP stop, can be removed or left. The adhesive layer is insulating and can be left behind, since it does not involve a risk of electrical short circuits.

The DE 100 53 467 A1 discloses a method of forming contacts in integrated circuits wherein a liner is provided in a contact hole and then the hole is filled with contact material. Finally, the contact material is polished back to the surface of a surrounding insulating layer.

The DE 100 42 932 C2 discloses a method of making a metal contact in a dielectric wherein at least in the region surrounding the via is provided on the dielectric a CMP process readily removable auxiliary layer between the dielectric and a liner.

Farther The invention relates to an integration concept for the production of Kontaktierungsanschlüssen, at which the execution a masking layer opposite Hard masks is improved according to the prior art. Specific The invention relates to a method for producing contacting terminals, wherein a substrate having electronic circuit units provided and the substrate by means of a via material is electrically connected to a metallization level.

Especially becomes the method according to the invention for facilities the information storage used on a deep trench technology (Deep trench).

conventional Methods for making Kontaktierungsanschlüssen include essentially providing a substrate that is electronic Circuit units, a deposition of an intermediate layer to fill up the gap between the electronic circuit units, depositing an insulating layer on the electronic circuit units and on the intermediate layer and depositing a masking layer on the insulation layer.

The The object of the present invention is a process for making Kontaktierungsanschlüssen to ver simple, wherein a contacting layer with respect to a surface structure is improved and at the same time a good electrical connection is provided to the substrate.

These The object is achieved by a solved in claim 1 given method.

Further Embodiments of the invention will become apparent from the dependent claims.

One The essential idea of the invention is the process flows for Deposition and structuring of a masking layer with an anisotropic etching process for structuring a contacting layer in a metallization plane, for example, to combine in a zeroth metallization plane, in particular a chemical-mechanical polishing (CMP) process to stop on the masking layer, such that the insulating layer not damaged or in their surface structure is deformed.

in this connection It is advantageous that the masking layer, which is formed as a polysilicon hardmask can be used to optimize contact hole sizes. Further it is appropriate that due to a to be performed dry etching in the metallization level a masking layer in such a Layer thickness is provided, that the masking layer at a subsequent Polishing process for removing a cover layer is maintained. Thus, it is advantageous that two process flows by modifying the Layer thickness of the hard mask can be combined.

In the dependent claims find advantageous developments and improvements of respective subject of the invention.

According to one preferred embodiment of the present invention is according to the Step of filling the contacting hole with the via material a Contacting layer deposited on the masking layer, wherein the contacting layer with the via material electrically is connected.

According to one Another preferred embodiment of the present invention will before the step of filling the contacting hole with the via material a Cover layer on the according to the via structure exposed portion of the substrate and on the masking layer deposited.

It is advantageous in that the masking layer in such Layer thickness is provided that the masking layer at a polishing process for removing the cover layer remains.

According to one more Another preferred embodiment of the present invention will the contacting layer together with the remaining masking layer according to a structure of one on the contacting layer applied contacting layer mask structured to conductor tracks as contacting connections to form in a metallization level.

in this connection it may be appropriate in structuring the contacting layer together with the remaining masking layer according to a structure the contacting layer mask applied to the contacting layer, around interconnects as Kontaktierungsanschlüsse in a metallization to form an overetch in provided under the masking layer insulation layer becomes.

The Coating and etching processes according to the present Invention are advantageously carried out in a multi-frequency parallel plate reactor.

According to one more Another preferred embodiment of the present invention will the step of etching the at least one contacting hole through the insulating layer and an intermediate layer to the substrate by an anisotropic etching process carried out. It is advantageous that the anisotropic etch process be considered a reactive ion etching (RIE = Reactive Ion Etching) is provided.

The Substrate is preferably made of a silicon material, and Preferably, the substrate is made of crystalline silicon.

Conveniently, the cap layer is provided on the exposed portion of the titanium and / or titanium nitride substrate such that the cap layer forms a titanium silicide (Ti _x Si _y ) compound with the silicon material of the substrate.

Preferably, the step of etching the at least one contact hole through the insulating layer and an intermediate layer to the substrate has a high selectivity to silicon nitride (Si _x N _y ).

A deposition of the insulating layer on the electronic circuit units and on the intermediate layer is preferably made of a tetraethyl orthosilicate (TEOS) material be provided, wherein a silicon dioxide layer (SiO ₂ ) is applied as an insulating layer.

Preferably becomes the masking layer deposited on the insulating layer as a polysilicon hardmask.

Further become the via material and the contacting layer, which are electrically connected to each other, made of a tungsten material educated.

embodiments The invention is illustrated in the drawings and in the following Description closer explained.

In show the drawings:

1 a substrate having electronic circuit units disposed thereon according to an embodiment of the present invention;

2 the arrangement of 1 that with a Intermediate layer, an insulating layer and a Hartmaskierungsschicht is provided;

3 in the 2 shown arrangement, wherein the masking layer has been provided with a via structure;

4 in the 3 shown arrangement after an etching process, wherein the via structure has reached the surface of the substrate;

5 the via structure filled with a via material 4 ;

6 in the 5 shown arrangement, wherein an inserted cover layer and the masking layer are removed on the top of the insulating layer;

7 in the 5 shown arrangement, wherein the cover layer is removed and the masking layer on top of the insulating layer 104 has remained;

8th the arrangement provided with a contacting layer on the upper side of the insulating layer 6 ;

9 the arrangement provided with a contacting layer on top of the masking layer 7 ;

10 in the 8th arrangement shown, wherein the contacting layer is structured in a metallization; and

11 the arrangement of 9 wherein the contacting layer is patterned together with the remaining masking layer in the metallization plane.

In the same reference numerals designate the same or functionally identical Components or steps.

1 shows a substrate 101 For example, made of a crystalline silicon material. As in 1 shown schematically are two electronic circuit units 102 . 102b on the substrate 101 applied.

It should be noted that the electronic circuit units shown 102 . 102b a gate oxide layer, a tungsten / tungsten nitride gate, and other gate stack and silicon nitride (Si _x N _y ) layers as an example to form a circuit functional unit as known to those of ordinary skill in the art Area of integrated circuits is common.

The exact structure of the electronic circuit units 102 . 102b is not explained in more detail below, since it is not essential to the representation of the method according to the invention for the production of Kontaktierungsanschlüssen.

As in 2 shown, the in 1 shown arrangement consisting of the substrate 101 and the two electronic circuit units 102 . 102b exists, with an intermediate layer 103 provided, which consists for example of boron phosphorus-doped Si glass and is electrically insulating. Here, the intermediate layer is used 103 as a filler material attached to the top of the electronic circuit units 102 . 102b concludes. Furthermore, the filling acts in the form of the intermediate layer 103 between the electronic circuit units 102 . 102b as a dielectric.

The filling material of the intermediate layer 103 is tempered to close cavities and / or to anneal the material. After a deposition of the intermediate layer 103 This is up to the stack (GC stacks) of the electronic circuit units 102 . 102b polished by means of chemical-mechanical polishing (CMP).

On a wafer planarized in this way, an insulating layer is subsequently formed 104 applied, which has a layer thickness of, for example, 100 nanometers (nm). Preferably, the thickness of the insulating layer is 104 between 0 and 400 nm. The insulation layer 104 acts as another dielectric and is provided of tetraethyl orthosilicate (TEOS) material, wherein the insulating layer is formed as a silicon dioxide layer (SiO ₂ ) layer.

After deposition in the insulation layer 104 becomes a masking layer 105 on the insulation layer 104 deposited. Preferably, the masking layer exists 105 of silicon provided in either amorphous or polycrystalline form with a preferred thickness of 120 nm. The layer thickness of the masking layer is preferably 30 to 300 nm.

3 shows the in 2 illustrated arrangement, here a via structure 106 in the masking layer 105 is available. The via structure 106 is usually by coating the masking layer 105 with photoresist and exposing and developing the photoresist generated. The via structure 106 becomes in the masking layer 105 provided at those locations at which contact holes are to arise. The lithography used is preferably based on a zigen hard mask, a double exposure with different masks is also possible.

4 shows the in 3 illustrated arrangement after performing an anisotropic dry etching process. For the dry etching process, preferably an etching chemistry is used which etches silicon oxide and which has a high selectivity for Si _x N _y (silicon nitride). In the event that a Si _x N _y - or a SiON liner was used, a SiN etching is carried out as a conclusion. As in 4 was shown, a contacting hole 112 according to a via structure 106 through the insulation layer 104 and the intermediate layer 103 to the substrate 101 etched.

Subsequently, the contact hole 112 , as in 5 illustrated with a via material 108 filled. To the substrate 101 It is possible to protect a cover layer 107 before the step of filling the contacting hole 112 with the via material 108 deposit. The cover layer 107 is preferably made of titanium (Ti) and / or titanium nitride (TiN) and is annealed in a nitrogen-containing atmosphere after deposition. Upon annealing, the titanium at the contact hole bottom converts to titanium silicide (Ti _x Si _y ) such that sufficient conductivity exists between the substrate 101 and the via material 108 provided. Through the process by which the cover layer 107 on the substrate 101 is applied in the contact hole bottom, a similar cover layer 107 on the masking layer 105 applied. The on the masking layer 105 applied cover layer 107 is then removed in a chemical-mechanical polishing process, so that now the via material 108 on the surface of the insulation layer 104 remains as in 6 shown, or the masking layer 105 on the surface of the insulation layer 104 remains as in 7 shown.

A basic idea of the invention is that when the in 7 A chemical-mechanical polishing (CMP) process is applied sharply to the masking layer 105 stops, such that the insulation layer 104 not damaged or deformed in its surface structure. Furthermore, there is the advantage of leaving the masking layer 105 on the insulation layer 104 in that a removing step (for example, an etching step) for removing the masking layer 105 is avoided. This provides a simplified process flow.

The completion of the contacting terminals will be described below with reference to FIGS 8th to 11 to shorten a representation, with reference to the 1 to 7 described components and steps will not be described again.

In the 8th and 9 is shown on the instructions of the 6 respectively. 7 a contacting layer 109 has been applied, wherein the contacting layer 109 with the via material 108 electrically connected. The layer thickness of the deposited contacting layer 109 then corresponds to a layer thickness of a metallization M, for example, a zeroth Metallisierungsebene M0 in which conductor tracks are formed as Kontaktierungsanschlüsse. At a transition of the process from the in 8th respectively. 9 shown states in the in 10 respectively. 11 The states shown for complete planarization and optical decoupling from the substrate to the contacting layer 109 an antireflection layer (not shown) is applied, followed by a metallization level lithography process.

Finally, as in the 10 respectively. 11 at a reference number 110 shown contacting layer structures introduced. This is preferably done by the application of a further masking layer in the form of a contacting layer hardmask 111 , With an etching process, the printed conductors in the metallization level M, for example M0 printed conductors in the zeroth metallization level M0, are now produced.

Furthermore, it is permissible that when structuring the contacting layer 109 together with the remaining masking layer 105 according to a structure of the contacting layer 109 applied contacting layer hardmask 111 in order to form conductor tracks as contacting terminals of a metallization level M, an overetching into the under masking layer 105 lying insulating layer is provided.

The inventive method for making Kontaktierungsanschlüssen further has the advantage on that one fill up the spaces between of conductive lines provided with a dielectric of a low dielectric constant besides being able to cavities can be generated between the tracks. Thus, it is appropriate that a design chosen that can be everywhere provides constantly small interconnect spaces. This arises the advantage that reduces couplings between the tracks become.

In an etching of the at least one contacting hole 112 through the insulation layer 104 and the intermediate layer 103 is an aspect ratio between a stack height and a width of a finished contact hole is a critical size. According to the invention, the insulating layer 104 with a thickness of 100 nm of TEOS, the tracks not being in the isolation layer as in a so-called dual damascene process, as is known to those of ordinary skill in the art of painting and etching technology 104 etched in, but on the insulating layer 104 be generated. Advantageously, this can be used to reduce an overall stacking height.

The use of the RIE process instead of the dual damascene process leads to an advantageous aspect ratio of the arrangement, wherein the on the insulating layer 104 left masking layer 105 a hard polishing stop in a tungsten chemical mechanical polishing is made possible.

Even though the present invention above based on preferred embodiments It is not limited to this, but in many ways modifiable.

Also the invention is not limited to the aforementioned applications limited.

101

substratum

102a, 102b

electronic circuit units

103

interlayer

104

insulation layer

105

masking layer

106

via structure

107

cover layer (Liner)

108

Durchkontaktierungsmaterial

109

contacting

110

Kontaktierungsschichtstruktur

111

Contacting layer mask

112

contact hole

M (0)

(Zero) metallization

Claims (14)

Method for producing contacting connections in a semiconductor component, comprising the steps of: a) providing a substrate ( 101 ) with electronic circuit units ( 102 . 102b ), wherein an insulation layer ( 104 ) on the electronic circuit units ( 102 . 102b ) is deposited; a masking layer ( 105 ) on the insulation layer ( 104 ) is deposited; and the masking layer ( 105 ) with a via structure ( 106 ) is structured; b) structuring a contacting region by means of the masking layer ( 105 ), wherein a contacting hole ( 112 ) through the insulation layer ( 104 ) to the substrate ( 101 ) is etched, wherein a portion of the substrate ( 101 ) according to the via structure ( 106 ) is exposed; c) filling the contacting hole ( 112 ) with a via material ( 108 ); d) polishing back one on the masking layer ( 105 ) deposited cover layer ( 107 ) to the masking layer ( 105 ); e) depositing a contacting layer ( 109 ) on the via material ( 108 ), wherein the contacting layer ( 109 ) with the via material ( 108 ) is contacted electrically; characterized in that in step d) the deposition of a contacting layer ( 109 ) also on the masking layer ( 105 ), and in step e) the structuring of the contacting layer ( 109 ) together with the remaining masking layer ( 105 ) according to a structure of a on the contacting layer ( 109 ) contacting layer mask ( 111 ) is carried out to form interconnects as Kontaktierungsanschlüsse in a Metallisierungsebene (M). Method according to claim 1, characterized in that the cover layer ( 107 ) on the exposed portion of the substrate ( 101 ) and on the masking layer ( 105 ) is deposited. Method according to claim 1, characterized in that the step d) of a polishing back on the masking layer ( 105 ) deposited cover layer ( 107 ) to the masking layer ( 105 ) comprises a chemical mechanical polishing (CMP), which on or in the masking layer ( 105 ) stops. A method according to claim 2, characterized in that on the exposed portion of the substrate ( 101 ) and on the masking layer ( 105 ) deposited cover layer ( 107 ) of titanium (Ti) and / or titanium nitride (TiN). Method according to claim 1 or 3, characterized in that the masking layer ( 105 ) is provided in such a layer thickness that the masking layer ( 105 ) in a polishing process for removing the cover layer (FIG. 107 ) is at least partially preserved. A method according to claim 1, characterized in that in the structuring of the contacting layer ( 109 ) together with the remaining masking layer ( 105 ) according to a structure of the contacting layer ( 109 ) contacting layer mask ( 111 ) in order to form interconnects as contact connections in a metallization plane (M), an overetching into the under the masking layer (FIG. 105 ) insulating layer ( 104 ) provided. Method according to one of the preceding claims, characterized characterized in that the coating and etching processes in a multiple frequency parallel plate reactor carried out become. Method according to Claim 1, characterized in that etching of the at least one contacting hole (b) is carried out in step b). 112 ) through the insulation layer ( 104 ) and one between substrate ( 101 ) and insulation layer ( 104 ) intermediate layer ( 103 ) to the substrate ( 101 ) is performed by means of a reactive ion etching process. Method according to claim 1, characterized in that the substrate ( 101 ) is provided from a silicon material. Method according to claim 3 and 9, characterized in that the cover layer ( 107 ) on the exposed portion of the substrate ( 101 ) made of titanium (Ti) and / or titanium nitride (TiN) with the silicon material of the substrate ( 101 ) a compound titanium silicide (Ti _x Si _y ) received. Method according to Claim 1, characterized in that etching of the at least one contacting hole (b) is carried out in step b). 112 ) through the insulation layer ( 104 ) and one between substrate ( 101 ) and insulation layer ( 104 ) provided intermediate layer ( 103 ) to the substrate ( 101 ) has a high selectivity towards silicon nitride (Si _x N _y ). A method according to claim 1, characterized in that on the electronic circuit units ( 102 . 102b ) and on the intermediate layer ( 103 ) isolated insulation layer ( 104 ) is provided from a tetraethylorthosilicate (TEOS) material, wherein a silicon dioxide layer (SiO ₂ ) is used as the insulating layer ( 104 ) is applied. A method according to claim 1, characterized in that on the insulating layer ( 104 ) deposited masking layer ( 105 ) is provided as a polysilicon hardmask. Method according to claim 1, characterized in that the via material ( 108 ) and the contacting layer ( 109 ) are formed from a tungsten material.