DE1076181B - Arrangement for decoding PCM signals - Google Patents

Description

GERMAN

The invention relates to an arrangement for decoding PCM signals according to a binary Code are formed, which is particularly suitable for multi-channel systems based on the time division multiplex method.

With pulse code modulation (PCM), the amplitude range to be transmitted is in amplitude steps divided. Each of these amplitude levels becomes a characteristic sequence of according to a code Assigned to impulses. The pulse sequence is then for each instantaneous value of the signal to be transmitted sent out whose associated amplitude level is closest to the instantaneous value.

Assuming a binary code according to which only two amplitude values occur in the code pulse sequences, each code pulse sequence must consist of M = log ₂ m code pulses if one wishes to distinguish between m amplitude levels in the signal range. For any amplitude level N , the associated pulse sequence results from the series

N = -a _n _ _t 2 "-i + ... + O ₁ 2i + o ₀ 2". (1)

Here, a _n _ _± ... α _{0 are} the amplitudes of the individual code pulses, which in the binary code are, for example, +1 or equal to - 1.

So z. B. for a code with five code pulses per pulse train 32 amplitude levels between +31 and - 31 differentiate. The amplitude level + 13 is then given by + l3 = + l -2 * -1 * 2 ³ +1 * 22 +1 * 2 ¹ - 1 * 2 °, ie by the pulse sequence +1, -1, +1, +1 , —1 shown. The value of the individual pulses in the code pulse sequence is graded according to powers of 2.

In the PCM decoder, the amplitude level coded in the coder is then converted by multiplying the »Yes, No «- or» + 1, —1 «statement of the code impulses with a weighting factor (power of 2) and then Addition is restored in accordance with the relationship (1) given above.

They are already different, according to these general ones Working principle PCM decoding circuits become known, so z. B. a circuit arrangement, with a constant current source controlled by the PCM pulses (Pentode) supplies a certain charge to a storage circuit, which then, and thus the The voltage at the storage tank decreases exponentially over time. The PCM pulses are in the memory added and multiplied by its weighting factor as the voltage at the storage unit drops, see above that after the last code pulse of a pulse train a corresponding to the originally coded amplitude value Tension arises. The voltage across the accumulator is determined by a -in series with the accumulator switched i? CL circuit a weak sinus component

Arrangement for decoding
of PCM signals

Applicant:

Standard electrical system Lorenz

Corporation,

Stuttgart-Zuffenhausen,

Hellmuth-Hirth-Str. 42

Dr.-Ing. Hans Marko, Stuttgart-Stammheim,
has been named as the inventor

nent superimposed so that the tangent of the resulting voltage curve parallel to several points in time runs along the time axis and thus the voltage on the storage tank is constant for a certain period of time. By this measure is the control of a gate circuit that queries the resulting voltage at the memory, less critical.

However, this circuit arrangement, like all similarly constructed arrangements, has the disadvantage that active switching elements must be used. The arrangement proposed here, on the other hand, has the advantage to be built in the actual decoder only with passive switching elements (diode, resistors). Furthermore, the circuit is characterized in that the addition in the memory is bipolar according to the sign of the Code pulses are carried out without direct current. Especially because of this last-mentioned advantage the result is a very simple structure compared to the known circuits.

The arrangement for decoding pulse code modulated Signals according to the invention is now characterized in that the code pulses of a code pulse group control a gate circuit from a control voltage decaying within a decoding period when a code pulse is applied, a pulse excerpt separates, and that these pulse excerpts with the polarity of the triggering code pulses in one of the gate circuits connected downstream Storage capacitor are summed up so that the decodded signal can be picked up there.

The invention is explained in more detail below with reference to the drawings. It shows:

909 757/338

1 shows an arrangement for decoding PCM signals according to the invention for several communication channels,

2 shows an arrangement for decoding PCM signals according to the invention for a communication channel,

3, 4 and 5 show three circuits for generating the circuits required in the arrangements according to FIGS Control voltages.

In the decoding arrangement shown in FIG. 1, the incoming code pulses are simultaneously fed to the circuit 2 at 1 and a control voltage 5 at 3. The circuit 2 is set up so that each positive and negative code pulse from the control voltage 5, depending on its time of occurrence, separates a pulse segment 6, which is then stored in the capacitor 4 with the polarity of the triggering code pulse. The control voltage 5 consists of a sequence of exponentially decaying oscillations with a respective length η · τ if τ is the time interval between two code pulses and η is the number of code pulses per pulse group.

The time constant of the exponential oscillations is dimensioned in such a way that its amplitude has decayed by half after the time segment τ. As a result, the individual code pulses are practically multiplied by factors that decrease in powers of 2. These individual pulses then add up in the capacitor 4, so that the voltage occurring there is proportional to the amplitude step encoded on the transmission side. The switch 7 then distributes the voltage values occurring on the capacitor 4 due to the code pulse groups arriving one after the other according to the multiplex scheme used via the low-pass filters 8, 9, 10 to the corresponding low-frequency communication channels. A simple modulator arrangement is expediently used as the circuit 2, as is known from PAM technology, e.g. B. a diode bridge modulator.

Fig. 2 shows a corresponding decoding arrangement for only one message channel. The storage capacitor 4 here consists of the input capacitor of the low-pass filter 11. The mode of operation of this circuit differs, apart from the fact that the distribution switch 7 is omitted here and, if the circuit arrangement is used in a multi-channel system, between the individual code pulse groups arriving at 1 and accordingly between the individual decaying exponential oscillations of the control voltage 5 greater time intervals exist, not from the circuit described in FIG. 1.

If the capacitor 4 is not completely discharged after each incoming code pulse group, it can crosstalk easily occur in the circuit of FIG.

To avoid this, the capacitor would have to be completely discharged during the transition. Since this encounters certain difficulties, two capacitors 4 can be used, which alternate in the circuit can be switched on so that one capacitor can discharge completely while the other is charged in the circuit, and vice versa. Correspondingly, two complete Use circuits according to Fig. 1, in one the even-numbered and in the other the odd-numbered Channels are decoded.

In Fig. 3, a network for generating the control voltage is shown. If this RC element 12 is fed with short current pulses, a voltage curve 13 results across it, which fulfills the conditions set for the control voltage 5 in FIGS. 1 and 2.

4 shows a further combined network 14. The one that can be removed with the same feed Voltage curve 15 shows an exponential curve caused by the additional i? CL element superimposed damped sinusoidal oscillation. Due to the resulting step-shaped course of the Small newspaper inaccuracies have a less disruptive effect on the exponential curve.

5 shows a further network 16, consisting of an oscillating circuit, the one that decays exponentially Oscillations with twice the frequency of the code steps supplies. By means of a rectifier, only the positive half-waves are allowed through, so that a voltage curve according to 17 results at the output. The damping of the oscillating circuit is dimensioned in such a way that that the momentum integrals of two successive positive half-waves behave as 2: 1. This arrangement has the advantage that the switch-on and switch-off time of the circuit 2 (Fig. 1 and 2) becomes less critical. The circuit now only needs to be between two successive positives Half-waves are switched on or off, with no high demands on the time accuracy the switch-on or switch-off time.

Claims (7)

PATENT CLAIMS: 1. Arrangement for the decoding of pulse-code-modulated signals according to a binary code are formed, characterized in that the code pulses of a code pulse group a gate circuit control that from a decaying S expensive voltage within a decoding period when concerns a code pulse separates a pulse segment, and that these pulse segments with the Polarity of the triggering code pulses in a storage capacitor connected downstream of the gate circuit are summed up so that the decoded signal can be picked up there. 2. Arrangement according to claim 1, characterized in that the control voltage consists of a sequence of exponentially decaying oscillations, the time constant of which is dimensioned so that their amplitude has decayed by half after the time τ, which corresponds to the distance between two code pulses, and whose length is equal to η · τ in each case. 3. Arrangement according to claim 2, characterized in that the exponentially decaying vibrations a sinusoidal voltage that is also decaying is also superimposed. 4. Arrangement according to claim 1, characterized in that the control voltage from sequences of positive half-waves of sine waves with the frequency and duration w τ per sequence, which are damped so that the momentum integrals of two successive half-waves behave like 2: 1. 5. Arrangement according to claim 2 or 3 for use in multi-channel systems, characterized in that that two storage capacitors are provided to avoid crosstalk, the are switched on alternately in the circuit. 6. Arrangement according to claim 2 or 3 for use in multi-channel systems, characterized in that that two identical circuits of the type mentioned are provided to avoid crosstalk of which one is the news signals of the even-numbered channels and the one others fed to the odd-numbered channels. 7. Arrangement according to claim 2 or 3 for use for only one channel, characterized in that that the storage capacitor is at the same time the first element of a low-pass filter to which the decoded and demodulated signal is extracted. Considered publications:
U.S. Patent No. 2,514,671. 1 sheet of drawings