CN203367266U - Encapsulation structure for buffering chip surface solder dosage - Google Patents
Encapsulation structure for buffering chip surface solder dosage Download PDFInfo
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Abstract
本实用新型一种用于缓冲芯片表面焊料用量的封装结构,其第一引线条一端的支撑区连接到整流芯片下表面,该整流芯片下表面通过焊锡膏与该第一引线条的支撑区电连接;位于第二引线条一端的焊接区与连接片的第一焊接面连接;连接片的第一焊接面和第二焊接面之间具有一中间区,此中间区与第一焊接面和第二焊接面之间分别设有第一折弯处和第二折弯处,所述连接片的第二焊接面相对的两侧端面均具有条状缺口,一第二通孔位于第二折弯处、第二焊接面、中间区上,此第二通孔横跨第二折弯处并延伸到第二焊接面、中间区边缘区域。本实用新型封装结构可以自适应吸收多余的焊料,既保证了焊接区域铺展有足够面积的焊料,又避免了因为焊料量多而溢出可焊接区造成产品失效,提高了产品电性、可靠性和良率。
The utility model relates to a packaging structure for buffering the amount of solder on the surface of a chip. The supporting area at one end of the first lead bar is connected to the lower surface of the rectifier chip, and the lower surface of the rectifying chip is electrically connected to the supporting area of the first lead bar through solder paste. connection; the welding zone at one end of the second lead bar is connected to the first welding surface of the connecting piece; there is an intermediate zone between the first welding surface and the second welding surface of the connecting piece, and this intermediate zone is connected to the first welding surface and the second welding surface A first bend and a second bend are respectively provided between the two welding surfaces, the end surfaces on both sides opposite to the second welding surface of the connecting piece have strip-shaped notches, and a second through hole is located at the second bend On the second welding surface and the middle zone, the second through hole crosses the second bend and extends to the edge area of the second welding surface and the middle zone. The package structure of the utility model can self-adaptively absorb excess solder, which not only ensures that the welding area has a sufficient area of solder, but also avoids product failure caused by overflowing the solderable area due to the excessive amount of solder, and improves the electrical properties, reliability and goodness of the product. Rate.
Description
技术领域 technical field
本实用新型涉及一种半导体封装器件,尤其涉及一种用于缓冲芯片表面焊料用量的封装结构。 The utility model relates to a semiconductor packaging device, in particular to a packaging structure for buffering the amount of solder on the surface of a chip.
背景技术 Background technique
整流器是利用二极管的单向导电特性对交流电进行整流,故被广泛应用于交流电转换成直流电的电路中。 The rectifier uses the unidirectional conductivity of the diode to rectify alternating current, so it is widely used in circuits that convert alternating current into direct current.
在设计开发连接片结构半导体产品时,为了提升大功率器件芯片表面的导电性能暨提升器件的关键电特性,需要把连接片与芯片焊接部分的面积设计的足够大。连接片与芯片上表面通过焊料焊接在一起。受限于连接片-芯片焊接区域和芯片上表面面积的匹配,焊料用量的控制成为关键工艺参数。焊料偏少会导致器件电特性不良,焊料过多会导致器件短路或早期可靠性失效。现有技术往往存在随着时间的延长,会出现各种电性能下降。尤其是 When designing and developing semiconductor products with connecting sheet structure, in order to improve the conductivity of the chip surface of high-power devices and improve the key electrical characteristics of the device, it is necessary to design the area of the connecting sheet and the chip welding part to be large enough. The connecting sheet and the upper surface of the chip are welded together by solder. Limited by the matching of the bonding pad-chip bonding area and the surface area of the chip, the control of the amount of solder becomes a key process parameter. Too little solder can lead to poor electrical characteristics of the device, and too much solder can cause short circuits or early reliability failures in the device. In the prior art, various electrical properties tend to decline with the extension of time. especially
因此,如何研发一种整流芯片封装结构,能解决上述问题,便成为本领域技术人员努力的方向。 Therefore, how to develop a rectifier chip packaging structure that can solve the above problems has become the direction of efforts of those skilled in the art.
发明内容 Contents of the invention
本实用新型目的是提供一种用于缓冲芯片表面焊料用量的封装结构,该用于缓冲芯片表面焊料用量的封装结构可以自适应吸收多余的焊料,既保证了焊接区域铺展有足够面积的焊料,又避免了因为焊料量多而溢出可焊接区造成产品失效,提高了产品电性、可靠性和良率。 The purpose of the utility model is to provide a packaging structure for buffering the amount of solder on the surface of the chip. The packaging structure for buffering the amount of solder on the surface of the chip can self-adaptively absorb excess solder, which not only ensures that the welding area has a sufficient area of solder, It also avoids the failure of the product caused by overflowing the solderable area due to the excessive amount of solder, and improves the electrical properties, reliability and yield of the product.
为达到上述目的,本实用新型采用的技术方案是:一种用于缓冲芯片表面焊料用量的封装结构,包括位于环氧封装体内的第一引线条、第二引线条、连接片和整流芯片,该第一引线条一端的支撑区连接到所述整流芯片下表面,该整流芯片下表面通过焊锡膏与该第一引线条的支撑区电连接,第一引线条另一端作为器件电流传输的引脚区; In order to achieve the above purpose, the technical solution adopted by the utility model is: a packaging structure for buffering the amount of solder on the surface of the chip, including the first lead bar, the second lead bar, the connecting piece and the rectifier chip located in the epoxy package, The support area at one end of the first lead bar is connected to the lower surface of the rectifier chip, the lower surface of the rectifier chip is electrically connected to the support area of the first lead bar through solder paste, and the other end of the first lead bar is used as a lead for device current transmission. foot area;
位于所述第二引线条一端的焊接区与连接片的第一焊接面连接,该第二引线条另一端作为器件电流传输的引脚区;所述连接片第二焊接面与整流芯片上表面通过焊锡膏电连接; The welding area located at one end of the second lead bar is connected to the first welding surface of the connecting sheet, and the other end of the second lead bar is used as a pin area for device current transmission; the second welding surface of the connecting sheet is connected to the upper surface of the rectifier chip Electrical connection via solder paste;
所述连接片的第一焊接面和第二焊接面之间具有一中间区,此中间区与第一焊接面和第二焊接面之间分别设有第一折弯处和第二折弯处,从而使得中间区高度高于第一焊接面和第二焊接面,所述连接片的第二焊接面相对的两侧端面均具有条状缺口;所述第二焊接面均匀分布有若干个第一通孔,一第二通孔位于第二折弯处、第二焊接面、中间区上,此第二通孔横跨第二折弯处并延伸到第二焊接面、中间区边缘区域。 There is an intermediate area between the first welding surface and the second welding surface of the connecting piece, and a first bending position and a second bending area are respectively provided between the intermediate area and the first welding surface and the second welding surface , so that the height of the middle zone is higher than the first welding surface and the second welding surface, and the opposite end surfaces of the second welding surface of the connecting sheet have strip-shaped notches; the second welding surface is evenly distributed with several first welding surfaces. A through hole and a second through hole are located on the second bending position, the second welding surface and the middle area, and the second through hole crosses the second bending position and extends to the edge area of the second welding surface and the middle area.
上述技术方案中进一步改进的方案如下: The scheme of further improvement in above-mentioned technical scheme is as follows:
1. 上述方案中,所述连接片的第一焊接面高度低于所述第二焊接面高度。 1. In the above scheme, the height of the first welding surface of the connecting piece is lower than the height of the second welding surface.
2. 上述方案中,所述第一折弯处、第二折弯处与中间区夹角为125°~145°。 2. In the above scheme, the included angle between the first bend, the second bend and the middle area is 125°~145°.
由于上述技术方案运用,本实用新型与现有技术相比具有下列优点和效果: Due to the application of the above-mentioned technical solutions, the utility model has the following advantages and effects compared with the prior art:
1. 本实用新型用于缓冲芯片表面焊料用量的封装结构,其连接片的第一焊接面和第二焊接面之间具有一中间区,此中间区与第一焊接面和第二焊接面之间分别设有第一折弯处和第二折弯处,从而使得中间区高度高于第一焊接面和第二焊接面,所述连接片的第二焊接面相对的两侧端面均具有条状缺口,在保证不降低接触面积和增加电阻的情况下,可以自适应吸收多余的焊料,从而防止焊料进入非焊接区,既保证了焊接区域铺展有足够面积的焊料,又避免了因为焊料量多而溢出可焊接区造成产品失效、短路,提高了产品电性和可靠性大大提高了良率。 1. This utility model is used to buffer the packaging structure of the chip surface solder consumption. There is an intermediate area between the first welding surface and the second welding surface of the connecting piece. The first bend and the second bend are respectively provided in between, so that the height of the middle zone is higher than the first welding surface and the second welding surface, and the opposite side end surfaces of the second welding surface of the connecting piece have strips Shaped gap, under the condition of not reducing the contact area and increasing the resistance, it can adaptively absorb the excess solder, thereby preventing the solder from entering the non-soldering area, which not only ensures that the soldering area has a sufficient area of solder, but also avoids due to the amount of solder Too many and overflowing solderable areas cause product failure and short circuit, which improves the electrical properties and reliability of the product and greatly improves the yield rate.
2. 本实用新型用于缓冲芯片表面焊料用量的封装结构,其连接片的第一焊接面和第二焊接面之间具有一中间区,此中间区与第一焊接面和第二焊接面之间分别设有第一折弯处和第二折弯处,从而使得中间区高度高于第一焊接面和第二焊接面,所述连接片的第二焊接面相对的两侧端面均具有条状缺口;所述第二焊接面均匀分布有若干个第一通孔;既可防止焊料进入非焊接区,避免了因为焊料量多而溢出可焊接区造成产品失效、短路,提高了产品电性和可靠性大大提高了良率,第二焊接面均匀分布有若干个第一通孔由于第一通孔覆盖溢出的焊料,防止焊料在焊接面边缘溢出,利用了连接片中第一通孔的侧面积,减小了接触电阻和响应时间,降低了功耗,也加强了连接片与整流芯片的连接强度。 2. The utility model is used to buffer the packaging structure of the chip surface solder consumption. There is an intermediate area between the first welding surface and the second welding surface of the connecting sheet, and the intermediate area is connected to the first welding surface and the second welding surface. The first bend and the second bend are respectively provided in between, so that the height of the middle zone is higher than the first welding surface and the second welding surface, and the opposite side end surfaces of the second welding surface of the connecting piece have strips There are a number of first through holes evenly distributed on the second welding surface; it can prevent the solder from entering the non-welding area, avoid product failure and short circuit caused by overflowing the weldable area due to a large amount of solder, and improve the electrical performance of the product. And the reliability greatly improves the yield rate. There are several first through holes evenly distributed on the second soldering surface. Since the first through hole covers the overflowing solder, it prevents the solder from overflowing at the edge of the soldering surface. The first through hole in the connecting piece is used. The side area reduces the contact resistance and response time, reduces power consumption, and also strengthens the connection strength between the connection piece and the rectifier chip.
3. 本实用新型用于缓冲芯片表面焊料用量的封装结构,其连接片的第二焊接面相对的两侧端面均具有条状缺口;所述第二焊接面均匀分布有若干个第一通孔,一第二通孔位于第二折弯处、第二焊接面、中间区上,此第二通孔横跨第二折弯处并延伸到第二焊接面、中间区边缘区域;进一步防止焊料进入非焊接区,避免了因为焊料量多而溢出可焊接区造成产品失效、短路,提高了产品电性和可靠性大大提高了良率,第二焊接面均匀分布有若干个第一通孔由于通孔覆盖溢出的焊料,防止焊料在焊接面边缘溢出,减小了接触电阻和响应时间,降低了功耗。 3. This utility model is used to buffer the packaging structure of the chip surface solder consumption, and the two end faces of the connecting piece opposite to the second welding surface have strip-shaped gaps; the second welding surface is evenly distributed with a number of first through holes , a second through hole is located on the second bend, the second welding surface, and the middle area, and the second through hole spans the second bend and extends to the edge area of the second welding surface and the middle area; further prevents solder Entering the non-soldering area, avoiding product failure and short circuit caused by overflowing the solderable area due to a large amount of solder, improving the electrical properties and reliability of the product and greatly improving the yield rate. There are several first through holes evenly distributed on the second welding surface due to The through hole covers the overflowing solder, prevents the solder from overflowing at the edge of the soldering surface, reduces contact resistance and response time, and reduces power consumption.
附图说明 Description of drawings
附图1为现有技术封装结构示意图一;
Accompanying
附图2为现有技术封装结构示意图二;
Accompanying
附图3为本实用新型用于缓冲芯片表面焊料用量的封装结构示意图;
Accompanying
附图4为附图3中A-A剖面结构示意图。
以上附图中:1、第一引线条;11、支撑区;2、第二引线条;21、焊接区;3、连接片;31、第一焊接面;32、第二焊接面;33、中间区;34、第一折弯处;35、第二折弯处;4、整流芯片;5、引脚区;6、条状缺口;7、第一通孔;8、焊料;9、第二通孔。 In the above drawings: 1, the first lead bar; 11, the supporting area; 2, the second lead bar; 21, the welding area; 3, the connecting piece; 31, the first welding surface; 32, the second welding surface; 33, Middle area; 34, first bend; 35, second bend; 4, rectifier chip; 5, lead area; 6, strip notch; 7, first through hole; 8, solder; Two through holes.
具体实施方式 Detailed ways
下面结合附图及实施例对本实用新型作进一步描述: Below in conjunction with accompanying drawing and embodiment the utility model is further described:
实施例:一种用于缓冲芯片表面焊料用量的封装结构,包括位于环氧封装体内的第一引线条1、第二引线条2、连接片3和整流芯片4,该第一引线条1一端的支撑区11连接到所述整流芯片4下表面,该整流芯片4下表面通过焊锡膏与该第一引线条1的支撑区11电连接,第一引线条1另一端作为器件电流传输的引脚区5;
Embodiment: A packaging structure for buffering the amount of solder on the chip surface, including a
位于所述第二引线条2一端的焊接区21与连接片3的第一焊接面31连接,该第二引线条2另一端作为器件电流传输的引脚区5;所述连接片3第二焊接面32与整流芯片4上表面通过焊锡膏电连接;
The
所述连接片3的第一焊接面31和第二焊接面32之间具有一中间区33,此中间区33与第一焊接面31和第二焊接面32之间分别设有第一折弯处34和第二折弯处35,从而使得中间区33高度高于第一焊接面31和第二焊接面32,所述连接片3的第二焊接面相对的两侧端面均具有条状缺口6;所述第二焊接面32均匀分布有若干个第一通孔7,一第二通孔9位于第二折弯处35、第二焊接面32、中间区33上,此第二通孔9横跨第二折弯处35并延伸到第二焊接面32、中间区33边缘区域。
There is an
上述连接片3的第一焊接面31高度低于所述第二焊接面32高度。
The height of the
上述第一折弯处34、第二折弯处35与中间区33夹角为125°~145°。
The above-mentioned
采用上述用于缓冲芯片表面焊料用量的封装结构时,其连接片的第一焊接面和第二焊接面之间具有一中间区,此中间区与第一焊接面和第二焊接面之间分别设有第一折弯处和第二折弯处,从而使得中间区高度高于第一焊接面和第二焊接面,所述连接片的第二焊接面相对的两侧端面均具有条状缺口,在保证不降低接触面积和增加电阻的情况下,可以自适应吸收多余的焊料,从而防止焊料8进入非焊接区,既保证了焊接区域铺展有足够面积的焊料8,又避免了因为焊料8量多而溢出可焊接区造成产品失效、短路,提高了产品电性和可靠性大大提高了良率;其次,其连接片的第一焊接面和第二焊接面之间具有一中间区,此中间区与第一焊接面和第二焊接面之间分别设有第一折弯处和第二折弯处,从而使得中间区高度高于第一焊接面和第二焊接面,所述连接片的第二焊接面相对的两侧端面均具有条状缺口;所述第二焊接面均匀分布有若干个第一通孔,防止焊料8在焊接面边缘溢出,利用了连接片中第一通孔的侧面积,减小了接触电阻和响应时间,降低了功耗,也加强了连接片与整流芯片的连接强度。
When the above packaging structure for buffering the amount of solder on the surface of the chip is adopted, there is an intermediate zone between the first soldering surface and the second soldering surface of the connecting sheet, and the intermediate zone is separated from the first soldering surface and the second soldering surface. A first bend and a second bend are provided, so that the height of the middle zone is higher than the first welding surface and the second welding surface, and the end surfaces on both sides opposite to the second welding surface of the connecting piece have strip-shaped notches , under the condition of not reducing the contact area and increasing the resistance, it can adaptively absorb excess solder, thereby preventing the
上述实施例只为说明本实用新型的技术构思及特点,其目的在于让熟悉此项技术的人士能够了解本实用新型的内容并据以实施,并不能以此限制本实用新型的保护范围。凡根据本实用新型精神实质所作的等效变化或修饰,都应涵盖在本实用新型的保护范围之内。 The above-mentioned embodiments are only to illustrate the technical concept and characteristics of the present utility model, and its purpose is to enable those familiar with this technology to understand the content of the present utility model and implement it accordingly, and not to limit the protection scope of the present utility model. All equivalent changes or modifications made according to the spirit of the utility model shall fall within the protection scope of the utility model.
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| CN2013204159588U CN203367266U (en) | 2013-07-12 | 2013-07-12 | Encapsulation structure for buffering chip surface solder dosage |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103383929A (en) * | 2013-07-12 | 2013-11-06 | 苏州固锝电子股份有限公司 | High-reliability rectifying device |
| CN110202289A (en) * | 2018-06-13 | 2019-09-06 | 华帝股份有限公司 | Welding material spreading part, welding part and manufacturing method of welding part |
-
2013
- 2013-07-12 CN CN2013204159588U patent/CN203367266U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103383929A (en) * | 2013-07-12 | 2013-11-06 | 苏州固锝电子股份有限公司 | High-reliability rectifying device |
| CN110202289A (en) * | 2018-06-13 | 2019-09-06 | 华帝股份有限公司 | Welding material spreading part, welding part and manufacturing method of welding part |
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