CN203339149U - QFN packaging structure - Google Patents

Abstract

The utility model discloses a QFN package structure, which is characterized in that it comprises: a copper bracket, a bare metal cooling plate is designed in the middle, and metal contacts for replacing pins are designed around; an upper layer chip and a lower layer chip are stacked on the On the above-mentioned metal cooling plate; a plurality of wires are electrically connected between the upper chip and the lower chip, between the lower chip and the metal contact; the insulating resin filled in the packaging space of the packaging structure. The QFN packaging structure described in the utility model uses metal contacts instead of traditional pins, which can reduce impedance and increase chip information processing frequency. At the same time, the central bottom of the copper bracket is designed with a bare metal heat sink, so that the chip can quickly conduct heat when it is working. , good cooling effect.

Description

QFN package structure

technical field

The utility model belongs to the technical field of semiconductor logic chip packaging, in particular to a logic chip QFN packaging structure with a small size chip, no pins and fast heat dissipation.

Background technique

Chips packaged in the prior art are generally larger, more than 8*8mm, using a copper support substrate, with pins, and no exposed heat dissipation plate at the bottom for rapid heat dissipation, and for small chips with a small size such as 3*3mm or less The general use of large-size package structure, and there is no special package structure to solve the problem of poor heat dissipation and large impedance.

Contents of the invention

The purpose of the utility model is to provide a logic chip QFN packaging structure suitable for small-sized chips, without pins and fast heat dissipation.

For realizing above-mentioned utility model purpose, the utility model has adopted following technical scheme:

A kind of QFN encapsulation structure is characterized in that, comprises:

A copper bracket with a bare metal cooling plate in the middle and metal contacts instead of pins around it;

At least one chip is arranged on the copper support, and the metal cooling plate is pasted under the chip;

A plurality of wires are electrically connected between the chip and the metal contacts; the wires can be gold wires.

The insulating resin filled in the packaging space of the packaging structure.

Further, the chip and the chip or the chip and the copper support are bonded with an adhesive tape.

Further, the size of the chip is ≤3mm*3mm.

The process flow for making the above-mentioned QFN package structure includes the following steps:

Chip grinding and dicing->chip stacking->gold wire bonding->resin synthesis->plating->cutting.

First, the chip is ground to the thickness required for the package, and cut into individual components, and then the chip and the chip, the chip and the copper bracket are connected by tape, the gold wire is welded, the chip is connected to the electronic circuit of the substrate, and the resin is synthesized into the entire cavity to protect the internal components. Metal contacts and pads are tinned for better connection to the PCB. In order to prevent copper oxidation and delamination between the resin and the copper bracket, special surface treatment technology is applied in part of the packaging process, using nitrogen, hydrogen, etc. and high energy to clean the surface impurities of the copper bracket and reduce surface oxidation to achieve enhanced surface roughness. Enhance the bonding force between surface and resin.

Utility model advantages:

The QFN packaging structure described in the utility model uses metal contacts instead of traditional pins, which can reduce impedance and increase chip information processing frequency. At the same time, the central bottom of the copper bracket is designed with a bare metal heat sink, so that the chip can quickly conduct heat when it is working. , good cooling effect.

Description of drawings

Fig. 1 is the sectional view of the utility model QFN packaging structure;

FIG. 2 is a top view of the QFN package structure of the present invention.

Among them, 1. Metal heat sink; 2. Chip; 3. Metal contact; 4. Gold wire; 5. Insulating resin; 6. Copper bracket.

Detailed ways

The technical solution of the utility model will be further described below in conjunction with the accompanying drawings and a preferred embodiment.

Example:

As shown in Figures 1 to 2: a QFN package structure, including:

A copper bracket 6, with a bare metal cooling plate 1 designed in the middle, and metal contacts 3 designed around it to replace pins;

A chip 2 is arranged on the copper bracket 6, and the metal cooling plate 1 is pasted under the chip 2;

A plurality of gold wires 4 are electrically connected between the chip 2 and the metal contact 3;

The insulating resin 5 filled in the packaging space of the packaging structure.

The chip 2 and the copper support 6 are bonded with adhesive tape.

The size of the chip 2 is 3mm*3mm. .

It should be pointed out that the above descriptions are only used to explain the preferred embodiments of the utility model, and are not intended to limit the utility model in any form. Any modifications or changes related to the utility model should still be included in the intended protection scope of the utility model.

Claims (1)

1. A QFN packaging structure, characterized in that, comprising: A copper bracket with a bare metal cooling plate in the middle and metal contacts instead of pins around it; At least one chip is arranged on the copper bracket, and the metal cooling plate is pasted under the chip; A plurality of wires are electrically connected between the chip and the metal contacts; The insulating resin filled in the package space of the package structure. 2. The QFN package structure according to claim 1, wherein the chip and the chip or the chip and the copper support are bonded with an adhesive tape. 3. The QFN package structure according to claim 2, wherein the size of the chip is ≤3mm*3mm.