CN1855450A - High heat dissipation semiconductor package and manufacturing method thereof - Google Patents

Abstract

A semiconductor package with high heat dissipation and a method for fabricating the same, the package comprising: a substrate; the semiconductor chip is arranged on the upper surface of the substrate and electrically connected with the substrate; a heat sink attached to the semiconductor chip; the packaging colloid wraps the semiconductor chip and the heat dissipation piece, the top surface and the side edge of the heat dissipation piece are exposed, the packaging colloid is flush with the side edge of the heat dissipation piece, and the size of the packaging colloid is smaller than that of the substrate; the invention makes the heat sink directly contact with the semiconductor chip, can improve the heat dissipation efficiency, and the semiconductor chip will not be pressed by the packaging mold or the heat sink, the bonding operation between the heat sink and the chip does not need to be highly controlled, the packaging cost can be reduced, the excellent rate can be improved, the limitation of the prior art on industrial utilization can be solved, and the industrial utilization value can be further improved.

Description

High heat dissipation semiconductor package and manufacturing method thereof

technical field

The present invention relates to a semiconductor package and its manufacturing method, in particular to a semiconductor package with heat sink to improve heat dissipation efficiency and its manufacturing method.

Background technique

With the demand for thinner, lighter and smaller electronic products, semiconductor packages such as Ball Grid Array (BGA, Ball GridArray), which can shrink integrated circuits (ICs) and have high density and multiple pins, have gradually become the mainstream in the packaging market. one. However, since this semiconductor package provides a higher density of electronic circuits (Electronic Circuits) and electronic components (Electronic Components), the heat generated during operation is also higher; moreover, this semiconductor package is made of materials with poor thermal conductivity. The encapsulation colloid covers the semiconductor chip, so the performance of the semiconductor chip is often affected by poor heat dissipation efficiency.

In order to improve the heat dissipation efficiency of semiconductor packages, many people have proposed the technology of adding heat sinks (Heat Sink, Heat Slug, Heat Block) to semiconductor packages. Related technologies such as US Patent No. 5,216,278, No. 5,736,785, No. 5,977,626 No. 6,522,428, 6,528,876, 6,462,405, 6,429,512, 6,433,420, 6,444,498, and 6,458,626.

Please refer to FIG. 7 , U.S. Patent No. 5,977,626 is a semiconductor package with a heat sink. The semiconductor package places a heat sink 71 on a substrate 73 and makes the central protrusion 711 of the heat sink 71 contact The semiconductor chip 70 , and the top surface 710 of the heat sink 71 exposes the encapsulant 74 , so that the heat generated by the semiconductor chip 70 can be dissipated through the heat sink 71 .

However, such semiconductor packages have several disadvantages in their manufacture. First of all, after the heat sink 71 is bonded to the chip 70, when it is put into the mold cavity of the packaging mold to carry out the molding operation (Molding) of the encapsulant 74, the top surface 710 of the heat sink 71 must be against the top of the mold cavity. wall, if the top surface 710 of the heat sink 71 fails to effectively abut against the top wall of the mold cavity, and a gap is formed between the two, the encapsulant 74 will overflow and remain on the top surface 710 of the heat sink 71 , once the top surface 710 of the heat sink 71 is formed with overflowing glue, in addition to affecting the heat dissipation efficiency of the heat sink 71, it will also affect the appearance of the finished product, so it is necessary to remove the glue (Deflash); however, to remove Glue processing is not only time-consuming and increases packaging costs, but also causes damage to finished products. In addition, if the force of the cooling fin 71 against the top wall of the mold cavity is too great, the brittle chip 70 will be cracked due to excessive pressure.

In addition, in order to make the distance between the top surface 710 of the heat sink 71 and the upper surface of the substrate 73 exactly equal to the depth of the mold cavity, the bonding of the heat sink 71 and the chip 70, the bonding of the chip 70 and the substrate 73, and the bonding of the heat sink 71 The thickness must be precisely controlled and manufactured, but this precision requirement will increase the packaging cost and increase the complexity of the manufacturing process, so it is more difficult to implement in practice. In addition, U.S. Patent Nos. 5,216,278 and 5,736,785 also propose similar semiconductor packages, but this semiconductor package also faces the above-mentioned problems in the manufacturing process, so its industrial utilization value will be reduced.

Therefore, US Patent Nos. 6,522,428, 6,528,876, 6,462,405, 6,429,512 and 6,433,420 provide a semiconductor package in which the heat sink does not contact the semiconductor chip. U.S. Patent No. 6,462,405 as shown in FIG. 8 has a semiconductor package with a heat sink. After the semiconductor chip 80 is electrically connected to the substrate 83 through a bonding wire 82, a defective chip is placed on the upper surface of the chip 80. cover body 85, and connect the heat sink 81 on the top surface of the substrate 83 to expose the encapsulant 84, and the heat sink 81 forms a concave portion 811 for the chip 80 to be accommodated under the heat sink 81 without contacting the heat sink 81 contacts to prevent the brittle semiconductor chip 80 from cracking due to excessive pressure during molding. However, because the heat sink 81 cannot directly contact the chip 80, the heat generated by it cannot be quickly dissipated, resulting in a decrease in the reliability of the semiconductor chip, which is not conducive to the needs of highly integrated circuits. Moreover, it still cannot solve the problem of heat dissipation during molding operations. The problem of glue overflow on the top surface of the fin 81, and the distance between the top surface of the heat sink 81 and the upper surface of the substrate 83 must be equal to the cavity depth of the mold and other precise control and production requirements.

In view of the above problems, US Pat. No. 6,444,498 and No. 6,458,626 propose a technique for directly contacting the heat sink with the semiconductor chip without causing chip cracks during the molding process.

Please refer to FIG. 9A to FIG. 9C, which is a semiconductor package disclosed in US Patent No. 6,444,498. The heat sink can be directly attached to the chip without pressure damage to the chip or overflow formed on the exposed surface of the heat sink. The problem. In this semiconductor package, on the surface of the heat sink 91 exposed to the atmosphere, a material layer 95 (such as an adhesive sheet made of polyimide resin) with poor adhesion between the heat sink 91 is formed, and then the heat sink is 91 is directly bonded on the chip 90 connected to the entire substrate 93, and then the molding process is performed to completely cover the heat sink 91 and the chip 90 with the encapsulant 94, and the encapsulant 94 is covered on the material layer of the heat sink 91 95 (as shown in FIG. 9A ), like this, the die cavity depth of the mold used in the molding process is greater than the sum of the thickness of the chip 90 and the heat sink 91, so after the mold clamping, the mold will not touch the heat sink 91, and the chip 90 will not It will be cracked under pressure; then, a singulation procedure (as shown in FIG. 9B ) is performed, and the encapsulant 94 above the heat sink 91 is removed. Wherein, because the adhesiveness between the material layer 95 formed on the heat sink 91 and the heat sink 91 is smaller than that between it and the encapsulant 94, after the encapsulant 94 is peeled off, the material layer 95 will adhere to the The encapsulant 94 is removed accordingly (as shown in FIG. 9C ), so no glue overflow will be formed on the heat sink 91 .

However, the manufacturing method of the above technology is only applicable to thin ball grid array (TFBGA, Thin FineBGA) semiconductor packages, in other words, the size of the encapsulant is flush with the size of the substrate. Therefore, this manufacturing method is not suitable for semiconductor packages such as PBGA, so its industrial utilization value is limited.

Therefore, how to overcome the problems of poor reliability, poor quality, and low industrial utilization value caused by the defects of semiconductor chip damage, difficult manufacturing process, and poor heat dissipation efficiency in the prior art, and how to effectively dissipate the heat generated by semiconductor packages has become a reality. become an urgent problem to be solved.

Contents of the invention

In order to overcome the shortcomings of the above-mentioned prior art, the main purpose of the present invention is to provide a semiconductor package with high heat dissipation and its manufacturing method, so that the heat sink and the chip can be directly bonded to improve the heat dissipation efficiency, and there will be no heat dissipation during the molding process. Cause chip cracks and glue overflow problems, thereby improving the good rate of finished products.

Another object of the present invention is to provide a highly heat-dissipating semiconductor package and its manufacturing method, which eliminates the need for highly controlled bonding of the heat sink and the chip, reduces packaging costs and improves yield.

Another object of the present invention is to provide a semiconductor package with high heat dissipation and a manufacturing method thereof that can increase industrial utility value.

To achieve the above and other objects, the present invention provides a semiconductor package with high heat dissipation and a manufacturing method thereof. The manufacturing method of the highly heat-dissipating semiconductor package includes: connecting and electrically connecting at least one semiconductor chip to a chip carrier, and the chip carrier is connected with a receiving plate having a hole corresponding to the position of the chip for the semiconductor chip Received in the opening and placed on the chip carrier; the heat sink with the interface layer formed on the surface is connected to the semiconductor chip with its opposite surface; molding operation is performed to form a heat sink covering the heat sink 1. The encapsulant of the semiconductor chip and part of the receiving board; cutting along the opening of the receiving board to remove the receiving board and the encapsulating gel covering it; and removing the encapsulating gel remaining on the interface layer of the heat sink.

The chip carrier may be a BGA substrate or an LGA substrate; the semiconductor chip and the substrate may be electrically connected by wire bonding or flip-chip. If the chip carrier is a BGA substrate, the above manufacturing method also includes: performing ball planting operation to form a plurality of conductive components, so that the semiconductor chip is electrically connected with external devices. In addition, the semiconductor package can be produced in batches, and the ball planting operation can be selected before or after the singulation operation.

The size of the opening of the receiving board is approximately the size of the molded and cut encapsulation compound. The size of the heat sink can be larger than the size of the opening of the receiving plate. When cutting along the opening of the receiving plate during the manufacturing process, the edge of the heat sink will be cut at the same time, so that the side of the heat sink exposes the encapsulant; The edge of the cutting part can optionally be provided with a concave part, so that the thickness of the edge of the heat sink can be thinned to facilitate the cutting operation; during the cutting operation, the size of the remaining encapsulant is equal to or smaller than the size of the opening of the receiving plate. An adhesive strengthening part is formed at the contact position between the lower surface of the heat sink and the encapsulant, and the adhesive strengthening part may be one of a group consisting of a concave-convex structure or a roughened (Roughened) or blackened (Black Oxide) structured structure kind.

The adhesion between the interface layer (such as a metal layer) and the heat sink can be greater than the adhesion between it and the encapsulation gel. The adhesion between colloids is poor, and the packaging colloid will not remain on the heat sink, so there is no problem of overflowing glue; relatively, the interface layer formed on the heat sink (such as an adhesive sheet made of polyimide resin) and heat dissipation The adhesiveness between the chips can be smaller than the adhesiveness between them and the encapsulation colloid. After the encapsulation colloid is peeled off, the interface layer will adhere to the encapsulation colloid and be removed accordingly, so there will be no glue overflow on the heat sink .

The highly heat-dissipating semiconductor package includes: a substrate; a semiconductor chip that is placed on the upper surface of the substrate and electrically connected to the substrate; a heat sink that is placed on the semiconductor chip; and an encapsulant that covers the semiconductor chip and the heat sink, and expose the top surface and side of the heat sink, and the encapsulant is flush with the side of the heat sink, and the size of the encapsulant is smaller than the size of the substrate.

The substrate can be a BGA substrate or an LGA substrate, and its size is larger than that of the heat sink and the encapsulant. The semiconductor chip can be placed on the upper surface of the substrate and electrically connected with the substrate by wire bonding or flip-chip. The edge of the heat sink can optionally be provided with a concave part, which is convenient for cutting operations. In addition, the lower surface of the heat sink and the contact position of the encapsulant can optionally be provided with an adhesive strengthening part, and the adhesive strengthening part can be a concave-convex structure or roughened (Roughened), Black Oxide (Black Oxide) processed structure constitutes one of the groups.

The semiconductor package also includes an interface layer formed on the heat sink, the interface layer is a metal layer; the semiconductor package can also include a plurality of conductive components, the conductive components are connected to the lower surface of the substrate, so that the semiconductor chip can It is electrically conductively connected to an external device. The conductive component may be, for example, a solder ball.

The invention makes the mold cavity of the package mold include the heat sink, and the mold cavity will not touch the heat sink. Therefore, compared with the prior art, the present invention can ensure that the heat sink is in direct contact with the semiconductor chip, thereby improving heat dissipation efficiency and preventing the semiconductor chip from cracking due to the pressure from the packaging mold or the heat sink. At the same time, the heat sink is also covered with an interface layer, which can be used for subsequent easy removal of the encapsulant covering it, and there will be no glue overflow problem. In the present invention, the bonding operation between the heat sink and the chip does not require height control, which can reduce the packaging cost and improve the yield. In addition, the encapsulant of the semiconductor package is flush with the edge of the heat sink, and the dimensions of the heat sink and the encapsulant are smaller than the substrate.

To sum up, because the manufacturing process of the present invention is simple to implement, it can solve the problems of poor reliability and poor quality caused by chip cracks in the prior art, and can increase the industrial utilization value. In addition, the present invention can be applied to semiconductor packages with different packaging structures, not limited to the TFBGA structure, so it can solve the limitations of the existing technology on industrial utilization, has considerable manufacturing flexibility, and further improves the industrial utilization value.

Description of drawings

FIG. 1A to FIG. 1G are schematic diagrams of the manufacturing method of Embodiment 1 of the high heat dissipation semiconductor package of the present invention;

Fig. 2 is the schematic diagram of embodiment 2 of the semiconductor package of high heat dissipation of the present invention;

Fig. 3 is the schematic diagram of embodiment 3 of the high heat dissipation semiconductor package of the present invention;

Fig. 4 is the schematic diagram of embodiment 4 of the semiconductor package of high heat dissipation of the present invention;

5 is a schematic diagram of Embodiment 5 of a semiconductor package with high heat dissipation of the present invention;

6 is a schematic diagram of embodiment 6 of a semiconductor package with high heat dissipation of the present invention;

7 is a schematic diagram of a semiconductor package with a heat sink disclosed in US Patent No. 5,977,626;

8 is a schematic diagram of a semiconductor package with a heat sink disclosed in US Patent No. 6,462,405; and

9A to 9C are schematic diagrams of a semiconductor package disclosed in US Pat. No. 6,444,498 where a heat sink can be directly bonded on a chip.

Detailed ways

The implementation of the present invention will be described below through specific specific examples.

Example 1

1A to 1G are drawn according to Embodiment 1 of the high heat dissipation semiconductor package and its manufacturing method of the present invention. In summary, the basic structure of the present invention is only schematically illustrated, so only the structures related to the present invention are shown, and the displayed structures are not drawn in proportion to the number, shape and size of the actual implementation. The number, shape and size of the actual implementation Proportion is an optional design, and its composition layout may be more complicated.

The manufacturing method of the highly heat-dissipating semiconductor package of the present invention is: as shown in FIG. 1A, a chip carrier (Chip Carrier) such as a substrate 11 is provided, and at least one semiconductor chip 15 is connected and electrically connected on the substrate 11. , and the substrate 11 is connected with the receiving plate 13 having the hole 131 corresponding to the chip position, and the semiconductor chip 15 is stored in the hole 131 and connected on the substrate 11 .

The substrate 11 can be, for example, a BGA substrate. The receiving plate 13 can be made of a metal sheet made of metal copper material, a polyimide (PI, Polyimide) film, a bismaleimide triazine (BT, Bismaleimide triazine) substrate or other suitable materials. The receiving plate 13 is formed with at least one cavity 131 for receiving at least one semiconductor chip 15 on the substrate 11 in the cavity 131 . In this embodiment, the size of the opening 131 is about the size of the molded package, for example, S1. The semiconductor chip 15 is electrically connected to the substrate 11 by, for example, bonding wires 17 .

It should be noted that the semiconductor chip 15 can be firstly arranged on the substrate 11 and electrically connected with the bonding wire 17, and then the receiving plate 13 can be combined on the substrate 11, or can be selected on the substrate 11 first. After combining the receiving board 13 , the semiconductor chip 15 is disposed in the opening 131 corresponding to the receiving board 13 on the substrate 11 and electrically connected with the bonding wire 17 .

As shown in FIG. 1B , the heat sink 3 with the interface layer 31 formed on its surface is connected to the semiconductor chip 15 with its opposite surface. The heat sink 3 can be made of, for example, copper, aluminum, copper alloy, aluminum alloy or other materials with good thermal conductivity.

In this embodiment, the heat sink 3 is, for example, a T-shaped cross-sectional structure, and the size of the heat sink 3 is, for example, S2, and S2 is larger than S1, that is, the size of the heat sink 3 is larger than the opening of the receiving plate 13. Hole 131. The heat sink 3 extends to the upper surface of the semiconductor chip 15 to form a contact portion 33 for being connected to the semiconductor chip 15 , and the bonding wire 17 is prevented from touching the heat sink 3 by the contact portion 33 .

The interface layer 31 can be pre-plated with gold, chromium or other metals with poor adhesion to the encapsulation colloidal compound, or a film made of polyimide resin can be pasted on the upper surface of the heat sink 3, or on the The upper surface of the heat sink 3 is coated with a coating such as epoxy resin, so that the adhesiveness between the film or the coating and the heat sink 3 is smaller than the adhesion between it and the packaging compound. In the subsequent process The encapsulation compound remaining on the interface layer 31 can be easily removed without glue overflow.

As shown in Figure 1C, the substrate 11 that is combined with the heat sink 3 and the chip 15 is placed in the mold cavity (not marked) of the packaging mold, and there is an appropriate gap between the top wall of the mold cavity and the heat sink 3 The distance is such that the mold cavity of the packaging mold is sufficient to include the heat sink 3, and the heat sink 3, the substrate 11, the semiconductor chip 15, the bonding wire 17 and the local storage plate are covered by the packaging compound injected into the mold cavity. 13 encapsulant 5. Since the mold cavity of the package mold does not touch the heat sink 3, the semiconductor chip 15 will not be subjected to pressure from the package mold or the heat sink 3 after the mold is closed, which avoids the possibility of chip cracks in the prior art question.

As shown in FIG. 1D and FIG. 1E , cut along the opening 131 of the receiving board 13 to remove the receiving board 13 and the encapsulant 5 covering it. The cutting positions 51 can be defined first, the distance between the cutting positions 51 is S3, and S3 can be equal to S1, so that the cutting tool 100 passes through the encapsulant 5 and the heat sink 3 along each of the cutting positions 51, and exposes The receiving board 13 , then, as shown in FIG. 1E , remove the receiving board 13 and the encapsulant 5 covering it.

As shown in FIG. 1F , the encapsulant 5 remaining on the interface layer 31 of the heat sink 3 is removed. When the adhesiveness between the interface layer 31 formed on the heat sink 3 (such as a film made of polyimide resin) and the heat sink 3 is less than the adhesiveness between it and the encapsulation body 5, the encapsulation body 5 After peeling off, the interface layer 31 will adhere to the encapsulant 5 and be removed (as shown in FIG. 1F ), so no glue overflow will be formed on the heat sink 3 . Relatively, the adhesiveness between the interface layer 31 (such as a gold-plated layer) and the heat sink 3 is greater than the adhesiveness between the interface layer 31 and the encapsulant 5. After the encapsulant 5 is peeled off, the interface layer 31 remains on the However, due to poor adhesion between the interface layer 31 and the encapsulant 5 , the encapsulant 5 will not remain on the heat sink 3 (as shown in FIG. 1F ′), so there is no glue overflow problem.

As shown in FIG. 1G, when the substrate 11 is a BGA substrate, the ball planting operation can be performed on the bottom of the substrate 11 to form a plurality of conductive components 6 such as solder balls, so that the semiconductor chip 15 can be electrically connected to external devices. , to obtain a semiconductor package with high heat dissipation. Of course, the semiconductor packages can be mass-produced in batches, and the ball planting operation can be performed first, and then individual semiconductor packages can be cut along predetermined cutting lines, which is not limited to the description in this embodiment.

Please refer to FIG. 1G , the present invention also discloses a semiconductor package with high heat dissipation. The semiconductor package includes a substrate 11 , a semiconductor chip 15 , a heat sink 3 , an encapsulant 5 and a plurality of conductive components 6 . The substrate 11 has an upper surface and a lower surface opposite to the upper surface, and the size of the substrate 11 is larger than the heat sink 3 and the encapsulant 5 , and can be, for example, a BGA substrate. The semiconductor chip 15 is bonded to the substrate 11 by eg an adhesive (not shown), and is electrically connected to the substrate 11 by eg a bonding wire 17 . The heat sink 3 has a T-shaped structure, for example, and has a contact portion 33 extending toward the upper surface of the semiconductor chip 15 and contacting the semiconductor chip 15 . The encapsulant 5 wraps the semiconductor chip 15 and exposes the top surface and side of the heat sink 3 , and the encapsulant 5 is flush with the side of the heat sink 3 . The conductive component 6 is connected to the lower surface of the substrate 11 so that the semiconductor chip 15 is electrically connected to external devices. In this embodiment, the conductive component 6 may be a solder ball, but it is not limited thereto.

Example 2

FIG. 2 is a schematic cross-sectional view of Embodiment 2 of the manufacturing method of the high heat dissipation semiconductor package of the present invention. Wherein, the same or similar components as in Embodiment 1 are represented by the same or similar component symbols, and to make the description of this case clearer and easier to understand, descriptions of the same parts in the manufacturing process and structure are omitted.

The biggest difference between embodiment 2 and embodiment 1 is that the distance S3 between the cutting positions in embodiment 1 is equal to the opening S1 of the storage plate, while in embodiment 2 the distance S3′ between the cutting positions is smaller than the opening S1 of the storage plate.

As shown in FIG. 2 , in the manufacturing process of Embodiment 2, the cutting position is defined to extend along the edge of the opening 131 of the receiving plate 13 toward the direction of the semiconductor chip 15 .

Example 3

FIG. 3 is a schematic cross-sectional view of Embodiment 3 of the high heat dissipation semiconductor package of the present invention. Wherein, components that are the same or similar to those of the above-mentioned embodiment are represented by the same or similar component symbols, and will not be described in detail. In order to make the characteristics of this case clearer, only the differences will be described.

The biggest difference between the third embodiment and the above-mentioned embodiments is that the cooling fins 3' in the third embodiment are respectively formed with recesses 351' on the edges of the lower surface.

The concave portion 351' can be selected to be located close to the cutting position in the above embodiment, so that the cutting tool only needs to cut the heat sink 3' with a thinner thickness, further improving the cutting efficiency.

Example 4

4 is a schematic cross-sectional view of Embodiment 4 of the high heat dissipation semiconductor package of the present invention. Wherein, components that are the same or similar to those in the above-mentioned embodiments are denoted by the same or similar component symbols, and will not be described in detail again.

The biggest difference between embodiment 4 and embodiment 3 is that the heat sink 3 ″ in embodiment 4 has an adhesive strengthening portion 353 ″ formed on its lower surface.

In this embodiment, the adhesive strengthening portion 353 ″ can be selected, for example, to have a concave-convex structure, so that the heat sink 3 ″ can be well bonded to the encapsulant 5 . However, it should be understood that the present invention is not limited thereto, and the lower surface of the heat sink 3" can also be roughened, blackened (Black Oxide) or other equivalent treatments to improve the cooling performance of the heat sink. 3″ and the adhesiveness between the encapsulant 5 .

Example 5

FIG. 5 is a schematic cross-sectional view of Embodiment 5 of the high heat dissipation semiconductor package of the present invention. Wherein, the same or similar components as those in the above-mentioned embodiments are represented by the same or similar component symbols, and will not be described in detail again.

The biggest difference between the fifth embodiment and the above-mentioned embodiments is that the above-mentioned uses a wire-bonded substrate 11 , while the fifth embodiment uses a flip-chip (Flip Chip) substrate 11 ′.

In this embodiment, a plurality of pads (Pads) 111' arranged in an array are formed on the upper surface of the substrate 11', for the semiconductor chip 15 to use the flip-chip method to weld the solder bumps 113' to actively The surface is electrically connected to the pad 111 ′ of the substrate 11 ′, and can be used for the heat sink 3 to be directly connected to the non-active surface of the chip 15 .

Example 6

FIG. 6 is a schematic cross-sectional view of Embodiment 6 of the high heat dissipation semiconductor package of the present invention. Wherein, components that are the same or similar to those in the above-mentioned embodiments are denoted by the same or similar component symbols, and will not be described in detail again.

The biggest difference between embodiment 6 and the above embodiment is that the above-mentioned chip carrier uses a BGA substrate 11, while embodiment 6 uses an LGA (LAND GRID ARRAY) substrate 11 "as the chip carrier of the semiconductor chip 15, and the semiconductor chip 15 non- The active surface is connected to the LGA substrate 11″, and the active surface of the chip 15 is electrically connected to the LGA substrate 11″ through the bonding wire 17, for subsequent via a plurality of metal contacts 110 arranged on the bottom surface of the LGA substrate 11″ "Electrically connected to external devices.

Since the present invention can make the heat sink directly contact with the semiconductor chip and will not cause chip cracks during the molding operation, it can avoid the poor reliability and poor quality of the prior art due to the defects of semiconductor chip damage and poor heat dissipation efficiency. And other issues. At the same time, the application of the present invention has no difficulty in the manufacturing process, and can be applied to different types of semiconductor packages, so it can solve the shortcomings of low or limited industrial utilization value caused by the prior art.

Therefore, the present invention can provide a semiconductor package with high heat dissipation and its manufacturing method, which solves various shortcomings of the prior art, improves product reliability while improving heat dissipation efficiency, and can further increase industrial utilization value.

Claims (34)

1. A high heat dissipation semiconductor package, characterized in that the semiconductor package comprises: Substrate; A semiconductor chip is placed on the upper surface of the substrate and electrically connected to the substrate; a heat sink attached to the semiconductor chip; and The encapsulant covers the semiconductor chip and the heat sink, and exposes the top surface and side of the heat sink, and the encapsulant is flush with the side of the heat sink, and the size of the encapsulant is smaller than the size of the substrate. 2. The semiconductor package as claimed in claim 1, wherein the substrate is a ball grid array or an LGA substrate. 3. The semiconductor package as claimed in claim 1, wherein the semiconductor chip is electrically connected to the substrate by a wire bonding method through a plurality of bonding wires. 4. The semiconductor package as claimed in claim 1, wherein the heat sink extends to the upper surface of the semiconductor chip to form a contact portion for being connected to the semiconductor chip, and at the same time, the contact portion prevents the wire bonding touch the heatsink. 5. The semiconductor package as claimed in claim 1, wherein the semiconductor chip is electrically connected to the substrate in a flip-chip manner. 6 . The semiconductor package as claimed in claim 1 , wherein a concave portion is formed on an edge of the lower surface of the heat sink. 7 . 7 . The semiconductor package as claimed in claim 1 , wherein an adhesive strengthening portion is provided on the lower surface of the heat sink in contact with the encapsulant. 7 . 8 . The semiconductor package as claimed in claim 7 , wherein the adhesion strengthening portion is one of a group consisting of a concave-convex structure or a roughened or blackened structure. 9 . The semiconductor package as claimed in claim 1 , further comprising a plurality of conductive components, the conductive components are connected to the lower surface of the substrate so that the semiconductor chip is electrically connected to external devices. 10 . 10. The semiconductor package as claimed in claim 9, wherein the conductive component is a solder ball. 11. The semiconductor package of claim 1, further comprising an interface layer formed on a top surface of the heat sink. 12. The semiconductor package as claimed in claim 11, wherein the interface layer is a metal with poor adhesion to the encapsulant. 13. The semiconductor package as claimed in claim 12, wherein the material of the interface layer is gold or chromium metal. 14. A method for manufacturing a semiconductor package with high heat dissipation, characterized in that the method comprises: At least one semiconductor chip is connected and electrically connected to the chip carrier, and the chip carrier is connected with a receiving plate with a hole corresponding to the chip position, for the semiconductor chip to be accommodated in the hole and placed on the chip carrier superior; connecting the heat sink with the interface layer formed on the surface to the semiconductor chip with its opposite surface; Carrying out molding operation to form an encapsulant covering the heat sink, semiconductor chip and part of the storage board; cutting along the opening of the receiving board to remove the receiving board and the encapsulant covering it; and The encapsulant remaining on the interface layer of the heat sink is removed. 15 . The manufacturing method according to claim 14 , further comprising forming a plurality of conductive elements on the lower surface of the chip carrier so that the semiconductor chip is electrically connected to external devices. 16 . The manufacturing method according to claim 14 , wherein the semiconductor packages are manufactured in a batch manner, and are cut into pieces to form a plurality of packaging units after the packaging is completed. 17 . 17 . The manufacturing method according to claim 16 , wherein the manufacturing method is to form a plurality of conductive components on the lower surface of the chip carrier before the singulation operation. 18 . 18 . The manufacturing method according to claim 16 , wherein the manufacturing method is to form a plurality of conductive components on the lower surface of the chip carrier after the singulation operation is performed. 19 . 19. The manufacturing method according to claim 14, wherein the semiconductor chip is electrically connected to the substrate through a plurality of bonding wires in a wire bonding manner. 20. The method according to claim 14, wherein the heat sink extends to the upper surface of the semiconductor chip to form a contact portion for being connected to the semiconductor chip, and at the same time, the contact portion prevents the welding wire from touch the heatsink. 21. The method of claim 14, wherein the semiconductor chip is electrically connected to the substrate in a flip-chip manner. 22. The method of claim 14, wherein the chip carrier is a ball grid array or an LGA substrate. 23. The method according to claim 14, wherein the size of the opening of the receiving plate is approximately the size of the molded encapsulant. 24. The method of claim 14, wherein the size of the heat sink is larger than the size of the opening of the receiving plate. 25. The manufacturing method according to claim 14, characterized in that an adhesive strengthening part is formed on the part where the lower surface of the heat sink is in contact with the encapsulant. 26 . The method according to claim 25 , wherein the adhesion strengthening portion is one of a group consisting of a concave-convex structure or a roughened or blackened structure. 27. The manufacturing method as claimed in claim 14, characterized in that, the edge of the lower surface of the cooling fin is provided with a concave portion for cutting operation. 28. The method of claim 14, wherein the size of the cut encapsulant is smaller than the size of the opening of the receiving plate. 29. The method according to claim 14, wherein the size of the encapsulant after cutting is equal to the size of the opening of the receiving plate. 30. The method according to claim 14, wherein the adhesiveness between the interface layer and the heat sink is greater than the adhesiveness between the interface layer and the encapsulant, and after the encapsulant on the interface layer is peeled off, The interface layer remains on the heat sink. 31. The method of claim 30, wherein the material of the interface layer is gold or chromium metal. 32. The method according to claim 14, wherein the adhesiveness between the interface layer and the heat sink is smaller than the adhesiveness between the interface layer and the encapsulant, and after the encapsulant on the interface layer is peeled off, The interface layer will adhere to the encapsulant and be removed accordingly. 33. The method of claim 32, wherein the interface layer is a film made of polyimide resin. 34. The method of claim 32, wherein the interface layer is a coating of epoxy resin.

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