CN1221027C - Semiconductor package with heat dissipation structure - Google Patents

Abstract

A semiconductor package with a heat dissipation structure comprises a chip bearing element, wherein a plurality of welding pads are arranged on the surface of the chip bearing element for the chip to be connected, so that a heat dissipation element is connected by a plurality of soft metal supporting blocks, and the heat dissipation element is supported above the chip by the supporting blocks; the heat sink has several positioning parts corresponding to the bonding parts of the supporting blocks, so that the heat sink can be properly positioned without deviation after being attached to the chip carrier; then the heat dissipation structure formed by the heat dissipation member and the supporting block and the semiconductor chip are reflowed to the chip bearing member together, and the top surface of the heat dissipation member is exposed out of the packaging colloid to improve the heat dissipation efficiency.

Description

Semiconductor package with heat dissipation structure

technical field

The invention relates to a semiconductor package, in particular to a flip-chip ball grid array (FCBGA) semiconductor package with an embedded heat sink to improve heat dissipation efficiency.

Background technique

Ball grid array (BGA) semiconductor package (Ball Grid Array Semiconductor Package) has a higher number of input/output connections (I/O Connection) to cope with semiconductor chips of high-density electronic components (Electronic Components) and electronic circuits (Electronic Circuits) It is necessary to meet the needs of electronic products for electrical functions and processing speed, and has become the mainstream of today's packaging. However, as the density of electronic circuits and electronic components on semiconductor chips increases, more heat will be generated during chip operation; if the heat energy generated by semiconductor chips is not effectively dissipated, the performance and service life of semiconductor chips will be affected. In addition, traditionally, the high-performance chip of the BGA semiconductor package is covered by encapsulant, but the encapsulant that constitutes the encapsulant is a poor heat transfer body with a thermal conductivity of only about 0.8w/m°K. Therefore, it is difficult to effectively dissipate heat on the active surface of the semiconductor chip on which the electronic circuit and electronic components are arranged; how to effectively remove the heat generated by the semiconductor chip has become a major issue to be solved in the industry.

U.S. Patent No. 5,726,079 discloses a flip-chip ball grid array (Flip ChipBall Grid Array, FCBGA) package structure (as shown in Figure 1), which arranges a heat sink 11 above the semiconductor chip 12, by The surface of the heat sink 11 exposed to the package 1 quickly dissipates the heat generated by the chip 12 into the atmosphere. However, the lack of this technology is that if the heat sink 11 is set too high, the mold clamping pressure will be pressed to the heat sink 11 when the molding operation is carried out, and then the chip 12 under the heat sink 11 will be pressed to cause damage to the chip 12; If the part 11 is placed too close to the chip 12, the exposed upper surface 110 of the heat sink 11 will be easily overflowed during the colloidal encapsulation process, which will reduce its heat dissipation effect and lead to poor appearance of the product. Therefore, this technique requires extremely high precision in order to ensure that the heat sink 11 is correctly placed at a predetermined height, which will increase the difficulty of the manufacturing process and is not cost-effective.

In addition, US Patent No. 5,977,626 also discloses a semiconductor package structure 1 with a special heat sink 11 . As shown in Figure 2, this semiconductor package structure 1 includes a heat sink 11 bonded to a substrate 14 on which a semiconductor chip 12 is attached; wherein the heat sink 11 has a flat portion 111 and is used for the flat portion 111 is supported on the support part 112 above the chip, so that the flat part 111 and the support part 112 form a storage space for the chip 12 and the gold wire 13 to be inserted. At the same time, the support part 112 is formed with a plurality of bumps 113, The heat sink 11 is stably connected to the substrate 14 through the bumps 113 .

Although this kind of package structure 1 can improve the heat dissipation efficiency of the chip through the design of the heat sink 11 with a special shape, the package still has the problem that it is difficult to properly place the heat sink 11 in the aforementioned patent (US Patent No. 5,726,079). In addition, the stamping process (Stamping) must be used to form the downwardly bent support portion 112 when making this special form of heat sink 11. In addition to increasing the packaging cost, the flatness of the flat portion 111 of the heat sink 11 after stamping (Planarity ) are often affected and cause the packaging resin to overflow on the upper surface 110 of the flat portion 111 (that is, the exposed surface 110 of the heat sink 11); especially nowadays, semiconductor packages are being developed towards a thinner trend, and the thickness of the heat sink 11 used is often as thin as 0.2 mm or even thinner, the reduced structural strength of the heat sink 11 due to the thinning will make it more difficult to maintain the flatness of the flat portion 111 , and the glue overflow phenomenon cannot be avoided.

Contents of the invention

The purpose of the present invention is to provide a semiconductor package with a built-in heat dissipation structure. The heat dissipation structure is provided with a plurality of soft metal support blocks so as to relieve the impact of the mold on the heat dissipation parts and even the chip during the mold clamping operation. In order to avoid damage to the semiconductor chip and allow the heat sink to be accurately positioned and placed on the chip smoothly, in addition to maintaining the excellent planarity of the heat sink, the exposed surface of the heat dissipation structure is not The excess glue thus improves the overall heat dissipation efficiency of the package.

Another object of the present invention is to provide a built-in heat dissipation structure by adjusting the size of the opening of the implant pad on the substrate so as to control the distance between the heat dissipation structure and the substrate, so as to reduce the packaging cost and the complexity of the manufacturing process. semiconductor package.

In view of the foregoing disclosure and other purposes, the semiconductor package with an embedded heat dissipation structure of the present invention includes: a substrate having a front surface and an opposite back surface, and a set of welding pads and a set of welding pads are respectively connected on the front surface of the substrate. Ball planting pads, and a plurality of conductive pads are arranged on the back of the substrate; a semiconductor chip has an active surface on which electronic circuits and electronic components are laid, and a plurality of soldering bumps are implanted on it for the chip and The conductive connection of the substrate; a heat dissipation structure, which is formed by a heat dissipation element and a plurality of soft metal support blocks, wherein the lower surface of the heat dissipation element is provided with a plurality of positioning parts for these support blocks to be glued; a plurality of solder balls, Implanted on the conductive pads to provide electrical coupling between the chip and external devices; and an encapsulant for covering the semiconductor chip, heat dissipation structure and part of the substrate, and exposing the upper surface of the heat dissipation element.

The positioning portion on the heat sink can be formed on the lower surface or a through hole that penetrates from the upper surface of the heat sink to the lower surface. Alloy and similar alloys and other soft metal materials) are glued to form a heat dissipation structure and are reflowed to the substrate at the same time as the solder bumps of the chip for molding operations. The height of the heat sink from the front of the substrate is slightly greater than that The distance between the top surface of the mold cavity and the substrate of the encapsulant encapsulation mold enables the mold clamping pressure provided by the mold to be released by the collapse of these soft metal support blocks during mold clamping, and is evenly distributed among the The heat dissipation element is used to reduce the pressure on the semiconductor chip to avoid damage to the chip, and also enables the heat dissipation element to be flatly attached to the top of the chip so as to maintain a good planarity of the heat dissipation element.

On the other hand, in addition to providing a space for the positioning portion to provide a pressure buffer space when the soft metal support block collapses, the heat sink is also made accurate by reflowing these support blocks to the welding pads of the substrate. If it is correctly positioned on the base plate without the risk of misalignment, the top surface of the heat sink and the top surface of the mold cavity of the upper mold of the mold can be tightly bonded during the molding process, thereby preventing the occurrence of glue overflow.

Description of drawings

Cooperate with the accompanying drawings below to further describe the characteristics and effects of the present invention in detail with preferred specific examples:

Figure 1 is a cross-sectional view of a semiconductor package of US Patent No. 5,726,079;

Figure 2 is a cross-sectional view of a semiconductor package of US Patent No. 5,977,626;

Fig. 3 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention;

Figures 4A to 4D are detailed process drawings of the first embodiment of the semiconductor package of the present invention;

Fig. 5 is a comparative sectional view before and after the molding process of the semiconductor package of the present invention;

FIG. 6 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention; and,

FIG. 7 is a cross-sectional view of a semiconductor package according to a third embodiment of the present invention.

Description of symbols

1, 2, 3 semiconductor package 20, 30 solder balls

11, 21, 31 Embedded heat sink 110, 210 Upper surface of heat sink

211, 311 Lower surface of heat sink 212 Dimple

312 Through hole 213, 313 Adhesive layer

111 Flat part 112 Support part

113 Bumps 12, 22, 32 Semiconductor chips

220 Active surface 221 Non-active surface

13 Gold wire 23, 33 Solder bump

14, 24, 34 Substrate 240 Substrate front

241 Substrate backside 242, 342 Solder pads

243 Ball Mounting Pad 243a Ball Mounting Pad Opening

244 Conductive Pad 245 Chip Landing Area

15, 25, 35 solder balls 16, 26, 36 encapsulant

17, 37 Underfill rubber 28 Molding mold

280 Top surface of mold cavity 29 Heat dissipation structure

Detailed ways

Various embodiments of the flip-chip ball grid array (FCBGA) semiconductor package of the present invention will be described in detail below with reference to the accompanying drawings.

First embodiment:

Figure 3 is a FCBGA semiconductor package 2 with an embedded heat sink according to the first embodiment of the present invention. The package structure is a substrate 24 with a plurality of solder pads 242, 243, 244 connected to one surface, each with a function. A semiconductor chip 22 on the surface 220, an embedded heat sink 21 (Embedded Heat Sink, EDHS) with a plurality of first solder balls 20 glued, a plurality of soldering bumps 23 implanted on the active surface 220 of the chip 22 , a plurality of second solder balls 25 planted on the substrate 24 for electrical connection between the semiconductor chip 12 and an external device (not shown), and one for covering the chip 22 and the heat sink 21, and making the heat dissipation The package compound 26 exposed on the upper surface 210 of the chip 21 is formed.

Figures 4A to 4D show the detailed manufacturing process of the FCBGA semiconductor package 2 with an embedded heat sink according to the first embodiment of the present invention. The manufacturing process of each part of the package will be described below.

First place a substrate 24, as shown in Fig. 4A, this substrate 24 has a front 240 and a relative back 241; The ball planting pads 243 (Ball Pads), and the back 241 of the substrate 24 are additionally provided with a plurality of conductive pads 244. A chip landing area 245 is preset on the front surface 240 of the substrate 24 to provide these welding pads 242 to be formed so as to be connected with solder bumps (not shown) of a semiconductor chip (not shown). These welding pads 242 are respectively connected by a plurality of A conductive trace (not shown) passes through a conductive via (not shown) and is electrically connected to a plurality of conductive pads 244 on the back surface 241 of the substrate 24 ; A plurality of ball planting pads 243 are formed so as to be soldered to the first solder balls (not shown) on the heat sink (not shown). In addition to the overall heat dissipation efficiency of the package 2, its electrical properties can be improved. The formation of the ball-planting pad 243 is the same as that of the conductive pad 244 on the existing BGA substrate for solder balls (not shown) to be planted thereon, so it will not be repeated here.

The semiconductor chip 22 has an active surface 220 and an opposite non-active surface 221, please refer to FIG. 4B. A plurality of electronic circuits and electronic components (not shown), and a plurality of input/output pads (not shown) are arranged on the active surface 220 so that a plurality of solder bumps 23 (SolderBump) are connected to the substrate 24 (As shown in FIG. 4A ) for electrical coupling, these solder bumps 23 are implanted through the bottom metallization process (Under Bump Metallization) and other methods. These flip-chip formation methods are known and will not be described separately. .

Moreover, prepare an embedded heat sink 21 made of metal materials such as copper and aluminum. As shown in FIG. 4C, the heat sink 21 has an upper surface 210 and an opposite lower surface 211. (Half Etching) or stamping (Stamping) technology (both are existing and therefore will not be described in detail) to set up a plurality of recesses 212 at appropriate positions on the lower surface 211 of the heat sink 21 for glue such as epoxy resin (Epoxy) Layer 213 is coated thereon; Then, a plurality of first solder balls 20 are placed one by one into these cavities 212 covered with adhesive layer 213 so that the first solder balls 20 are firmly connected to the heat sink 21 In order to form a heat dissipation structure 29 , the vertical height H of the first solder ball 20 must be greater than or equal to the sum of the thickness of the semiconductor chip 22 and the height of the solder bump 23 . The first solder ball 20 is not only made of tin, but other soft metals such as lead, tin/lead alloys and similar alloys are also applicable.

The semiconductor chip 22 and the embedded heat sink 21 are reflowed (Solder Reflow) to the corresponding pads 242, 243 of the substrate 24 by means of soldering bumps 23 and these first solder balls 20 respectively, as shown in FIG. 4D As shown, when performing ball planting by reflow operation, the first solder ball 20 can be accurately implanted on the ball planting pad 243 due to its self-alignment (Self-Alignment) to avoid the risk of misalignment; and, by The size of the opening 243a of the ball planting pad 243 on the surface of the substrate 24 can facilitate the adjustment of the height of the embedded heat sink 21 in the package 2 (the opening 243a of the ball planting pad 243 is larger, the first solder ball 20 The pressure sinks deeper, so that the height of the heat sink 21 in the package 2 is smaller and closer to the chip 22; and vice versa). After the semiconductor chip 22 , the solder bump 23 and the first solder ball 20 on the heat sink 21 are simultaneously reflowed to the substrate, the molding process can be performed.

The encapsulant 26 is formed of existing materials such as epoxy resin to cover the semiconductor chip 22 , the soldering bump 23 and the heat dissipation structure 29 . As shown in FIG. 5 , in order to effectively improve the heat dissipation efficiency of the semiconductor package 2 , the upper surface 210 of the heat sink 21 exposes the encapsulant 26 to directly contact with the atmosphere. Since the first solder ball 20 has a soft property, and the adhesive layer 213 between the first solder ball 20 and the heat sink 21 is also a buffer medium for absorbing pressure, the distance between the heat dissipation structure 29 and the substrate 24 The height H1 of the front side 240 is slightly greater than the distance between the cavity top surface 280 of the packaging mold 28 used to form the encapsulant 26 and the front surface 240 of the substrate 24, so when the mold clamping operation is performed, the cavity top surface 280 of the packaging mold 28 is A downward pressing force is provided so that the first solder ball 20 in contact with the heat sink 21 is deformed and sinks under pressure, and the upper surface 210 of the heat sink 21 is in close contact with the top surface 280 of the mold cavity so that no gap is formed between the two. Therefore, the occurrence of glue overflow can be avoided and the appearance and heat dissipation of the packaged product can be ensured; in addition, because the first solder ball 20 and the adhesive layer 213 stuck thereon have the characteristics of absorbing deformation, they can be effectively released. The compressive force produced by the packaging mold 28 on the heat sink 21 and even the chip 22 can be offset, so that the semiconductor chip 22 can be prevented from cracking during the molding process.

Second embodiment:

Figure 6 is a cross-sectional view of the semiconductor package of the second embodiment of the present invention, the semiconductor package 3 of the second embodiment is substantially the same as that disclosed in the first embodiment, the difference lies in the heat sink 31 A plurality of through holes 312 are opened to replace the recesses as positioning holes for connecting the solder balls 30 . A plurality of through holes 312 are pre-drilled at appropriate positions on the heat sink 31 by existing drilling technology, and an adhesive 313 is applied to the openings of the through holes 312 on the lower surface 311 of the heat sink 31 to bond the solder balls 30 and After the subsequent packaging operation, when the mold clamping operation is performed, the first solder ball 30 is forced to be deformed due to the pressing force exerted by the molding die (not shown) on the heat sink 31. At this time, these through holes 312 can form a buffer space to facilitate compression. The force is relieved so that less stress is transmitted to the chip, which in turn helps to maintain the structural integrity of the semiconductor chip 32 .

Third embodiment:

Fig. 7 is a cross-sectional view of a semiconductor package according to a third embodiment of the present invention. The semiconductor package according to this third embodiment is substantially the same as the previous two embodiments. The soldering quality of the soldering pad 342 on the substrate 34, then after the reflow operation is completed, the colloidal underfill (Underfill) (as shown in FIG. The fragile solder connection between the pads 342 will not be damaged by the pressing force exerted by the molding die (not shown), thus ensuring the quality reliability of the flip-chip soldering.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of the actual technical content of the present invention. The substantive technical content of the present invention is broadly defined within the scope of the claims of the present invention. If any technical entity or method completed by others is exactly the same as that defined in the scope of the claims of the present invention, or is an equivalent change, are deemed to be covered by this patent scope.

Claims (18)

1. A semiconductor package with heat dissipation structure, characterized in that: the semiconductor package comprises: A substrate, which has a front surface and an opposite back surface, a set of first welding pads and second welding pads are respectively arranged on the front surface of the substrate, and a plurality of third welding pads are connected to the back surface of the substrate; A semiconductor chip having an active surface for placing a plurality of solder bumps on it to electrically connect the chip with the first pad of the substrate; A heat dissipation structure, which has a heat dissipation element and a plurality of soft metal support blocks, wherein the heat dissipation element has an upper surface and an opposite lower surface, and a plurality of positioning parts are opened on the lower surface for these support blocks Adhesively placed and thereby connected to the second pad of the substrate; A plurality of conductive components are used to be connected to the third pad of the substrate for electrical coupling between the chip and external devices; and An encapsulation compound is used for covering the semiconductor chip and the heat dissipation structure and exposing the upper surface of the heat dissipation element. 2. The semiconductor package with heat dissipation structure as claimed in claim 1, wherein the semiconductor package is a flip chip ball grid array (FCBGA) semiconductor package. 3. The semiconductor package with heat dissipation structure as claimed in claim 1, wherein the first pad is a solder pad. 4. The semiconductor package with a heat dissipation structure as claimed in claim 1, wherein the second pad is a ball-mounted pad. 5 . The semiconductor package with heat dissipation structure as claimed in claim 1 , wherein the opening size of the second pad opening is adjusted according to the height of the heat dissipation structure from the front surface of the substrate. 6. The semiconductor package with heat dissipation structure as claimed in claim 1, wherein the third pad is a conductive pad. 7. The semiconductor package with heat dissipation structure as claimed in claim 1, wherein the active surface is a chip surface on which a plurality of electronic circuits and electronic components are laid. 8. The semiconductor package with heat dissipation structure as claimed in claim 1, wherein the solder bumps between the chip and the substrate are filled with a colloidal underfill to cover the gap between the chip and the substrate. Solder bumps. 9 . The semiconductor package with heat dissipation structure as claimed in claim 1 , wherein the heat dissipation element is an embedded heat sink made of metal. 10 . 10. The semiconductor package with heat dissipation structure as claimed in claim 1, wherein the material of the supporting block is selected from one of the group consisting of tin, lead, and tin/lead alloy. 11. The semiconductor package with heat dissipation structure as claimed in claim 1, wherein the supporting block is selected from one of the group consisting of solder column and solder ball. 12 . The semiconductor package with heat dissipation structure as claimed in claim 1 , wherein the vertical height of the supporting block is greater than or equal to the sum of the thickness of the semiconductor chip and the height of the solder bump. 13 . 13. The semiconductor package with heat dissipation structure as claimed in claim 1, wherein the support block is bonded to the positioning portion of the heat dissipation element by an adhesive layer. 14. The semiconductor package with heat dissipation structure as claimed in claim 13, wherein the adhesive layer is made of an elastic material of epoxy resin. 15. The semiconductor package with heat dissipation structure as claimed in claim 1, wherein the positioning portion is a cavity formed on the lower surface of the heat dissipation element. 16. The semiconductor package with a heat dissipation structure as claimed in claim 1, wherein the positioning portion is a plurality of through holes opened on the heat dissipation element. 17 . The semiconductor package with heat dissipation structure according to claim 1 , wherein the soldering bump and the supporting blocks are implanted on the plurality of groups of soldering pads provided on the substrate by means of reflow at the same time. 18 . 18. The semiconductor package with heat dissipation structure as claimed in claim 1, wherein the conductive component is a solder ball.

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