CN1929120A - Stacked chip package structure, chip package body and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a stacked chip packaging structure, a chip package and a manufacturing method thereof. The chip package comprises a packaging substrate, a chip and a packaging colloid. The packaging substrate comprises a core layer and a patterned circuit layer arranged on the core layer. The core layer has a first through hole and a plurality of second through holes, wherein the first through hole and the second through holes respectively expose a portion of the patterned circuit layer. The chip is arranged in the first through hole and electrically connected to the patterned circuit layer. The packaging colloid is arranged in the first through hole to fix the chip in the packaging substrate. Based on the above, the thickness of the chip package of the present invention can be thinned. In addition, the present invention also proposes a stacked chip packaging structure and a manufacturing method of the chip package.

Description

Stacked chip package structure, chip package body and manufacturing method thereof

technical field

The present invention relates to a package structure, and more particularly to a stacked chip package structure with high package density.

Background technique

In today's information society, users are pursuing high-speed, high-quality, and multi-functional electronic products. In terms of product appearance, the design of electronic products is also moving towards the trend of light, thin, short and small. In order to achieve the above purpose, many companies incorporate the concept of systemization when designing circuits, so that a single chip can have multiple functions, so as to save the number of chips configured in electronic products. In addition, as far as electronic packaging technology is concerned, in order to meet the design trend of light, thin, short, and small, the packaging design concept of multi-chip module (MCM) and chip scale package (chip scale package) have also been developed. , CSP) package design concept and the concept of stacked multi-chip package design. Several existing conventional stacked chip packaging structures are described below.

Please refer to FIG. 1 , which is a schematic cross-sectional view of a conventional stacked chip packaging structure. The conventional stacked chip package structure 100 includes a package substrate 110 , chips 120 a , 120 b , a spacer 130 , a plurality of wires 140 and an encapsulant 150 . Wherein, the chips 120a and 120b are disposed on the packaging substrate 110, and the spacer 130 is disposed between the chips 120a and 120b. Some wires 140 are respectively electrically connected between the chip 120 a and the package substrate 110 , while other parts of the wires 140 are respectively electrically connected between the chip 120 b and the package substrate 110 . In addition, the encapsulant 150 is disposed on the encapsulation substrate 110 and covers the wires 140 and the chips 120a and 120b.

Since the chips 120a and 120b must be separated by a certain distance to facilitate the wire bonding process, the overall thickness of the conventional stacked chip package structure 100 cannot be further reduced due to the thickness of the spacer 130 . In addition, the conventional stacked chip packaging structure 100 also has heat dissipation problems. Therefore, in order to solve the above problems, another stacked chip packaging structure has been developed.

Please refer to FIG. 2 , which is a schematic cross-sectional view of another conventional stacked chip packaging structure. The conventional stacked chip package structure 10 includes a package substrate 12 and a plurality of chip packages 200 a, 200 b, wherein the chip packages 200 a, 200 b are stacked on the package substrate 12 and electrically connected to the package substrate 12 . Each chip package 200 a , 200 b includes a package substrate 210 , a chip 220 , a plurality of bumps 230 , a primer 240 and a plurality of solder balls 250 . The chip 220 and the bumps 230 are disposed on the packaging substrate 210 , and the bumps 230 are disposed between the chip 220 and the packaging substrate 210 , and the chip 220 is electrically connected to the packaging substrate 210 through the bumps. The primer 240 is disposed between the chip 220 and the packaging substrate 210 to cover the bumps 230 .

The package substrate 210 has a plurality of conductive pillars 212 and a plurality of solder ball pads 214 , wherein the conductive pillars 212 respectively penetrate the package substrate 210 , and the solder ball pads 214 are respectively disposed on the conductive pillars 212 . In addition, the solder balls 250 are disposed on the solder ball pads 214 . It should be noted that the chip packages 200 a and 200 b are electrically connected to each other via the solder balls 250 , and the chip package 200 b is electrically connected to the package substrate 12 via the solder balls 250 .

Compared with the conventional stacked chip packaging structure 100, although the conventional stacked chip packaging structure 10 has lower manufacturing complexity, the conventional stacked chip packaging structure 10 The thickness is greater than that of the conventional stacked chip packaging structure 100 .

Contents of the invention

In view of this, the purpose of the present invention is to provide a chip package with a thinner overall thickness.

In addition, another object of the present invention is to provide a stacked chip packaging structure, which has a higher packaging density.

In addition, another object of the present invention is to provide a method for manufacturing a chip package to manufacture an embedded chip package.

Based on the above purpose or other purposes, the present invention provides a chip package, which includes a package substrate, a chip and a package compound. Wherein, the packaging substrate includes a core layer and a patterned circuit layer disposed on the core layer. The core layer has a first through hole and a plurality of second through holes, wherein the first through hole and the second through holes respectively expose part of the patterned circuit layer. The chip is arranged in the first through hole and is electrically connected with the patterned circuit layer. The encapsulant is disposed in the first through hole to fix the chip in the encapsulation substrate.

According to an embodiment of the present invention, the chip package may further include a plurality of external connection terminals (external terminals), which are respectively disposed in the second through holes, and each external connection terminal is electrically connected to the chip through the patterned circuit layer.

According to an embodiment of the present invention, the chip package may further include a plurality of bumps disposed between the chip and the patterned circuit layer, and the chip is electrically connected to the patterned circuit layer through these bumps, and the encapsulant covers these bump. In addition, the encapsulant may expose the surface of the chip away from the patterned circuit layer.

According to an embodiment of the present invention, the chip package may further include a plurality of wires, wherein the chip is electrically connected to the patterned circuit layer through the wires, and the encapsulant covers the wires.

Based on the above purpose or other purposes, the present invention proposes a stacked chip package structure, which includes a common carrier and a plurality of chip packages, wherein these chip packages are stacked on the common carrier and are electrically connected to the common carrier. connect. Each chip package includes a package substrate, a chip and a package glue. Wherein, the packaging substrate includes a core layer and a patterned circuit layer arranged on the core layer. The core layer has a first through hole and a plurality of second through holes, wherein the first through hole and the second through holes respectively expose part of the patterned circuit layer. The chip is arranged in the first through hole and is electrically connected with the patterned circuit layer. The encapsulant is disposed in the first through hole to fix the chip in the encapsulation substrate. The external connection terminals are respectively disposed in the second through holes, and each external connection terminal is electrically connected to the chip through the patterned circuit layer. Each chip package is electrically connected to the common carrier or another chip package via the corresponding external connection terminals.

According to an embodiment of the present invention, the common carrier may be a circuit board or a lead frame.

Based on the above purpose or other purposes, the present invention proposes a method for manufacturing a chip package, which includes the following steps. First, a chip and a packaging substrate are provided, wherein the packaging substrate includes a core layer and a patterned circuit layer disposed on the core layer, and a first through hole and a plurality of second through holes have been formed in the core layer, And the first through hole and the second through holes respectively expose part of the patterned circuit layer. The chip is arranged in the first through hole, so that the chip is electrically connected with the patterned circuit layer. An encapsulation compound is formed in the first through hole to fix the chip in the encapsulation substrate.

According to the embodiment of the present invention, the manufacturing method of the chip package can further form a plurality of external connection terminals in the second through holes, and each external connection terminal is electrically connected to the chip through the patterned circuit layer.

According to the embodiment of the present invention, the manufacturing method of the chip package can further form a plurality of bumps between the chip and the patterned circuit layer, and the chip is electrically connected to the patterned circuit layer through these bumps.

According to the embodiment of the present invention, the manufacturing method of the chip package can further form a plurality of wires, and these wires are connected between the chip and the patterned circuit layer.

Based on the above, the present invention embeds the chip into the core layer of the package substrate, so that the formed stacked chip package structure or chip package can be thinned.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a conventional stacked chip packaging structure.

FIG. 2 is a schematic cross-sectional view of another conventional stacked chip packaging structure.

3A to 3E are schematic cross-sectional views of the manufacturing process of the stacked chip packaging structure according to the first embodiment of the present invention.

4A to 4B are schematic cross-sectional views of the manufacturing process of the stacked chip packaging structure according to the second embodiment of the present invention.

5 is a schematic cross-sectional view of a chip packaging structure according to a third embodiment of the present invention.

10, 100: Existing known stacked chip packaging structure

12, 110, 210, 310: package substrate

20, 30: Stacked chip packaging structure

22, 32: shared carrier

22a, 22b, 214, 360: Solder ball pads

24, 250, 370: solder balls

120a, 120b, 220, 320, 410: chips

130: spacer

140, 420: wire

150, 340, 430: encapsulation colloid

200a, 200b, 300a, 300b, 300c, 400a, 400b, 400c, 500a: chip package

212, 350: Conductive column

230, 330: bump

240: primer

312: core layer

312a: first through hole

312b: second through hole

314: Patterned circuit layer

316: Solder mask layer

440: External connection terminal

510: Adhesive layer

Detailed ways

【The first embodiment】

3A to 3E are schematic cross-sectional views of the manufacturing process of the stacked chip packaging structure according to the first embodiment of the present invention. Please refer to FIG. 3A , the manufacturing method of the stacked chip packaging structure of this embodiment includes the following steps. Firstly, a packaging substrate 310 is provided, and the packaging substrate 310 can be a circuit board or a flexible circuit board. In addition, the packaging substrate 310 includes a core layer 312 and a patterned circuit layer 314 disposed on the core layer 312, wherein the core layer 312 may be Bismaleimide-Triazine (Bismaleimide-Triazine, BT ) materials, dielectric materials or other thin film materials. In addition, the package substrate 310 may also include a solder mask layer 316 , and the solder mask layer 316 is disposed on the core layer 312 and covers part of the patterned circuit layer 314 .

Then, a first through hole 312 a and a plurality of second through holes 312 b are formed in the core layer 312 , and the first through hole 312 a and the second through holes 312 b respectively expose part of the patterned circuit layer 314 . In addition, the method of forming the first through hole 312a and the second through hole 312b may be laser drilling, mechanical drilling or other processes capable of forming through holes.

Referring to FIG. 3B , a chip 320 is provided, and the chip 320 is disposed in the first through hole 312 a. Then, the chip 320 is electrically connected to the patterned circuit layer 314 , wherein the chip 320 is electrically connected to the patterned circuit layer 314 by flip-chip bonding technology. For the flip-chip bonding technology, the chip 320 is electrically connected to the patterned circuit layer 314 through the bump 330 . In this embodiment, the bumps 330 may be formed on the patterned circuit layer 314 or on the chip 320, and then undergo reflow so that the chip 320 can be connected to the patterned circuit layer by the bumps 330. 314 is electrically connected.

Referring to FIG. 3C , an encapsulant 340 is formed in the first through hole 312 a to fix the chip 320 in the encapsulation substrate 310 . In an embodiment of the present invention, the encapsulant 340 covers the bump 330 and part of the patterned circuit layer 314 . So far, the fabrication of the chip package 300a is preliminarily completed. It is worth mentioning that the encapsulant 340 of this embodiment can expose the surface of the chip 320 away from the patterned circuit layer 314 to improve the heat dissipation efficiency of the chip 320 . In other words, the encapsulant 340 exposes the backside of the chip 320 , but the encapsulant 340 can also completely cover the chip 320 . In addition, the encapsulant 340 and the encapsulation substrate 310 can also be aligned, but the encapsulant 340 can also protrude from the encapsulation substrate 310 .

Referring to FIG. 3D , a plurality of conductive pillars 350 are formed in the second through holes 312 b to be used as external connection terminals, and each conductive pillar 350 is electrically connected to the chip 320 through the patterned circuit layer 314 . In more detail, the method of forming the conductive pillars 350 may also be an electroless plating process, an electroplating process or other metal deposition processes. However, lead-free solder, tin-lead solder, other types of solder or other conductive materials may also be filled into the second through holes 312b to form external connection terminals (as shown in FIG. 4A ). As far as the conductive pillars 350 are used as external connection terminals, a plurality of solder ball pads 360 are formed on these conductive pillars 350 . Then, a plurality of solder balls 370 are formed on the solder ball pads 360 , and the solder balls 370 may be lead-free solder balls or tin-lead solder balls. So far, the fabrication of the chip package 300a is roughly completed.

Referring to FIG. 3E , the above steps are repeated to manufacture chip packages 300b and 300c. Then, a common carrier 22 is provided, and the common carrier 22 has a plurality of solder ball pads 22a and 22b. In this embodiment, the common carrier 22 is a circuit board, but the common carrier 22 may also be a lead frame. Then, the chip packages 300 a , 300 b and 300 c are stacked on the common carrier 22 , wherein the solder balls 370 of the chip packages 300 a , 300 b and 300 c are in contact with the corresponding solder ball pads 360 . In addition, the solder balls 370 of the chip package 300 c are in contact with the solder ball pads 22 a of the common carrier 22 . Then, a reflow process is performed on the above structure, so that the chip packages 300 a , 300 b and 300 c are electrically connected to each other, and the chip package 300 c is connected to the common carrier 22 .

It is worth mentioning that the chip packages 300a, 300b, and 300c are not limited to the arrangement shown in FIG. 3E , and the chip packages 300a, 300b, or 300c can also be flipped 180 degrees. If the chip package 300b is turned 180 degrees, at this time, the patterned circuit layers 314 of the chip packages 300b and 300c will face each other (similar to that shown in FIG. 4B ).

Then, a plurality of solder balls 24 are formed on the solder ball pads 22 b of the common carrier 22 to complete the fabrication of the stacked chip package structure 20 . The stacked chip package structure 20 can be disposed on a circuit board (not shown in the figure) through solder balls 24 . It is worth mentioning that the present embodiment does not limit the arrangement and quantity of the chip packages in the stacked chip package structure 20 .

Since the chip 320 of each chip package 300a, 300b and 300c is embedded in the core layer 312, the thickness of each chip package 300a, 300b and 300c can be reduced. In other words, the overall thickness of the stacked chip packaging structure 20 also becomes thinner. In addition, since each chip package 300a, 300b, and 300c is manufactured separately, defective chip packages will not be used in the stacked chip package structure 20, so as to improve the yield of the stacked chip package structure 20. . In addition, the backside of the chip 320 of each chip package 300a, 300b, and 300c is exposed, so the stacked chip package structure 20 can have better heat dissipation efficiency.

It is worth mentioning that in this embodiment, the chip packages 300 a , 300 b and 300 c are all flip-chip bonded packages, but wire bonded packages can also be used, which will be described in detail later.

【Second Embodiment】

4A to 4B are schematic cross-sectional views of the manufacturing process of the stacked chip packaging structure according to the second embodiment of the present invention. Please refer to FIG. 4A , this embodiment is similar to the above-mentioned embodiment, the difference is that after the chip 410 is placed in the first through hole 310a, a plurality of wires 420 are formed to connect the patterned circuit layer 314 and the chip 410 between. Similarly, an encapsulant 430 is formed in the first through hole 312 a to fix the chip 410 in the package substrate 310 , and the encapsulant 430 covers the chip 410 , the wire 420 and part of the patterned circuit layer 314 . So far, the fabrication of the chip package 400a is preliminarily completed.

It is worth mentioning that, in this embodiment, the encapsulant 430 protrudes from the packaging substrate 310 , however, the encapsulant 430 and the encapsulation substrate 310 may also be aligned. Then, lead-free solder, tin-lead solder, other types of solder or other conductive materials are filled into the first through holes 312b to form a plurality of external connection terminals 440 . However, the conductive posts 350 in the above embodiments can also replace the external connection terminals 440 in this embodiment.

Referring to FIG. 4B , the above steps are repeated to form chip packages 400b and 400c. A common carrier 32 is provided, and in this embodiment, the common carrier 32 is a lead frame, but the common carrier 32 can also be a circuit board (similar to that shown in FIG. 3E ). These chip packages 400 a , 400 b and 400 c are stacked on the common carrier 32 , and these chip packages 400 a , 400 b and 400 c are electrically connected to each other through external connection terminals 440 . In addition, the chip package 400c is electrically connected to the common carrier 32 through the external connection terminal 440 . Likewise, the stacked chip package structure 30 can also be configured on a circuit board (not shown) by solder or pre-solder.

It is worth mentioning that although the patterned circuit layers 314 of the chip packages 400 a and 400 b face each other, the present embodiment does not limit the arrangement and quantity of the chip packages in the stacked chip package structure 30 .

[Third embodiment]

Please refer to FIG. 5 , which is a schematic cross-sectional view of a chip package structure according to a third embodiment of the present invention. This embodiment is similar to the first embodiment, except that: an adhesive layer 510 is formed on a part of the chip 320 or on the patterned circuit layer 314 , and the chip 320 is bonded to the patterned circuit layer 314 . Then, a pin bonding process is performed to bond the patterned circuit layer 314 to the bump 330 , so that the patterned circuit layer 314 can be connected to the chip 320 via the bump 330 . In more detail, the pin bonding process may be an inner lead bonding (ILB) process for Tape Automatic Bonding (TAB).

Then, an encapsulant 340 is formed in the first through hole 312 a to fix the chip 320 in the package substrate 310 , and the encapsulant 340 covers the chip 320 , the bump 330 and part of the patterned circuit layer 314 . So far, the fabrication of the chip package 500a is preliminarily completed. It is worth mentioning that, in this embodiment, the encapsulant 340 completely covers the chip 320 , but the encapsulant 340 can also expose the backside of the chip 320 . Furthermore, the chip package 500a of this embodiment can also be used in the stacked chip package structure of the first embodiment or the second embodiment, and details will not be repeated here.

In summary, the present invention has at least the following advantages:

1. Since the chip is embedded in the core layer of the packaging substrate in the present invention, the thickness of the stacked chip packaging structure or the chip package of the present invention can be reduced.

2. The stacked chip package structure or chip package body of the present invention can be applied to a flip chip bonding process or a wire bonding process.

3. Compared with the prior art, the stacked chip package structure or chip package of the present invention has better heat dissipation efficiency.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention shall prevail as defined by the following claims.

Claims (10)

1. chip packing-body is characterized in that it comprises:

One base plate for packaging comprises a core layer and is configured in a patterned line layer on this core layer that wherein this core layer has one first perforation and a plurality of second perforation, and this first perforation and those second perforations expose partly this patterned line layer respectively;

One chip is configured in this first perforation, and electrically connects with this patterned line layer; And

One packing colloid is configured in this first perforation, so that this chip is anchored in this base plate for packaging.

2. chip packing-body according to claim 1 is characterized in that it more comprises a plurality of external connection terminals, be configured in respectively in those second perforations, and each those external connection terminals is electrically connected to this chip via this patterned line layer.

3. chip packing-body according to claim 1, it is characterized in that it more comprises a plurality of projections, be configured between this chip and this patterned line layer, and this chip is electrically connected to this patterned line layer via those projections, and this packing colloid coats those projections.

4. chip packing-body according to claim 1 is characterized in that it more comprises many leads, and wherein this chip is electrically connected to this patterned line layer via those leads, and this packing colloid coats those leads.

5. stack chip packaging structure is characterized in that it comprises:

One common carrier;

A plurality of chip packing-bodies are stacked on this common carrier, and electrically connect with this common carrier, and each those chip packing-body comprises:

One base plate for packaging comprises a core layer and is configured in a patterned line layer on this core layer that wherein this core layer has one first perforation and a plurality of second perforation, and this first perforation and those second perforations expose partly this patterned line layer respectively;

One chip is configured in this first perforation, and electrically connects with this patterned line layer;

One packing colloid is configured in this first perforation, so that this chip is anchored in this base plate for packaging; And

A plurality of external connection terminals, be configured in respectively in those second perforations, and each those external connection terminals is electrically connected to this chip via this patterned line layer, and each those chip packing-body is electrically connected to this common carrier or another those chip packing-bodies via those external connection terminals of correspondence.

6. stack chip packaging structure according to claim 5 is characterized in that wherein said common carrier comprises circuit board or lead frame.

7. the manufacture method of a chip packing-body is characterized in that it comprises:

One chip and a base plate for packaging are provided, wherein this base plate for packaging comprises a core layer and a patterned line layer that is configured on this core layer, and formed one first perforation and a plurality of second perforation in this core layer, and this first perforation and those second perforations expose this patterned line layer of part respectively;

With this chip configuration in this first perforation, so that this chip and this patterned line layer electrically connect; And

In this first perforation, form a packing colloid, so that this chip is anchored in this base plate for packaging.

8. the manufacture method of chip packing-body according to claim 7 it is characterized in that it more is included in a plurality of external connection terminals of formation in those second perforations, and each those external connection terminals is electrically connected to this chip via this patterned line layer.

9. the manufacture method of chip packing-body according to claim 7 it is characterized in that it more is included in a plurality of projections of formation between this chip and this patterned line layer, and this chip is electrically connected to this patterned line layer via those projections.

10. the manufacture method of chip packing-body according to claim 7 it is characterized in that it more comprises many leads of formation, and those leads connects between this chip and this patterned line layer.

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