CN1695245A - Lateral LUBISTOR structure and method - Google Patents

Abstract

An ESD LUBISTOR structure based on FINFET technology employs a vertical fin (a thin vertical member containing the source, drain and body of the device) in alternatives with and without a gate. The gate may be connected to the external electrode being protected to make a self-activating device and may be connected to a reference voltage. The device may be used in digital or analog circuits.

Description

LATERAL LUBISTOR STRUCTURE AND METHODS

technical field

The present invention relates generally to the field of integrated circuit fabrication, and in particular to the fabrication of devices for electrostatic discharge protection (ESD) in integrated circuit technology using FINFETs.

Background technique

FINFET is a promising integrated circuit technology that uses thin (10nm-100nm) vertical members as the source, drain and body of a field effect transistor (FET) and has a gate that is connected to two vertical sides adjacent to the top of the channel. With such a thin body, there is very strong gate coupling, making it easy to achieve fully depleted operation. These structures will require protection against overvoltages caused by electrical overstress (EOS) such as electrostatic discharge (ESD) and other voltage and current related overload phenomena during semiconductor manufacturing, shipping and testing. EOS phenomena include over-current overloads, latch-up overloads, and high currents that occur during testing and overloading. ESD phenomena and other phenomena can lead to electrical failure of the FINFET structure, ESD phenomena such as those in the Human Body Model (HBM), Mechanical Model (MM), Charged Device Model (CDM), Transient Latch Overload (TLU), Cable Discharge Model, Card Phenomena that occur during the course of the cassette model.

Therefore, it is clear that to provide adequate ESD protection for these structures, both EOS and ESD protection of the FINFET are required.

US Patent 6015993 presents a construction technique for lateral ESD devices with gated diodes, where the channel is formed in the device layer of a bulk silicon or SOI wafer. This structure is incompatible with FINFET structure and FINFET processing.

Contents of the invention

This invention relates to structures that provide EOS and ESD protection for FINFET technology.

According to one aspect of the invention, the ESD LUBISTOR structure based on FINFET technology uses vertical fins (50) (thin vertical members containing the source, drain and body of the device), with and without gates in alternative embodiments (60). The gate (60) can be connected to a protected external electrode (51) to make a self-activating device, or it can be connected to a reference voltage (92). The device can be used in digital or analog circuits.

Accordingly, in a substrate (10) based integrated circuit there is provided a structure comprising an elongated vertical member (50) comprising a semiconductor protruding from the substrate (10) and having a top (51) and Two opposite elongated sides (48, 49). A first electrode (52) is formed at a first end of the vertical member; and a second electrode (54) of opposite polarity is formed at an opposite second end of the vertical member. The first and second electrodes (52, 54) are doped with an electrode concentration greater than the dopant concentration of the central portion (52) of the vertical member, the vertical member being between the first and second electrodes.

Description of drawings

Figures 1A and 1B show a plan view and a cross-sectional view of an early stage device according to the present invention.

Figures 2-4 show cross-sectional views of later stages of the same device.

Figures 5 and 6 show examples of alternative embodiments.

Figure 7 shows a schematic diagram of the device in an ESD application.

Figure 8 shows a schematic diagram of a fin-resistor integrated with a FINFET.

Figure 9 shows another ESD application.

Detailed ways

ESD LUBISTOR structures based on FINFET technology use vertical fins (50) (thin vertical members containing the source, drain and body of the device), with and without gates (60) in alternative embodiments. The gate (60) can be connected to a protected external electrode (51) to make a self-excited device, or it can be connected to a reference voltage (92). The device can be used in digital or analog circuits.

The benefits that may arise from one or more preferred embodiments of the present invention are as follows:

Provides an ESD resistant structure, which is compatible with FINFET semiconductor process and structure;

Use ESD-resistant FINFET structure and support structure;

Provide fins with diode terminals separated by body, controlled by gate or not, with features such as p ⁺ /p ^- /n ⁺ , p ⁺ /n ^- /n ⁺ or p ⁺ /p ^- /n ^- /n ⁺ doping structure;

Provide lateral gate control diodes, formed on a layer of insulator, and have a p ⁺ /p ^- /n ⁺ structure or p ⁺ /n ^- /n ⁺ , or p ⁺ /p ^- /n ^- /n ⁺ , and lightly doped Miscellaneous bodies have body contacts;

providing a FINFET structure with body contacts that allows dynamic threshold FINFET devices to be used as ESD protection elements; and

FINFET resistor elements (gated or ungated) are provided to provide electrical and thermal stability of the FINFET device for ESD protection.

Referring now to the drawings, and more particularly to FIG. 1 , the process sequence according to the present invention includes an initial step of forming fins or vertical members (for fin-diode structures), which are conventional in FINFET technology. Typically, for example, nitride sidewalls are formed on dummy oxide mesas formed on a silicon layer (single crystal or epitaxial film), thereby forming a hardmask of suitable width (less than 10 nm). The silicon film may be single crystal silicon (including epitaxial layers). Polysilicon, selective silicon, strained silicon on silicon germanium films, or other films may also be used. The silicon is etched by a directional dry etch, leaving thin vertical features, for example 10 nm thick, 1 μm wide and 0.1 μm long, which will provide the electrodes and body of the device.

Referring to FIGS. 1A and 1B , the top view of FIG. 1B shows gate 60 above fin 50 extending in front of and behind the plane of the cross-section of FIG. 1A . In FIG. 1A , a substrate 10 has disposed thereon a fin 50 separated from a gate 60 by a gate dielectric 55 , for example a 1 nm oxide. In this example, the fins 50 are disposed directly on a silicon substrate, but some versions of the invention may have a dielectric between the substrate and the fins, eg, a buried insulator in a silicon-on-insulator (SOI) wafer. In this example, the substrate is an SOI substrate and buried oxide 20 is shown below device layer 10 . In some forms, fins can be formed from the device layer and disposed on the buried oxide. For example, fin 50 is initially doped with p ⁻ , as layer 10 . The gate 60 is polysilicon, which is later doped by implantation.

In FIG. 2, the gate implant step is shown, using a temporary layer 65, such as an anti-reflective coating, which is deposited during the steps of forming other devices in the circuit and which has been planarized, for example, by chemical Mechanical polishing planarizes to the level of the gate 60 . The gate 60 is doped with a heavy dose of either p or n ions. Preferably, gate 60 receives an N ⁺⁺ dose of about 10 ²¹ /cm ² . With this level of difference, any further doping the gate receives will not significantly affect its work function.

In Figures 3A and 3B, a non-critical hole is opened to expose cathode 52, which is implanted with N ⁺ (with a dose at least an order of magnitude smaller than the gate implant). Alternatively, holes may be opened in the ARC; or any other convenient mask, for example a layer of photoresist 67 may be deposited and patterned. FIG. 3B shows the same process, with the anode 54 implanted. Again, the dose (p ⁺ ) is one-tenth that of the gate.

The fins have been implanted at an early stage. If it is polysilicon and requires a single polarity, it can be implanted when it is deposited. Alternatively, the fins may be formed prior to the well implants, and holes may be opened in the photoresist for the well implants, such that the fins receive P and/or N implants simultaneously with the wells.

Reference is now made to FIG. 4, which shows the fin-diode device after deposition of the final interlayer dielectric, formation of contact holes 72, 74 and 76, and deposition of contact material. Since these contacts are at a lower level, tungsten (W) is suitable if it is used for other contacts at this level. If polysilicon is used at this level, a polysilicon contact is sufficient. For electrical interconnection, standard interconnection (Al or Cu) and inter-level dielectrics (ILD, inter-level dielectrics) processes can be used. Aluminum interconnect structures can include sticky refractory metals (eg, TiN), refractory metals (eg, Ti, TiNi, Co) and aluminum structures for adhesion, diffusion barrier, and providing good electrical conductivity. Copper interconnect structures may include adhesive films (eg, TaN), refractory metals (eg, Ta), and copper interconnects. Typically, for Cu interconnect structures, the structure is formed using a single damascene or dual damascene process. For ESD and resistor ballasting in these structures, refractory metals can be used because of their high melting temperature.

An advantage of the gate in this fin diode structure shown in FIG. 4 is that the current flow in the gated p ⁺ /n ⁻ /n ⁺ structure can be adjusted through electrical control of the gate structure. Thus, leakage, bias and electrical loading can be adjusted through the connection of the gate structure to the anode or cathode node, ground plane or power supply, voltage or current reference circuit or electrical network. The disadvantage of this gate is that it may damage the gate insulator. The circuit designer will make a choice based on a trade-off of advantages and disadvantages.

A group of several fin-diode structures can be arranged in parallel to provide lower overall series resistance and higher overall current carrying capability and higher power-to-failure of the ESD structure. For example, both the anode and cathode connections may be such as to allow electrical connection of parallel FINFET diode structures. These parallel structures may or may not use the same gate electrode. The number of paralleled components can also be customized or tailored based on ESD requirements or performance goals. Additionally, resistor ballasting may be present, and different gate biases may be established to improve current uniformity, or to provide a means of turning the element on or off. The advantages of paralleling elements over prior art devices are: 1) three-dimensional capability; 2) improved current ballast control; and 3) improved current uniformity control. In a two-dimensional single finger Lubistor structure, current uniformity is not inherent in the design, which leads to weakened ESD resistance per micron of cross-sectional area. In these structures, each fin-diode structure is thermally isolated from adjacent regions. This prevents thermal coupling between adjacent regions, thereby providing uniform thermal distribution and ESD resistance uniformity in each fin-diode parallel element.

Additionally, these fin-diode structures can be designed as p ⁺ /p ⁻ /n ⁺ elements or p ⁺ /n ⁻ /n ⁺ elements. The difference in the location of the metallurgical junction makes one embodiment preferable to another for a different purpose. This has been demonstrated experimentally by the inventors and is dependent on doping concentration and application. The choice is influenced by the capacitance-resistance trade-off and by the possibility of using implants for fin-diodes originally intended for certain other applications. When low resistance is better suited for the purpose at hand, and the available implants have relatively low doses, the p ⁺ /n ⁻ /n ⁺ structure is preferred because of its higher electron mobility. Conversely, when the implantable dose available is relatively high, the p ⁺ /p ⁻ /n ⁺ structure would be preferred.

Halo implants can be built into these devices to allow improved lateral conductance, better junction capacitance and improved breakdown characteristics. In this case, preferably only one doping polarity is provided with the halo, in order to prevent the formation of parasitic diodes by wrong halo implants of the wrong polarity.

Figure 5 shows an alternative version of the fin diode structure, where the channel is doped with ^P- and there is no separate gate. The advantage is that the gate is not exposed to ESD voltage overload. Electrical overloading in the gate dielectric can be eliminated by not allowing the gate structure to appear.

The CDM failure mechanism may occur due to the electrical connection of the gate structure of the FINFET ESD protection network. Although the previous embodiment includes gates that allow electrical control, this embodiment also requires more electrical connection and/or design area for the circuit. In the case of this embodiment, fewer electrical connections are necessary, allowing a denser circuit.

In the embodiment of FIG. 5, multiple fin-diode structures in parallel can be closely arranged to achieve high ESD tolerance per unit area. Additionally, resistor ballasting and current uniformity control can be addressed by varying the effective resistance within a single fin-diode structure. With physical separation of adjacent fin-diode structures, thermal coupling between adjacent components can be reduced. Optimization of the space between adjacent elements can be ensured by proper spacing and non-uniform adjacent spacing conditions to provide the best thermal results. This provides a set of thermal methods allowing optimization of components. This thermal approach cannot be used for two-dimensional Lubistor elements, but is a natural rule in building parallel fin-diode structures.

Similarly, Figure 6 shows a form in which the body is divided into two doped regions: a first ^P- and a second N ^- body region. The fin-diode structure allows optimization and placement of the metallurgical junction independently of the gate structure. The implant may be a p-well and/or n-well implant, or provided by a halo implant (eg, angled, helical, or straight), or other known implant or diffusion process steps. Gradient profiles introduced by p ⁺ /p ^-transitions and n ⁺ /n ^- transitions provide less abrupt junctions and may lead to improved ESD resistance.

Forms of devices with gates can be divided into several categories:

1) An N ⁺ /P fin-gated diode whose body contacts the substrate 10 . In this case, there is a path to the substrate.

2) N ⁺ /P fin-gated diode with floating body on SOI.

3) N ⁺ /P fin-gated diode on SOI, gate-contacted (P ⁺ ) body, allowing dynamic control of the anode potential.

4) N ⁺ /P fin-gated diode on SOI with gate contacting N ⁺ cathode.

In order to provide ESD protection for FINFET devices, it is advantageous to provide resistor elements integrated and/or not integrated into the FINFET device.

Referring to Figure 8, a FINFET device can be formed by similar techniques as used in the previous embodiments, with source and drain implants of the same polarity separated by bodies of opposite polarity. The body is covered by a gate insulator 55 and a gate 155 . This structure can be formed by symmetric or asymmetric implants to provide ESD benefits. In addition, in order to provide an ESD-resistant FINFET structure, resistors can be combined in the same structure. For example, a second gate 155' may be placed in series with the drain structure, where the second gate structure provides a barrier to heavily doped source/drain implants, such that the lightly doped fin provides resistance. The gate structure serves two functions: first, it provides a resistive region at the source or drain region; second, it provides a means to prevent the silicide film disposed on the source and drain region from shorting to the resistor. This forms a "ballast resistor" that is inherently integrated with the FINFET. We will call this structure a FIN-R-FET structure.

Alternatively, the second gate structure 155' can be removed from the FIN-R-FET, as is done in the fin-diode structure. Removing the second gate structure after silicidation allows preventing electrical overload or ESD problems with the resistor element.

The 150 elements used in FIN-R-FET devices can also be constructed as individual resistor elements. This is achieved by placing n-channel FINFETs in the n-well or n-body region. The resistor, or FIN-R device, can be used to provide ESD tolerance for FINFET, Fin-Diode, or in circuit applications. As discussed previously, the gate can be eliminated to avoid electrical overloading in the physical element.

In addition, to improve the ESD tolerance of FIN-FET devices, suicide can be removed from the source, drain and gate regions. Because the gate length of the device is relatively small compared to planar devices, suicide can be removed in the gate region.

Referring now to FIG. 7 , a schematic diagram of a typical arrangement for protecting a circuit from ESD on terminal 51 is shown. The dashed lines indicated with reference numerals 72 and 74 indicate selected portions discussed below. Two FIN-LUBISTORs according to the invention are connected between the protected node 53 and the voltage terminals 54 and 52'. In this case, the gate 60 is connected to the terminal 54 so that the ESD phenomenon dynamically reduces the resistance of one of the diodes. Optionally, terminal 60 may be connected to a power source. To avoid electrical overloading of the gate structure, circuits including FINFET devices may be used to electrically isolate the gate structure from electrical overloading. A circuit with a FINFET based converter, or a FINFET based reference control network to provide galvanic isolation from the power supply, prevents overloading and builds up a potential to avoid leakage.

In order to be used as an ESD network for the Human Body Model (HBM), Mechanical Model (MM) and other ESD phenomena, multiple lateral fin-diode structures must be used in parallel to minimize series resistance and to be able to discharge large currents through the structure without passing through the fins. - Malfunction in diode element or circuit. Therefore multiple parallel fin-diode elements are connected between the input pin and the power supply.

For voltage tolerance purposes, an ESD network constructed as fin-diode elements in a series configuration is shown in FIG. 7 , now including fin-diode 75 within dashed line 72 . A fin-diode structure can be constructed where the anode of the first fin-diode element is connected to the first pad and the cathode is connected to the anode of the second fin-diode. This can continue in a string or series structure. For each stage of the series structure, multiple parallel fin-diode elements may be provided for each "stage" of a string of fin-diodes. These strings can be placed between an input pin and a power supply, between two common power supply pads (such as VDD1 and VDD1), between any two different power supply pads (such as VCC and VDD), any ground rail (ground rail) (such as VSS1 and VSS2) and between any different ground rails (such as VSS and VEE). These fin-diode series elements can be arranged in a single series string or in a back-to-back configuration to allow bidirectional current flow between the two pads. For input pad to power supply, there is typically only a single fin-diode string to provide unidirectional current flow.

For HBM and Charged Device Model (CDM) phenomena, ESD circuits including fin-diode elements, fin-resistor (FIN-R) elements, and FINFETs can be used to improve ESD results. FIG. 9 is an example of a circuit providing ESD protection using a fin-diode 75, a fin-resistor 94, and a FINFET 96 with a grounded gate. For example, the gate voltage of the fin-diode is provided by the reference network, not by the ESD voltage itself. This allows better control over the current capacity of diode 75 .

Alternatively, resistor-ballasted FIN-R-FET components can be used to provide ESD protection. This circuit can be implemented in two ways. First, utilize a FIN-R resistor in series with the FINFET. To provide ESD protection, multiple parallel FIN-R resistors are placed in series with multiple FINFET devices. Another implementation can use multiple parallel FIN-R-FET structures for ESD protection. These aforementioned configurations can be configured as a cascode configuration for higher snapback voltage or voltage tolerance. For ESD protection, in the case of Fin-diode elements, series stages of FINFETs with FIN-R elements can be connected, where each stage comprises parallel groups of elements.

Devices constructed in accordance with the present invention are not limited to ESD applications, and may also be used in conventional devices in circuits such as digital, analog and radio frequency (RF) circuits. The invention is not limited to silicon wafers, other wafers such as SiGe alloy or GaAs may also be used. These structures can be placed on strained silicon films using deposited or grown SiGe films. These structures are suitable for silicon-on-insulator (SOI), RF SOI, and ultra-thin SOI (UTSOI).

While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be embodied in various forms within the scope of the appended claims.

industrial application

The invention can be applied to integrated circuit electronic devices and their manufacture.

Claims (14)

1. one kind based on the structure in the integrated circuit of substrate (10), comprising:

The vertical member (50) that prolongs comprises semiconductor, protrudes from described substrate (10), and has the limit (48,49) of top (51) and two relative prolongations, wherein

First electrode (52) be formed in first end of described vertical member and

Second electrode (54) with polarity relative with described first electrode is formed at second end of described vertical member, described relatively first end of described second end,

Described first and described second electrode (52,54) with the electrode doped in concentrations profiled, described electrode concentration is greater than the concentration of dopant in the core (53) between described first and second electrodes.

2. structure as claimed in claim 1, one of wherein said electrode (52,54) p ⁺Another n of doping and described electrode (52,54) ⁺Mix.

3. structure as claimed in claim 1, one of wherein said electrode (52,54) p ⁺Mix described core (53) p ^-Another n of doping and described electrode (52,54) ⁺Mix.

4. structure as claimed in claim 2, first subdivision (53A) of contiguous described first electrode of wherein said core (52) is with polarity identical with described first electrode (52) and lower doped in concentrations profiled, and second subdivision (53B) of contiguous described second electrode of described core (54) is with polarity identical with described second electrode (54) and lower doped in concentrations profiled.

5. structure as claimed in claim 2, wherein said dopant is set to p ⁺/ p ^-/ n ^-/ n ⁺In proper order.

6. as each described structure of claim 1 to 5, also comprise:

Grid (60) is arranged at core (53) top at described top and the core on close described both sides, and described grid (60) separates with described vertical member (50) by dielectric grid layer (55).

7. ESD protection circuit is connected in the outside terminal (51) of integrated circuit and comprises each described structure as claim 1 to 6.

8. ESD protection circuit as claimed in claim 7 also comprises two devices (75), and wherein said outside terminal is connected in the anode of first device (52) and the negative electrode of another device (54).

9. ESD protection circuit as claimed in claim 7, wherein said substrate (10) are the SOI substrates with one deck buried insulators (20), and described vertical member (50) directly is arranged on the described buried insulator layer (20).

10. ESD protection circuit as claimed in claim 7, wherein said substrate (10) are that body substrate and described vertical member (50) directly are arranged on the described body substrate.

11. ESD protection circuit as claimed in claim 7 comprises a plurality of fin-diode structures (75), these a plurality of fin-diode structures (75) externally are connected in parallel between terminal (51) and the voltage terminal (91,91 ').

12. ESD protection circuit as claimed in claim 7 comprises at least one fin-diode structure (75), this fin-diode structure (75) is connected between two outside terminals (51).

13. ESD protection circuit as claimed in claim 7 comprises at least one fin-diode structure (75) and at least one FIN-R resistor element (94).

14. ESD protection circuit as claimed in claim 7 comprises at least one fin-diode structure (75), at least one FIN-R resistor element (94) and at least one FINFET element (96).

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