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CN1075246C - Semiconductor device and method of fabricating the same - Google Patents

Semiconductor device and method of fabricating the same Download PDF

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CN1075246C
CN1075246C CN96123937A CN96123937A CN1075246C CN 1075246 C CN1075246 C CN 1075246C CN 96123937 A CN96123937 A CN 96123937A CN 96123937 A CN96123937 A CN 96123937A CN 1075246 C CN1075246 C CN 1075246C
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silicon layer
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oxide
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CN1160293A (en
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金载甲
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MagnaChip Semiconductor Ltd
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Hyundai Electronics Industries Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6708—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H10D30/6711—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect by using electrodes contacting the supplementary regions or layers
    • H10P90/1922—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10W10/181—

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Abstract

本发明披露了一种半导体器件及其制造方法。本发明的半导体器件包括：SOI晶片，它包括硅基片、形成于硅基片上部的绝缘膜、第一导电型硅层和形成于所述硅层与所述绝缘膜之间的传导层；形成于所述硅层的场氧化膜，它限定出第一和第二有源区；在所述第一有源区预定部分形成的栅电极；在所述栅电极两侧的第一有源区形成的第二导电型的源/漏区；在所述第二有源区形成的预定导电型的主体电极区。

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device of the present invention includes: an SOI wafer, which includes a silicon substrate, an insulating film formed on the top of the silicon substrate, a first conductivity type silicon layer, and a conductive layer formed between the silicon layer and the insulating film; A field oxide film formed on the silicon layer, which defines first and second active regions; a gate electrode formed in a predetermined portion of the first active region; a first active region on both sides of the gate electrode A source/drain region of a second conductivity type formed in the second active region; a body electrode region of a predetermined conductivity type formed in the second active region.

Description

半导体器件及其制造方法Semiconductor device and manufacturing method thereof

本发明涉及半导体器件及其制造方法，特别涉及没有基片浮置现象的SOI晶片及其制造方法。The invention relates to a semiconductor device and its manufacturing method, in particular to an SOI wafer without substrate floating phenomenon and its manufacturing method.

通常，SOI(绝缘层上生长硅)晶片可防止因半导体器件的寄生电容所引起的RC延迟时间，以及接合区域的漏电流等，从而提供可形成低功耗和高速动作的器件用基片。In general, SOI (Silicon On Insulator) wafers can prevent RC delay time caused by parasitic capacitance of semiconductor devices, leakage current in junction regions, etc., and provide substrates for devices that can form low power consumption and high-speed operation.

通过由形成了绝缘膜的器件晶片和支撑晶片进行粘附的方法，及向硅晶片深部注入氧离子而形成SIMOX(由注入的氧进行分离)的方法，制造这种SOI晶片。Such an SOI wafer is manufactured by a method of adhering a device wafer and a support wafer formed with an insulating film, and a method of implanting oxygen ions deep into a silicon wafer to form SIMOX (separation by implanted oxygen).

现有技术如图3所示，制备由支撑基片1、绝缘层2及形成器件的硅层3组成的SOI晶片100。其中，硅层3为掺杂第一导电型杂质的膜层，为了防止形成于SOI晶片上的MOS(金属氧化物半导体)晶体管的击穿及短路现象，应形成厚度为约300～1500的硅层3。在该硅层3预定部分用公知的LOCOS方法形成场氧化膜4，从而限定出有源区。其中，场氧化膜4下部与绝缘层2接触，使形成元件的有源区完全被分隔。在硅层3上部顺序形成栅氧化膜5和多晶硅膜，对栅氧化膜5与多晶硅膜构图，从而形成栅电极6。在栅电极6和场氧化膜4之间的硅层3上离子注入第二导电型杂质，形成源/漏区7。其中，源/漏区7与绝缘层2接触，因而不会产生接触电容和泄漏电流。此后，在所得整个结构上部蒸镀预定厚度的层间绝缘膜8，进行蚀刻以露出源/漏区7，然后形成与源/漏区7接触的金属布线9。Prior art As shown in FIG. 3 , an SOI wafer 100 composed of a supporting substrate 1 , an insulating layer 2 and a silicon layer 3 forming devices is prepared. Wherein, the silicon layer 3 is a film layer doped with impurities of the first conductivity type. In order to prevent the breakdown and short circuit phenomenon of the MOS (metal oxide semiconductor) transistor formed on the SOI wafer, it should be formed with a thickness of about 300-1500. Silicon layer 3. A field oxide film 4 is formed on a predetermined portion of the silicon layer 3 by a known LOCOS method, thereby defining an active region. Wherein, the lower part of the field oxide film 4 is in contact with the insulating layer 2, so that the active regions forming the elements are completely separated. A gate oxide film 5 and a polysilicon film are sequentially formed on the upper part of the silicon layer 3 , and the gate oxide film 5 and the polysilicon film are patterned to form a gate electrode 6 . Impurities of the second conductivity type are ion-implanted on the silicon layer 3 between the gate electrode 6 and the field oxide film 4 to form source/drain regions 7 . Wherein, the source/drain region 7 is in contact with the insulating layer 2, so no contact capacitance and leakage current will be generated. Thereafter, an interlayer insulating film 8 of a predetermined thickness is vapor-deposited on the entire structure obtained, etched to expose the source/drain regions 7, and then metal wiring 9 in contact with the source/drain regions 7 is formed.

可是，形成上述器件的硅层厚度为薄膜时，当沟道区完全被耗空之时，沟道区内的电位就会高于普通MOS晶体管的电位。而且，源区与沟道区间的电位位垒变低，在漏区侧的耗尽层中由碰撞离子生成的空穴在沟道区里暂时地堆积。此时，沟道区内的电位被提升，从源区开始向沟道区内急剧地注入电子，于是源、漏间的耐压变低，容易发生基片浮置现象。However, when the thickness of the silicon layer forming the above-mentioned device is a thin film, when the channel region is completely depleted, the potential in the channel region will be higher than that of an ordinary MOS transistor. Furthermore, the potential barrier between the source region and the channel becomes low, and holes generated by colliding ions in the depletion layer on the drain side temporarily accumulate in the channel region. At this time, the potential in the channel region is raised, and electrons are injected into the channel region rapidly from the source region, so the withstand voltage between the source and the drain becomes lower, and the substrate floating phenomenon easily occurs.

因此，本发明的目的是提供一种半导体器件及其制造方法，即在不影响集成度的范围内，形成主体电极区，从而可防止在SOI基片上发生的基片浮置现象。Therefore, it is an object of the present invention to provide a semiconductor device and its manufacturing method in which a body electrode region is formed within a range that does not affect the degree of integration, thereby preventing substrate floating on an SOI substrate.

本发明包括：SOI晶片，它具有硅基片、形成于硅基片上部的绝缘膜、第一导电型硅层和在所述硅层与所述绝缘膜之间形成的具有与所述硅层相同的导电型的传导层；形成于所述硅层，限定出第一和第二有源区的场氧化膜；形成于所述第一有源区预定部位的栅电极；形成于所述栅电极两侧的第一有源区的第二导电型源/漏区；以及形成于所述第二有源区的预定导电型主体电极区。The present invention comprises: SOI wafer, it has silicon substrate, the insulating film that is formed on the upper part of silicon substrate, the silicon layer of first conductivity type and the silicon layer that is formed between described silicon layer and described insulating film and described silicon layer A conduction layer of the same conductivity type; a field oxide film formed on the silicon layer to define the first and second active regions; a gate electrode formed at a predetermined position of the first active region; a gate electrode formed on the gate The second conductivity type source/drain region of the first active region on both sides of the electrode; and the predetermined conductivity type body electrode region formed in the second active region.

本发明半导体器件的制造方法，在SOI晶片上部制造存储器件的方法中，包括下列步骤：The manufacturing method of semiconductor device of the present invention, in the method for manufacturing memory device on SOI wafer, comprises the following steps:

提供形成有第一氧化膜的支撑基片；providing a support substrate formed with a first oxide film;

提供形成有场氧化膜的器件基片，该场氧化膜限定出第一有源区和第二有源区；providing a device substrate formed with a field oxide film defining a first active region and a second active region;

在所述器件基片上部形成第二氧化膜，以使所述第一和第二有源区的预定部分露出；forming a second oxide film on the upper portion of the device substrate to expose predetermined portions of the first and second active regions;

在第二氧化膜上部形成传导层使其包含所述露出的部分；forming a conductive layer on the second oxide film to include the exposed portion;

在所述传导层上部形成第二氧化膜；forming a second oxide film on the conductive layer;

所述器件基片的第二氧化膜与支撑基片的所述第一氧化膜表面接触，使所述器件基片与所述支撑基片接合；The second oxide film of the device substrate is in contact with the surface of the first oxide film of the supporting substrate, so that the device substrate is bonded to the supporting substrate;

蚀刻器件基片形成硅层，从而由所述支撑基片、硅层和所述基片与硅层之间的第一和第二氧化膜组成SOI晶片；Etching the device substrate to form a silicon layer, thereby forming an SOI wafer from the support substrate, the silicon layer, and the first and second oxide films between the substrate and the silicon layer;

在所述SOI晶片的硅层上掺杂第一导电型杂质；doping the silicon layer of the SOI wafer with impurities of the first conductivity type;

在所述沟道预定区域上部形成栅电极；forming a gate electrode on the upper portion of the channel predetermined region;

在所述硅层注入第二导电型杂质，在第一和第二有源区分别形成源/漏区和主体电极区，implanting impurities of the second conductivity type into the silicon layer, forming source/drain regions and body electrode regions in the first and second active regions respectively,

并且，所述传导层与所述硅层具有相同的导电型。Also, the conduction layer has the same conductivity type as the silicon layer.

下面，参照附图说明本发明实施例。Hereinafter, embodiments of the present invention will be described with reference to the drawings.

图1是按照本发明实施例在SOI晶片上形成的MOS晶体管(金属氧化物半导体晶体管)的剖面图；1 is a cross-sectional view of a MOS transistor (metal oxide semiconductor transistor) formed on an SOI wafer according to an embodiment of the present invention;

图2A-2C是按照本发明实施例在SOI晶片上制造MOS晶体管的制造方法剖面图；2A-2C are cross-sectional views of a manufacturing method for manufacturing a MOS transistor on an SOI wafer according to an embodiment of the present invention;

图3是现有SOI晶片上形成MOS晶体管的剖面图。FIG. 3 is a cross-sectional view of a MOS transistor formed on a conventional SOI wafer.

参见图1，在SOI基片200硅层的预定部分上，即硅层40的预定部分上形成场氧化膜31，该SOI晶片配置有硅支撑基片10、硅支撑基片10上部的氧化膜20和形成MOS晶体管的硅层40，从而限定出形成MOS晶体管的第一有源区AA和应形成主体电极区的第二有源区BB。其中，限定为第一有源区AA和第二有源区BB的硅层中掺有第一导电型、例如N型或P型杂质中的一种杂质。Referring to FIG. 1, a field oxide film 31 is formed on a predetermined portion of the silicon layer of the SOI substrate 200, that is, a predetermined portion of the silicon layer 40. The SOI wafer is equipped with a silicon support substrate 10 and an oxide film on the silicon support substrate 10 20 and the silicon layer 40 for forming the MOS transistor, thereby defining the first active region AA for forming the MOS transistor and the second active region BB for forming the body electrode region. Wherein, the silicon layer defined as the first active region AA and the second active region BB is doped with one impurity of the first conductivity type, such as N-type or P-type impurities.

在场氧化膜31之间的第一有源区AA形成栅氧化膜41和栅电极42。在栅电极两侧的第一有源区形成具有第二导电型的源/漏区43A、43B，在第二有源区形成主体电极区43C。其中，主体电极区43C与源/漏区43A、43B为同一种导电型，但其它实施例中也可为相反的导电型。A gate oxide film 41 and a gate electrode 42 are formed in the first active area AA between the field oxide films 31 . Source/drain regions 43A and 43B of the second conductivity type are formed in the first active region on both sides of the gate electrode, and a body electrode region 43C is formed in the second active region. Wherein, the body electrode region 43C and the source/drain regions 43A, 43B are of the same conductivity type, but in other embodiments, the conductivity type may also be opposite.

在硅层40与氧化膜20之间形成传导层33，由绝缘膜与硅支撑基片10绝缘。并且，传导层33由源/漏区43A、43B下部的绝缘膜32而与源/漏区43A、43B绝缘，源/漏区43A、43B之间的沟道区与主体电极区43C接触，即沟道区与主体电极区通过传导层33电气连接。其中，传导层33与形成器件的硅层40为含有同样的第一导电型杂质的硅层、多晶硅层或硅化物层。Conductive layer 33 is formed between silicon layer 40 and oxide film 20, and is insulated from silicon supporting substrate 10 by an insulating film. Moreover, the conductive layer 33 is insulated from the source/drain regions 43A, 43B by the insulating film 32 below the source/drain regions 43A, 43B, and the channel region between the source/drain regions 43A, 43B is in contact with the body electrode region 43C, that is, The channel region is electrically connected to the body electrode region through the conductive layer 33 . Wherein, the conductive layer 33 and the silicon layer 40 forming the device are a silicon layer, a polysilicon layer or a silicide layer containing the same impurities of the first conductivity type.

图2示出按本发明实施例在SOI晶片上制造MOS晶体管的方法，因而，首先参见图2A，提供硅(Si)支撑基片10和器件基片30，硅支撑片形成有第一氧化膜20A、器件基片30具有预定的传导型。在由Si或GaAs组成的器件基片30的周边面的预定部分通过例如公知的LOCOS方法形成场氧化膜31。其中，按如下方式形成场氧化膜31，亦即可以限定形成有器件的第一有源区AA以及以后将形成主体电极的第二有源区BB。2 shows a method for manufacturing MOS transistors on an SOI wafer according to an embodiment of the present invention. Therefore, referring to FIG. 2A at first, a silicon (Si) supporting substrate 10 and a device substrate 30 are provided, and the silicon supporting substrate is formed with a first oxide film 20A. The device substrate 30 has a predetermined conductivity type. Field oxide film 31 is formed on a predetermined portion of the peripheral surface of device substrate 30 composed of Si or GaAs by, for example, a known LOCOS method. Wherein, the field oxide film 31 is formed in such a way that the first active area AA where the device is formed and the second active area BB where the body electrode will be formed later can be defined.

在形成了场氧化膜31的器件基片30表面上，利用化学汽相淀积法淀积预定厚度的氧化膜32，然后，进行蚀刻，露出在第一有源区AA的器件沟道的预定区域和第二有源区BB的主体电极形成区域部分。On the surface of the device substrate 30 on which the field oxide film 31 is formed, an oxide film 32 with a predetermined thickness is deposited by chemical vapor deposition, and then etched to expose the predetermined portion of the device channel in the first active region AA. The region and the body electrode of the second active region BB form part of the region.

随后，形成传导层33，以使露出的器件基片30的沟道预定区和第二有源区BB的本体电极区域部分接触，该传导层33为与器件基片有同样导电类型，最好为硅层、多晶硅层、非晶硅或硅化物层。Subsequently, a conductive layer 33 is formed so that the exposed channel predetermined region of the device substrate 30 is in partial contact with the body electrode region of the second active region BB, the conductive layer 33 is of the same conductivity type as the device substrate, preferably It is a silicon layer, polysilicon layer, amorphous silicon or silicide layer.

在传导层33上部形成预定厚度的第二氧化膜20B，该氧化膜20B用作为形成SOI晶片的器件基片的埋置绝缘层，并为了使器件基片平坦化，对该露出的表面进行抛光。A second oxide film 20B having a predetermined thickness is formed on the upper portion of the conductive layer 33, the oxide film 20B is used as an embedded insulating layer for forming the device substrate of the SOI wafer, and the exposed surface is polished in order to planarize the device substrate. .

本发明中，在支撑基片10上部形成用作SOI晶片埋置绝缘膜的第一氧化膜20A，在器件基片30上部形成用作SOI晶片埋置绝缘膜的第二氧化膜20B。In the present invention, a first oxide film 20A serving as an SOI wafer embedded insulating film is formed on the support substrate 10, and a second oxide film 20B used as an SOI wafer embedded insulating film is formed on the device substrate 30.

其它方法是，在器件基片30上部形成用作SOI基片埋置绝缘层的第一氧化膜20A，和在支撑基片10上部形成用作传导层33和SOI晶片的埋置绝缘膜的第二氧化膜20B。Another method is to form the first oxide film 20A used as the SOI substrate embedded insulating layer on the device substrate 30, and form the first oxide film 20A used as the conductive layer 33 and the embedded insulating film of the SOI wafer on the supporting substrate 10. Dioxide film 20B.

如图2B所示，放置器件基片30和硅基片10，使器件基片的第二氧化膜20B和支撑基片的第一氧化膜20A接触，之后通过热处理工艺进行接合。接着，除去器件基片30，以使场氧化膜31A、31B的表面露出为止，从而形成器件用硅层40，即形成SOI基片200。不仅腐蚀器件基片30，并且进行化学的、机械的研磨清除，以使其表面平坦，从而形成硅层40。As shown in FIG. 2B , the device substrate 30 and the silicon substrate 10 are placed so that the second oxide film 20B of the device substrate is in contact with the first oxide film 20A of the supporting substrate, and then bonded by a heat treatment process. Next, the device substrate 30 is removed until the surfaces of the field oxide films 31A and 31B are exposed, thereby forming the silicon layer 40 for devices, that is, the SOI substrate 200 . The device substrate 30 is not only etched, but also chemically and mechanically removed to flatten its surface, thereby forming the silicon layer 40 .

如图2C所示，为了在硅层40形成器件，离子注入第一导电型、例如P或N型杂质，使其有导电性。然后，在硅层40上部形成厚150～200的栅氧化膜41，和在栅氧化膜上部形成预定厚度的多晶硅膜，接着，使多晶硅膜和栅氧化膜41构图，形成栅电极42。As shown in FIG. 2C , in order to form devices in the silicon layer 40 , ions of the first conductivity type, such as P or N type impurities, are implanted to make them conductive. Then, a gate oxide film 41 with a thickness of 150-200 Å is formed on the silicon layer 40, and a polysilicon film with a predetermined thickness is formed on the top of the gate oxide film. Then, the polysilicon film and the gate oxide film 41 are patterned to form a gate electrode 42.

在栅电极40两侧的第一有源区AA，离子注入第二导电型杂质，就形成源/漏区43A、43B，与此同时，在第二有源区BB离子注入第二导电型杂质，就形成主体电极区43C。因此，形成SOI晶片200上的MOS晶体管。In the first active region AA on both sides of the gate electrode 40, ions of the second conductivity type impurity are implanted to form source/drain regions 43A and 43B, and at the same time, the second conductivity type impurity is ion implanted in the second active region BB. , the body electrode region 43C is formed. Thus, MOS transistors on the SOI wafer 200 are formed.

本发明实施例中，若硅层4和传导层33为N型，则源/漏区43A、43B就为P型。另一方面，若硅层40和传导层33为P型，则源/漏区43A、43B就为N型。此时，虽然主体电极区43C与源/漏区43A、43B为相同导电型，但在其它实施例中它们也可具有不同的传导型。In the embodiment of the present invention, if the silicon layer 4 and the conductive layer 33 are N-type, then the source/drain regions 43A and 43B are P-type. On the other hand, if the silicon layer 40 and the conductive layer 33 are P-type, the source/drain regions 43A, 43B are N-type. At this time, although the body electrode region 43C is of the same conductivity type as the source/drain regions 43A, 43B, they may also have different conductivity types in other embodiments.

图2D是用于电连接上述MOS晶体管的金属布线工序的示意图，在形成MOS晶体管的硅层40上部形成预定厚度的层间绝缘膜44，进行刻蚀后，露出源、漏区43A、43B和主体电极区43C。然后，在该获得物表面上形成金属膜，以使金属膜与源、漏区43A、43B和主体电极区43C接触，对预定金属膜部分构图，于是形成电极布线45。2D is a schematic diagram of the metal wiring process for electrically connecting the above-mentioned MOS transistors. An interlayer insulating film 44 with a predetermined thickness is formed on the upper part of the silicon layer 40 forming the MOS transistors. After etching, the source and drain regions 43A, 43B and Body electrode region 43C. Then, a metal film is formed on the obtained surface so that the metal film is in contact with the source and drain regions 43A, 43B and the body electrode region 43C, a predetermined metal film portion is patterned, and electrode wiring 45 is formed.

本发明中，虽然利用杂质掺杂的硅作连接沟道区和连接主体电极区的传导层，但是，使用可掺杂导电型物质，如多晶硅、非晶硅、硅化物膜等，也能获得与本发明相同的效果。In the present invention, although impurity-doped silicon is used as the conductive layer connecting the channel region and the body electrode region, it can also be obtained by using dopable conductive materials, such as polysilicon, amorphous silicon, silicide film, etc. Same effect as the present invention.

以上对本发明进行了详细说明，即在不影响集成度的范围内，形成主体电极区，防止了SOI晶片上发生的基片浮置现象，从而改善了SOI器件特性。The present invention has been described in detail above, that is, within the range that does not affect the integration degree, the body electrode region is formed to prevent the floating phenomenon of the substrate on the SOI wafer, thereby improving the characteristics of the SOI device.

Claims (16)

1, a kind of semiconductor device is characterized in that comprising:
The SOI wafer, the dielectric film that it comprises silicon chip, form on silicon chip top, the first conductivity type silicon layer and the conducting shell that between described silicon layer and described dielectric film, forms with conductivity type identical with described silicon layer;
Field oxide film, it is formed at described silicon layer, and limits first active area and second active area;
Gate electrode, it is formed at the predetermined portions of the described silicon layer of described first active area;
Second conductive type source/drain region, it is formed at first active area of described gate electrode both sides; With
Be formed at the described silicon layer of described second active area, the main body electrode district of the predetermined conductivity type that contacts with described conducting shell.
2, semiconductor device as claimed in claim 1 is characterized in that, the conducting shell of described SOI substrate is the material that is mixed with predetermined conductive-type impurity.
3, semiconductor device as claimed in claim 2 is characterized in that, described conducting shell is to be selected from a kind of in silicon layer, polysilicon layer, amorphous silicon and the silicide layer.
4, semiconductor device as claimed in claim 1 is characterized in that, described conducting shell is that N type, described source/drain region are the P type.
5, semiconductor device as claimed in claim 1 is characterized in that, described conducting shell is that P type, described source/drain region are the N type.
6, semiconductor device as claimed in claim 1 is characterized in that, described main body electrode district has identical conductivity type with described source/drain region.
7, semiconductor device as claimed in claim 1 is characterized in that, described SOI wafer also comprises the source of being formed at/bottom, drain region, the dielectric film that source/drain region is separated with conducting shell.
8, semiconductor device as claimed in claim 7 is characterized in that, described dielectric film is an oxide-film.
9, a kind of manufacture method of semiconductor device is characterized in that, comprises the following steps: in the method for SOI wafer top manufacturing memory device
Provide the supporting substrate that forms first oxide-film;
The device substrate that has formed field oxide film is provided, and this field oxide film limits first active area and second active area;
Form second oxide-film on described device substrate top, so that the predetermined portions of described first and second active areas exposes;
Form conducting shell on the described second oxide-film top, make this conducting shell comprise the described part of exposing;
Form second oxide-film on described conducting shell top;
Second oxide-film of described device substrate is contacted with the surface of described first oxide-film of supporting substrate, described device substrate is engaged with described supporting substrate;
The etch device substrate forms silicon layer, thereby forms the SOI wafer by first and second oxide-films between described supporting substrate, silicon layer and described substrate and the silicon layer;
First conductive-type impurity mixes on the silicon layer of described SOI wafer;
Form gate electrode on described raceway groove presumptive area top;
Inject second conductive-type impurity at described silicon layer, form source/drain region and main body electrode district respectively at described first and second active areas,
And described conducting shell has identical conductivity type with described silicon layer.
10, method, semi-conductor device manufacturing method as claimed in claim 9 is characterized in that, a kind of in silicon layer, polysilicon layer, amorphous silicon layer and the silicide layer form described conducting shell by being selected from.
11, method, semi-conductor device manufacturing method as claimed in claim 9, it is characterized in that, between the step that forms described second oxide-film and the engagement step that described device substrate and supporting substrate are contacted, also comprise additional step, even the smooth flatening process step of second oxide-film.
12, method, semi-conductor device manufacturing method as claimed in claim 9 is characterized in that, makes the described second oxide-film planarization by etching process.
13, method, semi-conductor device manufacturing method as claimed in claim 9 is characterized in that, makes the described second oxide-film planarization by Ginding process chemistry, machinery.
14, method, semi-conductor device manufacturing method as claimed in claim 9 is characterized in that, after the step that forms described source/drain region and main body electrode district, also comprises the following steps:
Form interlayer dielectric on silicon layer top;
The etching interlayer dielectric exposes described source/drain region and main body electrode district;
Form metal line, described source/drain region of exposing is contacted with the main body electrode district.
15, method, semi-conductor device manufacturing method as claimed in claim 9 is characterized in that, described first conductivity type is a p type impurity, and second conductivity type is a N type impurity.
16, method, semi-conductor device manufacturing method as claimed in claim 9 is characterized in that, described first conductivity type is a N type impurity, and second conductivity type is a p type impurity.
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