CN1585121A - Flip-chip packaging structure with area bumps, flip-chip substrate and flip-chip assembly - Google Patents

Abstract

The invention relates to a flip chip packaging structure with an area bump, a flip chip substrate and a flip chip assembly. The first bumps are respectively electrically and mechanically connected with one of the first bonding pads of the chip to one of the first contact pads of the substrate corresponding to the first bumps, and the second bumps are respectively electrically and mechanically connected with the second bonding pads of the chip to the second contact pads of the substrate, wherein the size of the second bumps is larger than the respective size of the first bumps. It should be noted that, since the size of the second bumps is larger than the respective size of the first bumps, the flip chip package structure has better electrical performance and heat dissipation performance.

Description

Flip-chip packaging structure with area bumps, flip-chip substrate and flip-chip assembly

technical field

The invention relates to a flip-chip packaging structure, a flip-chip substrate and a flip-chip assembly in semiconductor devices in the field of electrical basic electrical components, in particular to a flip-chip packaging structure with regional bumps, a flip-chip substrate and a flip-chip assembly.

Background technique

Flip Chip Interconnect Technology (Flip Chip Interconnect Technology) mainly uses the arrangement of area arrays (arrays are arrays, hereinafter referred to as arrays) to arrange multiple bonding pads (die, chip That is, the active surface (active surface) of the chip (hereinafter referred to as the chip) and the bumps are formed on each pad, and after the chip is turned over (flip), the bumps on the pads of the chip are used to electrically Electrically and mechanically connected to the corresponding contact pads on the surface of the substrate or printed circuit board (PCB). In addition, flip-chip bonding technology can also pre-form bumps on the contact pads on the surface of the substrate or printed circuit board, and then use the pads on the active surface of the chip to connect electrically and mechanically to the corresponding bumps. . It is worth noting that because the flip-chip bonding technology can be applied to high pin count (High Pin Count) chip packaging structures, and has many advantages such as reducing the package area and shortening the signal transmission path, the flip-chip bonding technology has been adopted at present. Widely used in the field of chip packaging, the current common chip packaging structure using flip chip bonding technology, including flip chip ball grid array (Flip Chip Ball Grid Array, FC/BGA) and flip chip pin grid array (Flip Chip Pin Grid Array, FC/PGA) and other types of chip packaging structures.

Please refer to FIG. 1 and FIG. 2 at the same time, wherein FIG. 1 is a schematic top view of a conventional flip-chip package structure, and FIG. 2 is a schematic cross-sectional view of the I-I section in FIG. 1 . The conventional flip-chip package structure 100 includes a substrate 110 , a chip 130 , and a plurality of bumps 140 . As shown in FIG. 2 , the substrate 110 has a substrate surface 112 and a plurality of contact pads 114 , and these contact pads 114 are disposed on the substrate surface 112 of the substrate 110 . In addition, the chip 130 has an active surface (active surface) 132, wherein the active surface 132 of the chip 130 generally refers to the side of the chip 130 with an active device (not shown in the figure), and the chip 130 has a plurality of The welding pads 134 are disposed on the active surface 132 of the chip 130 and used as a medium for the signal input and output of the chip 130 , wherein the positions of the contact pads 114 are respectively corresponding to the positions of the welding pads 134 . In addition, the bumps 140 respectively electrically and mechanically connect one of the pads 134 to one of the corresponding contact pads 114 . Finally, an underfill 150 is filled in the space enclosed by the substrate 110 , the chip 130 and the bumps 140 to protect the contact pads 114 , the solder pads 134 and the exposed parts of the bumps 140 .

As far as the conventional flip-chip bonding technology is concerned, the solder pads of the chip that function as signal (signal), power (power) and ground (ground) are all electrically connected to the substrate through spherical bumps of the same size. of the corresponding contact pad. It is worth noting that since the electrical performance and heat dissipation performance of bumps of the same size are fixed, it is difficult to improve the electrical performance and heat dissipation performance of the chip after packaging, starting from the bumps of the same size. Therefore, if the designer wants to greatly improve the electrical performance and heat dissipation performance of the chip after packaging, it is necessary to start improving it in other ways.

It can be seen that the above existing flip-chip packaging structure, flip-chip substrate and flip-chip assembly still have many defects, and further improvement is urgently needed. In order to solve the defects of the existing flip-chip packaging structure, flip-chip substrate and flip-chip components, relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time. This is obviously the relevant industry urgent problem to be solved.

In view of the defects in the above-mentioned existing flip-chip packaging structure, flip-chip substrate and flip-chip components, the inventor actively researches and innovates based on his rich practical experience and professional knowledge in the design and manufacture of such products for many years, in order to Creating a new type of flip-chip packaging structure, flip-chip substrate, and flip-chip assembly with regional bumps can improve the general existing flip-chip packaging structure, flip-chip substrate, and flip-chip assembly, making it more practical. Through continuous research, design, and after repeated trial samples and improvements, the present invention with practical value is finally created.

Contents of the invention

The main purpose of the present invention is to overcome the defects of the above-mentioned existing flip-chip packaging structure, flip-chip substrate and flip-chip assembly, and provide a new flip-chip packaging structure with regional bumps. The main technical problems to be solved It is to make it possible to design the bumps in any shape in the lateral direction according to various special requirements on the electrical properties of the chip, so as to improve the electrical performance and heat dissipation performance of the chip after packaging, which is more suitable for practical use and has industrial advantages. on the use value.

Another object of the present invention is to provide a flip-chip substrate. The technical problem to be solved is that the bumps can be designed in any shape in the lateral direction according to various special requirements on the electrical properties of the chip, and the The electrical performance and heat dissipation performance of the chip after packaging are improved, so that it is more suitable for practical use and has industrial utilization value.

Another object of the present invention is to provide a flip-chip component. The technical problem to be solved is that the bump can be designed in any shape in the lateral direction according to various special requirements on the electrical properties of the chip, and the Improving the electrical performance and heat dissipation performance of the chip after packaging is more suitable for practical use and has industrial utilization value.

The purpose of the present invention and the solution to its main technical problems are achieved by adopting the following technical solutions. According to the present invention, a flip-chip packaging structure with regional bumps includes: a substrate with a first surface, a plurality of first contact pads and at least one second contact pad, wherein the second contact pad The area is larger than the individual areas of the first contact pads; at least one chip has an active surface, a plurality of first pads and at least one second pad, wherein the area of the second pad is larger than the area of the first pads An individual area of a pad; a plurality of first bumps, respectively connecting one of the first pads to one of the corresponding first contact pads; and at least one second bump, connecting the second Welding pads to the second contact pads, wherein the size of the second bump is larger than individual sizes of the first bumps.

The purpose of the present invention and the solution to its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned flip-chip package structure with area bumps, the size of the second bumps is twice the individual size of the first bumps.

In the aforementioned flip-chip package structure with area bumps, the first bumps are located on the periphery of the second bumps.

In the aforementioned flip-chip package structure with regional bumps, the first bonding pad is one of a signal chip bonding pad, a power chip bonding pad, and a ground chip bonding pad.

In the aforementioned flip-chip package structure with regional bumps, the second bonding pad is one of a power chip bonding pad, a grounding chip bonding pad, and a special signal chip bonding pad.

The aforesaid flip-chip package structure with regional bumps further includes a primer, and the primer is filled in the cavity surrounded by the substrate, the chip, the first bumps, and the second bumps.

The purpose of the present invention and its main technical problems are solved by adopting the following technical solutions. A flip-chip substrate according to the present invention includes: a substrate including a first surface, a plurality of first contact pads and at least one second contact pad, wherein the area of the second contact pad is larger than that of the first contact pads. An individual area of a contact pad; a plurality of first bumps, respectively connected to one of the corresponding first contact pads; and at least one second bump, connected to the second contact pad, wherein the The size of the second bump is larger than the individual size of the first bumps.

The purpose of the present invention and the solution to its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned flip-chip substrate, the size of the second bumps is twice the individual size of the first bumps.

In the aforementioned flip-chip substrate, the first bumps are located on the periphery of the second bumps.

The purpose of the present invention and its main technical problems are solved by adopting the following technical solutions. A flip-chip component proposed according to the present invention includes: a chip including an active surface, a plurality of first pads and at least one second pad, wherein the area of the second pad is larger than that of the first pads Individual areas of the pads; a plurality of first bumps respectively connected to one of the first pads; and at least one second bump connected to the second pad, wherein the size of the second bump is are larger than individual dimensions of the first bumps.

The purpose of the present invention and the solution to its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned flip-chip device, the size of the second bump is twice the individual size of the first bumps.

In the aforementioned flip-chip component, the first bumps are located on the periphery of the second bumps.

Compared with the prior art, the present invention has obvious advantages and beneficial effects. As can be seen from the above technical solutions, in order to achieve the aforementioned object of the invention, the main technical contents of the present invention are as follows:

The present invention provides a flip-chip packaging structure with regional bumps, which has a substrate, at least one chip, a plurality of first bumps (general bumps) and at least one second bump (regional bumps). Firstly, the substrate has a substrate surface, a plurality of first contact pads and at least one second contact pad, wherein the area of the second contact pad is larger than the individual areas of the first contact pads. In addition, the chip has an active surface, a plurality of first bonding pads and at least one second bonding pad, wherein the area of the second bonding pad is larger than the respective areas of the first bonding pads. In addition, the first bumps are respectively connected to one of the first pads and one of the corresponding first contact pads. Moreover, the second bump is connected to the second pad to the second contact pad, wherein the size of the second bump is larger than the individual size of the first bumps.

According to a preferred embodiment of the present invention, the size of the second bumps is double the individual size of the first bumps. In addition, these first bumps can be located on the periphery of the second bumps, wherein the first bonding pads are, for example, signal chip bonding pads, power chip bonding pads, or ground chip bonding pads, and the second chip bonding pads are, for example, power chip bonding pads. pads, ground chip pads, or special signal chip pads. Furthermore, a primer is filled in the space surrounded by the chip, the first bumps, the second bumps and the substrate.

Therefore, the flip-chip packaging structure with regional bumps of the present invention changes the shape of the bumps in the lateral direction, so that multiple bumps of the same group of power supply or ground can be integrated into bumps, so that a plurality of bumps can be relatively increased. The area before bump integration can increase the conductive area and heat dissipation area before the integration of multiple bumps, thereby improving the electrical performance and heat dissipation performance of the chip after packaging.

With the above technical solution, the flip-chip package structure with regional bumps of the present invention has at least the following advantages:

1. The flip-chip packaging structure with regional bumps of the present invention can design the bumps in any shape in the lateral direction according to various special requirements on the electrical properties of the chip, so that the electrical performance of the chip after packaging can be improved. Efficiency makes the flip-chip packaging structure of the present invention applicable to electronic products with special electrical requirements.

2. In the flip-chip packaging structure with regional bumps of the present invention, the size of the regional bumps is larger (this is relative to general bumps), so the heat dissipation performance of the chip after packaging can be improved, making the present invention The flip-chip packaging structure can be applied to electronic products with high power consumption.

To sum up, the special flip-chip package structure, flip-chip substrate and flip-chip assembly with regional bumps of the present invention, wherein, the flip-chip package structure can be bumped according to various special requirements on the chip’s electrical properties. The block is designed in any shape in the lateral direction, which can improve the electrical performance and heat dissipation performance of the chip after packaging; the flip-chip substrate can be designed according to various special requirements of the chip in the lateral direction. Any shape can improve the electrical performance and heat dissipation performance of the chip after packaging; the flip-chip component can design the bumps in any shape in the lateral direction according to various special requirements of the chip's electrical properties, and can Improve the electrical performance and heat dissipation performance of the chip after packaging. It has the above-mentioned many advantages and practical value, and it is indeed innovative in product structure. It has great improvement in both product structure and function. Compared with the existing flip-chip packaging structure, flip-chip substrate and flip-chip components, it has improved It has many functions, and has made great progress in technology, and has produced easy-to-use and practical effects. It has wide application value in the industry, so it is more suitable for practical use. It is a novel, progressive and practical new design.

The above description is only an overview of the technical solutions of the present invention. In order to understand the technical means of the present invention more clearly and implement them according to the contents of the description, the preferred embodiments of the present invention and accompanying drawings are described in detail below.

Description of drawings

FIG. 1 is a schematic top view of a conventional flip-chip package structure.

Fig. 2 is a schematic cross-sectional view of section I-I in Fig. 1 .

FIG. 3 is a schematic top view of a flip-chip package structure with area bumps according to a preferred embodiment of the present invention.

Fig. 4 is a schematic cross-sectional view of II-II section in Fig. 3 .

100: Flip Chip Package Structure 110: Substrate

112: Substrate surface 114: Contact pad

130: wafer (chip) 132: active surface

134: Welding pad 140: Bump

150: Primer 200: Flip chip package structure

210: Substrate 212: Substrate surface

214: Contact pads 216: Area contact pads

230: wafer (chip) 232: active surface

234: Welding pads 236: Area welding pads

240: bump 242: area bump

250: primer

Detailed ways

The specific structures, features and functions of the flip-chip packaging structure with regional bumps, flip-chip substrates, and flip-chip components according to the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments.

Please refer to FIG. 3 and FIG. 4 , wherein FIG. 3 is a schematic top view of a flip-chip package structure with area bumps according to a preferred embodiment of the present invention, and FIG. 4 is a schematic cross-sectional view of section II-II in FIG. 3 . The flip-chip package structure 200 of the preferred embodiment of the present invention includes a substrate 210, a chip 230 and a plurality of bumps, wherein:

The plurality of bumps include a plurality of first bumps and a second bump, wherein the first bumps are general bumps 240 , and the second bumps are at least one area bump 242 .

The substrate 210, as shown in FIG.

In addition, the chip 230 has an active surface 232, wherein the active surface 232 of the chip 230 generally refers to the side of the chip 230 with active components (not shown), and the chip 230 also has a plurality of welding pads 234 and a plurality of area pads 236 , and the pads 234 and the area pads 236 are all disposed on the active surface 232 of the chip 230 . Wherein, the positions of the bonding pads 234 and the regional bonding pads 236 are respectively corresponding to the positions of the contact pads 214 and the regional contact pads 216 .

In addition, these bumps 240 are respectively electrically and mechanically connected to one of these pads 234 to one of the corresponding contact pads 214, and these regional bumps 242 are respectively electrically and mechanically connected to the regional pads 236 to Its corresponding area is the contact pad 216 .

Please refer to FIG. 4, the primer 250 can be filled in the space surrounded by the substrate 210, the wafer 230, these bumps 240 and these regional bumps 242, so as to protect these bumps 240 and these regional bumps 242. The exposed part and provide proper elastic buffer between the substrate 210 and the wafer 230 . Therefore, the pads 234 of the chip 230 can be electrically and mechanically connected to the contact pads 214 of the substrate 210 through the bumps 240 respectively, and the area pads 236 of the chip 230 can be electrically and mechanically connected to the contact pads 214 through the area bumps 242 respectively. The area contact pads 216 are electrically and mechanically connected to the substrate 210 .

Please also refer to FIG. 4, these pads 234 can be used as the signal, power or ground transmission medium of the chip 230, so the pads 234 can be signal chip pads, power chip pads or ground chip pads, and These area pads 236 can be used as the power supply or ground transmission medium of the chip 230, so the area pads 236 can be power wafer pads or ground wafer pads, wherein the area of these area pads 236 can be larger than these pads 234 individual area. It should be noted that if there is a special signal that requires a larger current conduction area, the area pad 236 can also be used as a transmission medium for the special signal, and can be a chip pad for a special signal. In addition, since the regional bump 242 must provide a larger current conduction area, the size of the regional bump 242 must be larger than the individual sizes of these bumps 240 , and the difference between the two sizes may even be more than twice. In addition, since the circuit layout of most chips gathers power or ground at the center of the chip 230 , most of the bumps 240 will be arranged around the area bumps 242 .

Please continue to refer to shown in FIG. 4, because most of the pads 134 used as power supply or grounding shown in FIG. 2 are arranged in groups in the center of the active surface 132 of the chip 134, so The lateral shape of the regional pads 236a, 236c is, for example, L-shaped, which is used to replace the distribution of the existing pads used as power supply or grounding, and the lateral shape of the regional pad 236b, such as a rectangle, can also be used to replace the existing The distribution of pads that were originally used as power or ground. Therefore, the lateral shape of the regional bump 242 may correspond to the lateral shape of the regional pad 236 , and be L-shaped or square-shaped, or even other shapes. In addition, the areas of these regional contact pads 216 are also larger than the individual areas of these contact pads 214, and these contact pads 214 can also be located on the periphery of the regional contact pads 216, and the lateral shape of the regional contact pads 216a, 216c is, for example, L-shaped. , and the lateral shape of the area contact pad 216b is, for example, a rectangle. Based on the above, the lateral shape of the regional pad 236 may be the same as that of the corresponding regional contact pad 216 , but the areas of the two may be different.

Please also refer to FIG. 4 , when the area pad 236 is a power pad or a ground pad, since the area of the area pad 236 is relatively large, and the corresponding area bump 242 and area contact pad 216 The area is also relatively large, so a large current conduction area can be provided, which will help to improve the electrical performance of the chip 230 after packaging. In addition, due to the larger area of the area contact pad 216 , the heat conduction area of the area contact pad 216 increases, which will help to improve the heat dissipation performance of the chip 230 after packaging.

However, those familiar with the art should know that the area pads of the chip are not limited to power pads or ground pads. For special signals that require a larger current conduction area, the area pads of the chip of the present invention It can also be used as a soldering pad for the above-mentioned special signals to meet the electrical requirements of the chip in design. Therefore, the area pads can be power pads, ground pads or special signal pads.

Based on the above, the flip-chip package structure with regional bumps of the present invention has a substrate, at least one chip, a plurality of first bumps (general bumps) and at least one second bump (regional bumps). Wherein the second bump is connected to the second welding pad to the second contact pad, and the size of the second bump is larger than the individual size of the first bumps. It is worth noting that since the size of the second bumps is larger than the individual sizes of the first bumps, the flip-chip package structure will have better electrical performance and heat dissipation performance.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, may use the structure and technical content disclosed above to make some changes or modifications to equivalent embodiments with equivalent changes, but any content that does not depart from the technical solution of the present invention, Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solutions of the present invention.

Claims (12)

1, a kind of composite packing structure with zone projection is characterized in that it comprises:

One substrate has a first surface, a plurality of first contact mat and at least one second contact mat, and wherein the area of this second contact mat is other area greater than those first contact mats;

At least one wafer has an active surface, a plurality of first weld pad and at least one second weld pad, and wherein the area of this second weld pad is other area greater than those first weld pads;

A plurality of first projections connect one of those first weld pads respectively to one of its pairing those first contact mats; And

At least one second projection connects this second weld pad to this second contact mat, and wherein the size of this second projection is other size greater than those first projections.

2, the composite packing structure with zone projection according to claim 1, the size that it is characterized in that wherein said second projection are double other sizes in those first projections.

3, the composite packing structure with zone projection according to claim 1 is characterized in that wherein said those first projections are the peripheries that are positioned at this second projection.

4, the composite packing structure with zone projection according to claim 1, it is characterized in that wherein said first weld pad be for signal chip bonding pads, power supply chip bonding pads and ground connection chip bonding pads one of them.

5, the composite packing structure with zone projection according to claim 1, it is characterized in that wherein said second weld pad be for power supply chip bonding pads, ground connection chip bonding pads and special signal chip bonding pads one of them.

6, the composite packing structure with zone projection according to claim 1 is characterized in that it more comprises a primer, and this primer is filled in the cavity that this substrate, this wafer, those first projections and this second projection are surrounded.

7, a kind ofly cover brilliant substrate, it is characterized in that it comprises:

One substrate comprises a first surface, a plurality of first contact mat and at least one second contact mat, and wherein the area of this second contact mat is other area greater than those first contact mats;

A plurality of first projections, connecting respectively should be to one of its pairing those first contact mat; And

At least one second projection is connected to this second contact mat, and wherein the size of this second projection is other size greater than those first projections.

8, according to claim 7ly cover brilliant substrate, the size that it is characterized in that wherein said second projection is double other size in those first projections.

9, according to claim 7ly cover brilliant substrate, it is characterized in that wherein said those first projections are the peripheries that are positioned at this second projection.

10, a kind ofly cover brilliant assembly, it is characterized in that it comprises:

One wafer comprises an active surface, a plurality of first weld pad and at least one second weld pad, and wherein the area of this second weld pad is other area greater than those first weld pads;

A plurality of first projections are connected to one of those first weld pads respectively; And

At least one second projection is connected to this second weld pad, and wherein the size of this second projection is other size greater than those first projections.

11, according to claim 10ly cover brilliant assembly, the size that it is characterized in that wherein said second projection is double other size in those first projections.

12, according to claim 10ly cover brilliant assembly, it is characterized in that wherein said those first projections are the peripheries that are positioned at this second projection.

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