CN1210789C - Semiconductor package element with heat dissipation structure - Google Patents

Abstract

A semiconductor package element with a heat dissipation structure. The present invention is proposed to provide a semiconductor package component with high heat dissipation efficiency, effectively remove the heat generated by chip operation, and avoid chip failure due to overheating. It includes a substrate with upper and lower surfaces and a semiconductor chip; the upper surface of the substrate is respectively provided with an upper wire layer and an upper heat conductive layer; the semiconductor chip is combined with the upper heat conductive layer and electrically connected to the upper wire layer; the lower surface of the substrate is provided with a plurality of solder balls and a lower heat conductive layer, and a plurality of solder balls are provided on the surface of the lower heat conductive layer; the upper wire layer and some of the solder balls are connected by a plurality of conductive holes; a heat dissipation structure for connecting the upper heat conductive layer on the upper surface of the substrate and the remaining solder balls on the lower surface of the substrate is provided with a heat dissipation bump.

Description

Semiconductor package element with heat dissipation structure

technical field

The invention belongs to a semiconductor package assembly, in particular to a semiconductor package element with a heat dissipation structure.

Background technique

As shown in FIG. 1 , a conventional semiconductor package device includes a substrate 10 and a wafer 20 which are prepregs.

A layer of copper foil is attached to the upper and lower surfaces of the substrate 10, and upper and lower conductor layers 11, 12 are formed on the upper and lower surfaces respectively by means of lithography and etching, and the upper and lower conductor layers 11, 12 A plurality of via holes 13 are used for electrical connection. The via hole 13 is a plurality of through holes formed on the substrate 10 by drilling or laser, and a layer of copper metal is plated on the inner surface of the through hole by electroplating to conduct the upper and lower conductor layers 11 and 12. 14, and then plug the through hole.

A plurality of bonding pads 15 are disposed on the surface of the upper conductor layer 11 , and a plurality of solder ball pads 16 are disposed on the lower conductor layer 12 . In order to protect the upper and lower conductor layers 11, 12 from external influences, such as external force, moisture or corrosive substances, the surface of the upper conductor layer 11 is usually covered with a layer of green paint 17 and the bonding pad 15 is exposed to Outside, the surface of the lower conductor layer 12 is usually covered with a layer of tin ball cap 18 and exposes the solder ball pad 16 to the outside.

When the chip 20 is packaged, the bonding pad 19 of the chip 20 is electrically connected to the bonding pad 15 of the upper conductor layer 11 by bonding on the substrate 10, and then A plurality of solder balls 21 are soldered on the solder ball pads 16; finally, epoxy resin is used for injection molding to form a semiconductor package element. Since the chip 20 usually generates a large amount of heat during operation, if the heat cannot be discharged to the outside and remains inside the package component, it will cause the chip 20 to fail due to excessive temperature. Therefore, the semiconductor package component is usually provided with a thermal hole. twenty two. As shown in FIG. 1 , a plurality of thermal vias 22 are disposed on the substrate 10 below the chip 20 . The forming method of the heat conduction hole 22 is also manufactured by drilling, copper plating and plugging. One end of the heat conduction hole 22 is combined with the chip 20 by the adhesive 19, and the other end is by the solder ball pad. 16 is combined with the solder ball 21, and the heat of the chip 20 is transmitted to the outside through the conduction of the heat conduction hole 22 and the solder ball 21.

As the number of I/Os of the chip is increasing, the density is getting higher and the speed is getting faster and faster, the heat generated during the operation of the chip is also getting higher and higher, but the heat conduction heat that can be provided by the design of the thermal conduction hole 22 Due to the limited area, the heat inside the package cannot be effectively removed, so that there is still a large amount of heat remaining inside the package, resulting in the failure of the chip.

Contents of the invention

The object of the present invention is to provide a semiconductor package element with a heat dissipation structure which has high heat dissipation efficiency, effectively removes heat generated by wafer operation, and avoids failure of the wafer due to overheating.

The present invention includes a substrate and a semiconductor chip with upper and lower surfaces; the upper surface of the substrate is respectively provided with an upper conductive layer and an upper thermal conduction layer; the semiconductor chip is combined on the upper thermal conduction layer and electrically connected with the upper conductive layer; There are a plurality of solder balls and the lower heat conduction layer, and a plurality of solder balls are arranged on the surface of the lower heat conduction layer; the upper wire layer and some solder balls are connected by a plurality of via holes; the upper heat conduction layer on the upper surface of the substrate is connected to the lower surface of the substrate The rest of the solder balls are provided with a heat dissipation structure which is a heat dissipation bump for connecting the two.

in:

Between the lower surface of the substrate and the plurality of solder balls, there is a lower wire layer and a lower thermal conduction layer for bonding the solder ball pad; The ball pads, the lower heat conduction layer and the heat dissipation structure are connected to each other.

The lower conductor layer and the lower heat conduction layer on the lower surface of the substrate are covered with a layer of tin ball cover to expose the tin ball pads to the outside world.

The heat dissipation structure is a regular heat dissipation bump.

The heat dissipation structure is a plurality of irregular heat dissipation bumps.

The via hole is to form a through hole on the substrate by drilling or laser, and a conductive layer is formed on the inner peripheral surface of the through hole by electroplating, and then the hole is plugged.

A semiconductor wafer bonded to a substrate is a monolithic wafer.

The upper wire layer is provided with a plurality of inner pins; the semiconductor chip combined on the substrate is a flip chip, which is provided with a plurality of inner solder balls; The pins are coupled to each other.

The semiconductor chip is a multi-chip packaging module composed of two chips; two upper heat conduction layers and two lower heat conduction layers are respectively formed on the upper and lower surfaces of the substrate.

The semiconductor chip is a stacked multi-chip packaging module consisting of two sets of lower chips and upper chips stacked on the lower chip; two upper heat conduction layers and two lower heat conduction layers are respectively formed on the upper and lower surfaces of the substrate.

One of the two lower chips is provided with a plurality of inner solder balls; the upper wire layer is provided with a plurality of inner pins corresponding to the plurality of inner solder balls of the lower chip; the lower chip is combined on the substrate in a flip-chip manner and Coupling the inner solder balls with the inner pins of the upper conductor layer.

The top surfaces of the two chips of the multi-chip packaging module are combined with heat dissipation plates.

A plurality of heat conduction plugs are arranged between the chip and the upper heat conduction layer.

Between the two chips and the two upper heat-conducting layers, a plurality of heat-conducting plugs are respectively arranged to conduct the two chips.

Between the two lower chips and the two upper heat-conducting layers, a plurality of heat-conducting plugs are arranged respectively.

A plurality of heat conduction plugs are arranged between the lower chip and the upper heat conduction layer respectively.

A plurality of heat conduction plugs are arranged between a chip and an upper heat conduction layer.

Since the present invention includes a substrate and a semiconductor wafer with upper and lower surfaces; the upper surface of the substrate is respectively provided with an upper conductor layer and an upper heat conduction layer; the semiconductor wafer is combined on the upper heat conduction layer and is electrically connected with the upper conductor layer; There are a plurality of solder balls and a lower heat conduction layer, and a plurality of solder balls are arranged on the surface of the lower heat conduction layer; the upper wire layer and some solder balls are connected by a plurality of via holes; the upper heat conduction layer on the upper surface of the substrate is connected to the lower heat conduction layer of the substrate A heat dissipation structure, which is a heat dissipation bump, is provided between the remaining solder balls on the surface to connect them. The heat generated during the operation of the semiconductor chip is diffused through the heat dissipation structure connected to the upper heat conduction layer, and the heat dissipation area provided by it is obviously larger than the heat conduction hole of the conventional technology, so it can provide better heat dissipation efficiency for semiconductor package components ; That is, the heat dissipation structure is used to increase the heat dissipation area, so as to increase the heat dissipation efficiency of the semiconductor package element, and improve the stability of the chip inside the package element, the heat dissipation efficiency is high, the heat generated by the chip operation is effectively eliminated, and the chip fails due to overheating, so as to achieve this goal. purpose of the invention.

Description of drawings

FIG. 1 is a schematic cross-sectional view of the structure of a semiconductor package element.

Fig. 2 is a schematic sectional view of the structure of the present invention.

Fig. 3 is a schematic sectional view of the structure of the present invention (the heat dissipation structure is a plurality of irregular heat dissipation bumps).

Fig. 4 is a schematic sectional view of the structure of the present invention (the semiconductor wafer is a flip chip).

Fig. 5 is a schematic sectional view of the structure of the present invention (the semiconductor wafer is a multi-chip package module).

Fig. 6 is a schematic cross-sectional view of the structure of the present invention (the semiconductor wafer is a stacked multi-chip packaging module).

7 is a schematic cross-sectional view of the structure of the present invention (the semiconductor chip is a stacked multi-chip package module, and the heat dissipation structure is a plurality of irregular heat dissipation bumps).

8 is a schematic cross-sectional view of the structure of the present invention (the semiconductor chip is a flip-chip stacked multi-chip packaging module, and the heat dissipation structure is a plurality of irregular heat dissipation bumps).

Fig. 9 is a schematic cross-sectional view of the structure of the present invention (the semiconductor chip is a multi-chip packaging module, and the top surface of the chip is combined with a heat dissipation plate).

Detailed ways

The invention uses the heat dissipation structure to increase the heat dissipation area, so as to increase the heat dissipation efficiency of the semiconductor package element and improve the stability of the chip inside the package element.

As shown in FIG. 2 , the present invention includes a substrate 30 which is a prepreg or a material with insulating function and a semiconductor wafer which is a single wafer 20 .

A layer of copper foil is attached to the upper and lower surfaces of the substrate 30 respectively. The copper foil and the substrate 30 are usually mass-produced in the form of a composite substrate. An upper conductive layer 311 and an upper thermal conductive layer 312 are formed on the upper surface, and a lower conductive layer 32 and a lower thermal conductive layer 322 are formed on the lower surface. Of course, the above upper and lower conductive layers can also be made by using printed circuit methods. Special attention should be paid to the Except for some lines connected to each other for grounding, most of the wire layers and the heat conduction layer are not connected to each other to avoid short circuit.

A plurality of bonding pads 34 are provided on the surface of the upper conductor layer 311, and a top-sheet adhesive 33 is provided on the surface of the upper heat-conducting layer 312. The semiconductor system of the chip 20 is bonded to the substrate 30 by using the top-sheet adhesive 33, and the bonding pads of the chip 20 and The wiring pads 34 of the upper wire layer 311 are electrically connected by wire bonding. In addition, the surface of the upper wire layer 311 is usually covered with a layer of green paint 35 and the wire pads 34 are exposed to the outside world to protect the upper wire layer 311. Avoid being damaged by external influences, and will not affect the wiring operation between the chip 20 and the upper conductive layer 311, and in order to avoid the setting of the green paint 35 from affecting the heat conduction of the chip 20, the chip 20 and the upper thermal conductive layer 311 A plurality of heat conduction plugs 36 are arranged between them.

The surface of the lower conductor layer 32 and the lower heat conduction layer 322 is provided with a plurality of solder ball pads 37, and each solder ball pad 37 is welded with a solder ball 38. In addition, on the surface of the lower conductor layer 32 and the lower heat conduction layer 322 A layer of tin ball cover 39 is covered and the tin ball pad 37 is exposed to the outside world, so as to protect the lower conductor layer 32 and the lower heat conduction layer 322 from being damaged by external influences, and will not affect the soldering operation of the tin ball 38. Influence.

The upper conductive layer 311 and the lower conductive layer 32 are respectively connected by a plurality of via holes 40. The via holes 40 are formed on the substrate 30 by drilling or laser to form a plurality of through holes, and are formed on the through holes by electroplating. A layer of copper metal for connecting the upper and lower wire layers 311 and 32 is plated on the inner peripheral surface, and then the through holes are plugged.

The upper heat conduction layer 312 and the lower heat conduction layer 322 are connected to each other by a heat dissipation structure. The heat dissipation structure is a regular heat dissipation bump 41. The entire area of the heat dissipation bump 41 is used for heat dissipation of the chip 20. The present invention uses the heat dissipation bump 41 as a semiconductor package. The element heat dissipation structure provides a significantly larger heat dissipation area than the heat conduction hole 22 in the prior art, so it can provide better heat dissipation efficiency for the semiconductor package element.

Also as shown in Figure 3, the heat dissipation structure is composed of a plurality of irregular heat dissipation bumps 42, and the irregular heat dissipation bumps 42 can be applied to semiconductor packaging components of multilayer circuit boards, but they also have a larger area. The heat dissipation bump 42 replaces the heat conduction hole 22 of the prior art for heat dissipation, and the heat dissipation area provided by it is obviously larger than the heat dissipation hole 22 of the prior art, which helps to improve the heat dissipation efficiency of the chip 20, and the generated The heat is discharged out of the package body, therefore, the failure of the chip 20 due to overheating can be avoided and the operation performance of the package components can be improved.

As shown in FIG. 4 , the present invention includes a prepreg or a substrate 30 with an insulating function material and a flip-chip semiconductor wafer formed by bonding the wafer 20 on the substrate 30 downward.

The wafer 20 is provided with a plurality of internal solder balls (bump) 314 respectively coupled with the upper conductive layer 311 and the upper thermal conduction layer 312 on the substrate 30. Therefore, the position corresponding to the upper conductive layer 311 and the inner solder ball 314 of the chip 20 must be A plurality of internal pins 313 are provided to achieve electrical connection between the chip 20 and the upper conductor layer 311 . At this time, the wafer 20 and the substrate 30 are subjected to under fill 315, the purpose of which is to protect the inner solder balls 314 and increase the reliability of the packaged components. Finally, the chip 20 and the upper wire layer 311 can be packaged with epoxy resin to protect the internal components from being damaged by external force.

At present, multi-chip module (Multi-Chip Module) packaging has the advantages of saving packaging cost, packaging area and fast speed, so it has been widely used in semiconductor packaging technology. The most common system package (System Package) includes CPU The chip and the Northbridge chip are packaged on the same substrate or the Graphic chip and the Memory chip are packaged on the same substrate to form a package structure. The heat dissipation structure of the present invention can be used to dissipate heat between chips, whether they are stacked packages or horizontal packages.

As shown in FIG. 5 , the present invention includes a prepreg or a substrate 30 having an insulating function material and a semiconductor wafer of a multi-chip packaging module (MCM) composed of two wafers 20a and 20b.

An upper conductor layer 311 , two upper heat conduction layers 312 , a lower conductor layer 32 , and two lower heat conduction layers 322 are respectively formed on the upper and lower surfaces of the substrate 30 . Except for some lines connected between the wire layer and the heat conduction layer for grounding, most of the wire layer and the heat conduction layer are not connected to each other to avoid short circuit.

A plurality of bonding pads 34 are arranged on the surface of the upper wire layer 311, and the surface of the two upper heat-conducting layers 312 is respectively provided with an adhesive 33, and the two wafers 20a, 20b are combined on the substrate 30 by the adhesive 33, and the two wafers 20a , 20b and the wiring pad 34 of the upper wire layer 311 are electrically connected by wire bonding. In addition, the surface of the upper wire layer 311 is usually covered with a layer of green paint 35 and the wire pad 34 is exposed to the outside, to protect the upper conductor layer 311 from being damaged by external influences, and will not affect the wiring operation between the two wafers 20a, 20b and the upper conductor layer 311, and in order to avoid the setting of the green paint 35 on the two wafers 20a , 20b is affected by the heat conduction, between the two wafers 20a, 20b and the upper heat conduction layer 312, there are a plurality of heat conduction plugs 36 that conduct both of them.

A plurality of solder ball pads 37 are provided on the surface of the lower wire layer 32 and the two lower heat conduction layers 311, and each solder ball pad 37 is welded with a solder ball 38. In addition, the lower wire layer 32 and the lower heat conduction layer 322 The surface is covered with a layer of tin ball cover 39 and exposes the solder ball pad 37 to the outside world, protecting the lower conductor layer 32 and the lower heat conduction layer 322 from being damaged by external influences, and will not affect the soldering operation of the tin ball 38. Influence.

The upper conductive layer 311 and the lower conductive layer 32 are respectively connected by a plurality of via holes 40. The via holes 40 are formed on the substrate by drilling or laser to form a plurality of through holes, and are formed in the through holes by electroplating. The surrounding surface is plated with a layer of copper metal for connecting the upper and lower conductor layers 311, 32, and then the through holes are plugged.

The upper heat conduction layer 312 and the lower heat conduction layer 322 are connected to each other by a heat dissipation structure. The heat dissipation structure is a regular heat dissipation bump 41. The entire area of the two heat dissipation bumps 41 is used for heat dissipation of the chips 20a and 20b. Therefore, the present invention uses heat dissipation bumps 41 is used as the heat dissipation structure of the semiconductor package element, and the heat dissipation area provided by it is obviously larger than that of the heat conduction hole 22 in the prior art, so it can provide better heat dissipation efficiency for the semiconductor package element.

As shown in FIG. 6 , the present invention includes a substrate 30 that is a prepreg or a material with an insulating function, and a stacked multi-layer multi-layer system composed of two groups of lower wafers 20a, 20b and upper wafers 20c, 20d stacked on the lower wafers 20a, 20b. Chip packaging module (MCM) semiconductor wafer.

An upper conductor layer 311 , two upper heat conduction layers 312 , a lower conductor layer 32 , and two lower heat conduction layers 322 are respectively formed on the upper and lower surfaces of the substrate 30 . Except for some lines connected between the wire layer and the heat conduction layer for grounding, most of the wire layer and the heat conduction layer are not connected to each other to avoid short circuit.

A plurality of wire bonding pads 34 are provided on the surface of the upper conductor layer 311, and an upper film glue 33 is respectively provided on the surface of the two upper heat conduction layers 312, and the lower chips 20a, 20b stacked with the upper chips 20c, 20d are bonded by the upper film glue 33 On the substrate 30, the bonding pads of the upper and lower chips 20c, 20d, 20a, 20b and the wiring pads 34 of the upper wiring layer 311 are electrically connected by wire bonding. In addition, the surface of the upper wiring layer 311 is usually covered with A layer of green paint 35 and the bonding pad 34 are exposed to the outside world to protect the upper wiring layer 311 from being damaged by external influences, and will not affect the upper and lower chips 20c, 20d, 20a, 20b and the upper wiring layer 311 In order to prevent the setting of the green paint 35 from affecting the heat conduction of the upper and lower wafers 20c, 20d, 20a, and 20b, the lower wafers 20a, 20b and the upper heat-conducting layer 312 are provided with a conductive A plurality of heat conducting plugs 36.

A plurality of solder ball pads 37 are provided on the surface of the lower wire layer 32 and the two lower heat conduction layers 322, and each solder ball pad 37 is welded with a solder ball 38. In addition, the lower wire layer 32 and the lower heat conduction layer 322 The surface is covered with a layer of tin ball cover 39 and exposes the solder ball pad 37 to the outside world, protecting the lower conductor layer 32 and the lower heat conduction layer 322 from being damaged by external influences, and will not affect the soldering operation of the tin ball 38. Influence.

The upper conductive layer 311 and the lower conductive layer 32 are respectively connected by a plurality of via holes 4, and the via holes 40 are formed on the substrate 30 by drilling or laser. The inner peripheral surface of the hole is plated with a layer of copper metal for conducting the upper and lower wire layers 311, 32, and then the through hole is plugged.

The upper heat conduction layer 312 and the lower heat conduction layer 322 are connected to each other by a heat dissipation structure. The heat dissipation structure is a regular heat dissipation bump 41. The entire area of the two heat dissipation bumps 41 is used for heat dissipation of the upper and lower chips 20c, 20d, 20a, and 20b. Therefore, the present invention uses the heat dissipation bump 41 as the heat dissipation structure of the semiconductor package component, and the heat dissipation area provided by it is obviously larger than that of the heat conduction hole in the prior art. Therefore, it can provide better heat dissipation efficiency for the semiconductor package component.

Also as shown in FIG. 7, the heat dissipation structure for connecting the upper and lower heat conduction layers 312, 322 is composed of a plurality of irregular heat dissipation bumps 42, and the irregular heat dissipation bumps 42 can be applied to semiconductors of multilayer circuit substrates. Packaged components, but it also replaces the thermal conduction holes 22 of the prior art with the larger heat dissipation bumps 42 to dissipate heat, and the heat dissipation area provided by it is obviously larger than the heat dissipation holes 22 of the prior art, which helps to improve the chip The heat dissipation efficiency of the chip 20 is high, and the heat generated by it is discharged out of the package body, so that the chip 20 can be prevented from failure due to overheating and the operation efficiency of the package component can be improved.

As shown in FIG. 8 , the present invention includes a substrate 30 that is a prepreg or a material with an insulating function, and a stacked multi-layer multi-layer composite system composed of two groups of lower wafers 20a, 20b and upper wafers 20c, 20d stacked on the lower wafers 20a, 20b. Chip packaging module (MCM) semiconductor wafer.

The lower chip 20 b is a flip-chip bonded downward on the substrate 30 , and a plurality of internal solder bumps (bumps) 314 respectively coupled to the upper conductive layer 311 and the upper thermal conductive layer 312 on the substrate 30 are provided on it.

The heat dissipation structure for connecting the upper and lower heat conduction layers 312, 322 is composed of a plurality of irregular heat dissipation bumps 42, and the irregular heat dissipation bumps 42 can be applied to semiconductor packaging components of multilayer circuit boards, but they are also based on The larger heat dissipation bump 42 replaces the heat conduction hole 22 of the prior art to dissipate heat, and the heat dissipation area provided by it is obviously larger than the heat dissipation hole 22 of the prior art, which helps to improve the upper and lower wafers 20c, 20d, 20a, 20b have high heat dissipation efficiency and discharge the generated heat out of the package. Therefore, the upper and lower chips 20c, 20d, 20a, 20b can avoid failure due to overheating and improve the operating performance of the packaged components.

As shown in FIG. 9 , the present invention includes a prepreg or a substrate 30 having an insulating function material and a semiconductor wafer of a multi-chip package module (MCM) composed of two wafers 20a and 20b.

The top surfaces of the chips 20a, 20b are respectively combined with heat dissipation plates 43a, 43b to increase the heat dissipation effect of the packaged components. The chip 20 b is a flip chip bonded downwards on the substrate 30 , and there are a plurality of inner bumps 314 respectively coupled to the upper conductive layer 311 and the upper thermal conduction layer 312 on the substrate 30 .

An upper conductor layer 311 , two upper heat conduction layers 312 , a lower conductor layer 32 , and two lower heat conduction layers 322 are respectively formed on the upper and lower surfaces of the substrate 30 . Except for some lines connected between the wire layer and the heat conduction layer for grounding, most of the wire layer and the heat conduction layer are not connected to each other to avoid short circuit.

The heat dissipation structure for connecting the upper and lower heat conducting layers 312, 322 is composed of a plurality of irregular heat dissipation bumps 42, and the irregular heat dissipation bumps 42 and the heat dissipation plates 43a, 43b combined on the top surfaces of the chips 20a, 20b can be used The semiconductor package element on the multi-layer circuit board replaces the thermal conduction hole 22 of the prior art with the large-area heat dissipation bump 42 and the heat dissipation plate 43a, 43b to dissipate heat, and the heat dissipation area provided by it is obviously larger than that of the prior art. The heat dissipation holes 22 are large, which help to improve the heat dissipation efficiency of the chips 20a, 20b, and discharge the heat generated by them out of the package body, so that the chips 20a, 20b can be prevented from failing due to overheating and thus improve the reliability of the packaged components. operating performance.

Claims (17)

1, a kind of semiconductor encapsulated element with radiator structure, it comprises substrate and the semiconductor wafer with upper and lower surface; Upper surface of base plate is respectively equipped with upper conductor layer and goes up heat-conducting layer; Semiconductor wafer is incorporated on the heat-conducting layer and with upper conductor layer and electrically connects; Base lower surface is provided with a plurality of tin balls and reaches heat-conducting layer down, is provided with a plurality of tin balls in following heat-conducting layer surface; Utilize a plurality of vias to be connected between upper conductor layer and the part tin ball; Be provided with between the last heat-conducting layer that it is characterized in that described upper surface of base plate and the rest tin of base lower surface and use the radiator structure that is connected both for the heat radiation projection.

2, the semiconductor encapsulated element with radiator structure according to claim 1 is characterized in that being provided with between described base lower surface and the plural tin ball tool and uses the lower wire layer that combines the tin ball pad and heat-conducting layer down; Plural number tin ball is connected to each other through tin ball pad, lower wire layer, via and upper conductor layer and through tin ball pad, following heat-conducting layer and radiator structure respectively.

3, the semiconductor encapsulated element with radiator structure according to claim 2, it is characterized in that described base lower surface lower wire layer and down the heat-conducting layer surface coverage one deck tin ball cover is arranged and makes the tin ball pad be exposed to the external world.

4, the semiconductor encapsulated element with radiator structure according to claim 1 is characterized in that described radiator structure is the heat radiation projection of a rule.

5, the semiconductor encapsulated element with radiator structure according to claim 1 is characterized in that described radiator structure is a plurality of irregular heat radiation projections.

6, the semiconductor encapsulated element with radiator structure according to claim 1, it is characterized in that described via is to form through hole with boring or laser mode on substrate, and form conductive layer in the through hole inner peripheral surface, and then carry out consent with plating mode.

7,, it is characterized in that the described semiconductor wafer that is incorporated on the substrate is a single-wafer according to claim 1,2,3,4,5 described semiconductor encapsulated elements with radiator structure.

8,, it is characterized in that described upper conductor layer is provided with a plurality of interior pins according to claim 1,2,3,4,5 described semiconductor encapsulated elements with radiator structure; Being incorporated into substrate semiconductor-on-insulator wafer is flip chip, and it is provided with tin ball in the plural number; Wafer be incorporated on the substrate in the flip chip mode and make in tin ball and the upper conductor layer pin be coupled mutually.

9,, it is characterized in that the polycrystalline sheet encapsulation module of described semiconductor wafer for constituting with two wafer according to claim 1,2,3,4 or 5 described semiconductor encapsulated elements with radiator structure; The upper and lower surface of substrate forms heat-conducting layer and twice heat-conducting layers on two respectively.

10, according to claim 1,2,3,4 or 5 described semiconductor encapsulated elements with radiator structure, it is characterized in that described semiconductor wafer for two groups by lower wafer and be stacked in the stack polycrystalline sheet encapsulation module that wafer constitutes on the lower wafer; The upper and lower surface of substrate forms heat-conducting layer and twice heat-conducting layers on two respectively.

11, the semiconductor encapsulated element with radiator structure according to claim 10 is characterized in that a slice lower wafer is provided with tin ball in the plural number in described two lower wafers; For upper conductor layer be provided with in a plurality of and this lower wafer plural number the tin ball corresponding in pin; This lower wafer be incorporated on the substrate in the flip chip mode and make in tin ball and the upper conductor layer pin be coupled mutually.

12, the semiconductor encapsulated element with radiator structure according to claim 9 is characterized in that describedly being combined with heating panel for the two plates end face of polycrystalline sheet encapsulation module.

13, the semiconductor encapsulated element with radiator structure according to claim 7 is characterized in that being provided with between described wafer and the last heat-conducting layer a plurality of heat conduction bolts of conducting.

14, the semiconductor encapsulated element with radiator structure according to claim 9 is characterized in that being respectively equipped with between the heat-conducting layer on described two plates and two a plurality of heat conduction bolts of conducting.

15, the semiconductor encapsulated element with radiator structure according to claim 10 is characterized in that being respectively equipped with between the heat-conducting layer on described two lower wafers and two a plurality of heat conduction bolts of conducting.

16, the semiconductor encapsulated element with radiator structure according to claim 11 is characterized in that being respectively equipped with between the heat-conducting layer on a described lower wafer and one a plurality of heat conduction bolts of conducting.

17, the semiconductor encapsulated element with radiator structure according to claim 12 is characterized in that being provided with between the heat-conducting layer on a described wafer and one a plurality of heat conduction bolts of conducting.

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