CN1262004C - Metal Pad Structure for Bonding Pads and Sense Pads - Google Patents

Abstract

A bonding pad area structure is arranged on a semiconductor chip with a circuit, comprising: a bottom metal layer, arranged on the surface of the semiconductor chip and electrically connected to its circuit; an intermetallic dielectric layer, covering the surface of the bottom metal layer, and a metal plug structure in contact with the bottom metal layer is embedded in the intermetallic dielectric layer; a top metal layer, arranged on the surface of the intermetallic dielectric layer; and a protective layer, arranged on the top metal layer, having a plurality of openings, exposing the portion of the top metal layer to be bonded to serve as a bonding pad; wherein the bonding pad has a marking shape to define the relative position of the bonding pad on the semiconductor chip.

Description

Metal Pad Structure for Bonding Pads and Sense Pads

technical field

The present invention relates to a semiconductor manufacturing process, and in particular to a metal pad with a marking shape.

Background technique

Generally, after the integrated circuit on the wafer is manufactured, the top metal layer on the surface is defined as a plurality of bonding pads, which are respectively electrically connected to the underlying metal interconnection structure to complete the manufacturing of the IC chip. Then, after cutting out the IC chip (die) from the wafer, electronic packaging (Electronic Packaging) is performed.

In electronic assembly, the IC chip is wire bonded with metal wires through a bonder, so as to connect the bonding pads on the IC chip with the corresponding pins on the assembly substrate or lead frame. In other words, the bonding pad serves as an interface between the internal circuit of the chip and the external signal pins, and the external signal is nothing more than a power signal, a ground signal, or an input/output signal and so on.

In a typical IC chip, active circuit components such as transistors, resistors, etc., are formed in the center of the chip (active area), and bonding pads are usually arranged around the active area to avoid subsequent chipping. Damage to components in the active area during wire bonding. There are also designs where the bonding pads are placed in the center of the chip and the active circuit components are placed on the outside.

However, conventional bonding pad structures are usually square or rectangular. The following problems may occur. Referring to FIG. 1, the chip arrangement on a conventional wafer is illustrated. Generally, a plurality of wafer regions, such as 12A and 12B, are formed on the wafer 10 with dicing streets 16 therebetween. Generally, a plurality of alignment marks (markers, 14A˜14C) are arranged on the dicing line 16 for alignment during the manufacturing process. However, after the integrated circuit manufacturing process is completed, the wafer area must be cut off from the wafer 10 first. For the wafer area 12A, the alignment marks 14A and 14B can be aligned during dicing, but for the incomplete wafer area 12B, there is a lack of diagonal alignment marks, so , prone to cutting alignment problems.

Next, the design of the bonding pads on the conventional chip will be described with reference to FIG. 2A and FIG. 2B . It can be seen from FIG. 2A that when the chip 20A is cut from the wafer, it is rectangular, and the bonding pads 22A on it are also rectangular with equal size, and are evenly arranged on the long sides of the chip 20A. Another configuration of the bonding pads is shown in FIG. 2B , the bonding pads 22B of equal size are uniformly arranged at the center of the chip 20B. In this type of conventional bonding pad configuration, when the chip 20A or 20B is to be bonded by wire, the circuit design therein often has a certain directionality, and each bonding pad needs to be connected with the component substrate pins to be bonded in a specific way. Position engagement. However, the symmetrical wafer appearance formed by the bonding pads 22A and 22B of the same size and rectangle on the wafers 20A and 20B is difficult to determine the alignment position of the wafer and the bonding component substrate.

The same alignment problem also occurs with the circuits inside the chip. In the manufacture of IC chips, for the purpose of circuit design and fabrication or on-line inspection, inspection areas are usually set on specific internal circuits on the chip. Referring to FIG. 3, a conventional detection pad design in an on-chip circuit is illustrated. On the wafer 30, in the predetermined detection area 34, the internal circuit is designed with a detection metal pad (probe pad) 36. This type of very small metal pad 36 provides process personnel with a small detection probe to perform wafer inspection under a microscope. Electrical measurement of internal circuits.

For inspectors, since this kind of test metal pad is quite small, generally 5×5 μm, it is difficult to confirm the relationship between the connected lines after being enlarged by a microscope, causing troubles in electrical testing.

Contents of the invention

In order to solve the above-mentioned alignment problem of wafer dicing, an object of the present invention is to provide a semiconductor bonding pad region structure, which can be used as an alignment mark during wafer dicing.

Another object of the present invention is to provide a semiconductor bonding pad region structure, which can be used as an alignment mark during wafer bonding.

Another object of the present invention is to provide a test pad area suitable for semiconductor circuits, so as to identify the layout of the test lines connected thereto during circuit test.

A bonding pad region structure according to the present invention is disposed on a semiconductor wafer with a circuit, comprising: a bottom metal layer disposed on the surface of the semiconductor wafer and electrically connected to the circuit; an inter-metal dielectric layer covering the On the surface of the bottom metal layer, and the metal interlayer dielectric layer is embedded with a metal plug structure in contact with the bottom metal layer; a top metal layer is arranged on the surface of the metal layer inter-dielectric layer; and a protective layer is arranged on the top On the metal layer, there are a plurality of openings, exposing the portion of the top metal layer to be bonded as a bonding pad; wherein the bonding pad has a marking shape to define the relative position of the bonding pad on the semiconductor wafer .

In the above bonding pad region structure, the bonding pad can be in a "convex" shape, a "concave" shape, a "+" shape, or a """ shape, etc.

In the above bonding pad structure, the top and bottom metal layers may be Al-Cu alloy or Al-Si-Cu alloy. The inter-metal dielectric layer may be a silicon dioxide layer. The protective layer can be a silicon dioxide layer or a borophosphosilicate glass layer and a silicon nitride layer.

According to the present invention, there is further provided a detection pad used in a semiconductor circuit to measure electrical properties, having a marking shape to define the relative position of the detection pad in the semiconductor circuit.

Among the above detection pads, the detection pads can be in the shape of "convex", "concave", "+" or "" and so on. The detection pad can be made of aluminum-copper alloy or aluminum-silicon-copper alloy.

With the above structure of the bonding pad area, the positioning of the wafer during dicing, in addition to aligning with the alignment mark on the dicing line, can also be based on the directional shape of the bonding pad on the wafer as an alignment reference point. And when the chip is bonded by wire, the above-mentioned structure of the bonding pad area can be used as a basis for bonding positioning.

With the above-mentioned testing pad having a marked shape, it is also possible for testing personnel to easily determine the relative position of the circuit when measuring the electrical properties of the internal circuit.

Description of drawings

FIG. 1 is a schematic diagram of chip arrangement on a conventional wafer.

2A and 2B are schematic diagrams showing the design of bonding pads on a conventional chip.

FIG. 3 is a schematic diagram showing the design of detection pads in a conventional chip circuit.

FIG. 4 is a schematic diagram of the structure of the bonding pad region according to an embodiment of the present invention.

5A-5D are schematic diagrams showing the symbolic shapes of bonding pads according to an embodiment of the present invention.

FIG. 6 is a schematic diagram showing the structure of a detection pad according to an embodiment of the present invention.

Detailed ways

Referring to FIG. 4 , the bonding pad region structure according to an embodiment of the present invention is illustrated. First, a bottom metal layer 42 is covered on a substrate 40 with a semiconductor circuit (not shown), and is electrically connected to the semiconductor circuit in the substrate. The bottom metal layer 42 can be aluminum copper alloy or aluminum silicon copper alloy. The bottom metal layer 42 is covered with an inter-metal dielectric layer 44, which may be a silicon dioxide layer (SiO ₂ ). A metal plug structure 46 in contact with the bottom metal layer is embedded in the IMD layer 44 . A top metal layer 48 is disposed on the surface of the inter-metal dielectric layer 44 and is electrically connected to the bottom metal layer 42 through the plug 46 . The top metal layer 48 can be aluminum-copper alloy or aluminum-silicon-copper alloy, and its surface is covered with a protective layer 49 , such as borophosphosilicate glass (BPSG) and silicon nitride (SiN).

A plurality of openings are formed on the protective layer 49 to expose the top metal layer 48 as bonding pads 50 with an area of about 40×40 μm. The bonding pads 50 formed by the top metal layer 48 can be used for wire bonding of the chip 40 after it is diced from the wafer. The bonding pad 50 has a marking shape for defining the relative position of the bonding pad 50 on the semiconductor chip 40 .

Referring to FIG. 5A to FIG. 5D , schematic diagrams illustrating the symbolic shapes of bonding pads according to an embodiment of the present invention are illustrated. As shown in FIGS. 5A-5D , the bonding pads on the rectangular wafer 40 can be in the shape of a "convex" shape 50A, a "concave" shape 50B, a "+" shape 50C, or a rectangle """ 50D with a right angle notch. With the above-mentioned various bonding pads having certain directional shapes, the relative position between the bonding pads 50 of a special shape and the wafer 40 can be used as a positioning reference point for the rectangular wafer 40 during wafer dicing. In addition, after the rectangular chip 40 is cut from the wafer, it can be used as a positioning point for the chip 40 when performing wire bonding. Although the present invention includes marking-shaped bonding pads having the above-mentioned shapes, the present invention is not limited thereto.

Next, referring to FIG. 6 , it illustrates a schematic structural diagram of a detection pad (probe pad) in an embodiment of the present invention. On the rectangular wafer 40 , the uppermost layer has marked metal bonding pads 50 to define the relative position of the rectangular wafer 40 . On the measurement area 62 of the rectangular wafer 40, a plurality of detection pads are arranged in the circuit to be detected inside it, and these detection pads can be made of aluminum-copper alloy or aluminum-silicon-copper alloy, and its area range is about 5mm. ×5 μm. Wherein, the detection pads provided in the circuit of the chip 40 have a specific positioning shape, such as a "convex" shape detection pad 60A or a rectangular detection pad 60B with a groove, and so on.

With the detection pads of the above-mentioned specific shape, when inspectors observe the area 62 on the rectangular wafer 40 under a microscope, they can easily judge the relative relationship of the internal circuits by the shape or arrangement direction of the detection pads, which greatly improves the detection efficiency of the circuits. convenience. Although the present invention lists the shapes of the above-mentioned symbolic detection pads, the present invention is not limited thereto.

The metal pad with the making shape proposed by the present invention can be applied to the bonding pad on the chip surface or the probe pad in the internal circuit of the chip. The advantage of this kind of metal pad with a marked shape is that it can assist in identifying the marking array of the rectangular wafer, which greatly improves the recognition of the wafer orientation during wafer dicing or wafer bonding. Furthermore, when used as a detection pad for the internal circuits of the wafer, the relative relationship between the circuits can be quickly identified in the multi-layer densely distributed circuits, which greatly improves the recognition of the circuits by the inspectors.

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection is subject to what is defined in the claims.

Claims (14)

1. a junction pad area structure is arranged at one and has on the semiconductor wafer of circuit, it is characterized in that comprising:

One bottom metal layers is arranged at this semiconductor wafer surface, is electrically connect with this circuit;

One dielectric layer between metal layers is covered in the bottom metal laminar surface, and this dielectric layer between metal layers inside is embedded with the metal plug structure that contacts with this bottom metal layers;

One metal layer at top is arranged at this dielectric layer between metal layers surface; And

One sheath is arranged on this metal layer at top, has a plurality of openings, expose this metal layer at top desire for engaging portion with as joint sheet; Wherein at least one joint sheet has a sign property shape, to define the relative position of this joint sheet on this semiconductor wafer.

2. junction pad area structure according to claim 1 is characterized in that: this joint sheet is " protruding " shape.

3. junction pad area structure according to claim 1 is characterized in that: this joint sheet is " recessed " shape.

4. junction pad area structure according to claim 1 is characterized in that: this joint sheet is a cross "+".

5. junction pad area structure according to claim 1 is characterized in that: this joint sheet is the rectangle " " " with a right angle unfilled corner.

6. junction pad area structure according to claim 1 is characterized in that: this top and bottom metal layers are made of aluminium copper or Al-Si-Cu alloy.

7. junction pad area structure according to claim 1 is characterized in that: this dielectric layer between metal layers is a silicon dioxide layer.

8. junction pad area structure according to claim 1 is characterized in that: this sheath is silicon dioxide layer or boron-phosphorosilicate glass layer and silicon nitride layer.

9. a detecting pad is used for the semiconductor circuit to measure electrically, it is characterized in that: have a sign property shape, to define the relative position of this detecting pad in this semiconductor circuit.

10. detecting pad according to claim 9 is characterized in that: this detecting pad is " protruding " shape.

11. detecting pad according to claim 9 is characterized in that: this detecting pad is " recessed " shape.

12. detecting pad according to claim 9 is characterized in that: this detecting pad is a cross "+".

13. detecting pad according to claim 9 is characterized in that: this detecting pad is the rectangle " " " with a right angle unfilled corner.

14. detecting pad according to claim 9 is characterized in that: this detecting pad is made of aluminium copper or Al-Si-Cu alloy.

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