CN1251183A - Integrated circuit and method for testing the same - Google Patents

Abstract

An integrated circuit having a CPU and a user ROM, characterized in that the address space of the test ROM is located within the address space of the user ROM, the integrated circuit also having an external RAM for the CPU and a switching device, the switching device enabling access to only one of the user ROM or the test ROM, and it can be set to an irreversible state, in which case only access to the user ROM is allowed.

Description

Integrated circuit and method for testing the integrated circuit

The earliest chip cards, such as telephone cards or ward cards, can basically only achieve storage functions. Later, simpler logic functions were added, such as digital comparison or pseudo-random number generation. With the increasing use of chip cards in important security areas, such as in the banking industry, it is necessary to partially store a large number of values, sometimes even confidential data, for which it is necessary to use a microprocessor, and the processing can realize Complex security, coding and/or authentication operations. At the same time, more and more encryption methods are required, which increases the computational cost.

The semiconductor chips in today's chip cards contain expensive and complex circuits. According to regulations, these circuits are composed of a CPU, a ROM, an EEPROM (or EPROM) and some modules, as well as a bus connecting the above-mentioned devices. The module referred to is a UART, or a coprocessor. The CPU is allocated at most one RAM, which is usually static RAM in implementation. Because static RAM consumes a lot of space, they are usually made very small, and the storage capacity is less than 1KB. In addition, chip card products have another feature, that is, they only have one or two serial interfaces with the outside world, so the speed of data transmission is very slow. Since the internal parallel works as 8 bits, a serial/parallel conversion has to be done, which is implemented in the CPU by the accumulator under software control, so this conversion process also runs very slowly. Usually, data transmission is defined according to an ISO standard, and only a few thousand bytes per second, so this is not a problem for regular operations, and users can also use this operation according to regulations, making it a frequent A money bag that adds money at a time.

However, the aforementioned complex integrated circuits must be of sufficient quality when submitted to customers, so extensive testing is essential.

This product testing work is realized by a self-testing software. For this reason, chip card products all contain a test memory, which is implemented as a ROM. The memory comes with self-test software, which is used to test the power-on-reset components on the chip. The self-test software is composed of various test programs, and the test programs are called through test vectors. Such test vectors can be input via the IO port. Since the size of the test memory is limited, and the internal size of each product is inconsistent, according to regulations, not all test programs are included in the test memory. Therefore, the remaining test programs are loaded in EEPROM and called from there. To this end, many programming and erasing procedures were added, and these original testing procedures lasted longer.

There are many ROMs on the semiconductor chip. As a part of the ROM test memory, it also contains user programs, such as operating systems, and often has subroutines for use, such as EEPROM writing and deleting programs. Testing the memory range requires occupying a portion of the entire ROM address space so that this address range can be entered in the event of an error or intentional and misuse, etc., according to defined measures, to access this portion of the ROM address range during the implementation of the interrupt test.

The implementation methods hitherto have some disadvantages, on the one hand they are slow, so that the test time is too long and expensive, and on the other hand, in order to be able to access the test programs during the test, these test programs must be fairly securely connected In a ROM or if possible, store it in the on-chip EEPROM to make it non-volatile.

It is therefore the object of the present invention to provide a circuit arrangement which can be tested very quickly and which is highly resistant to misuse.

This task is realized by an integrated circuit, which at least includes a CPU, a user ROM, a test ROM and a CPU internal RAM. Here, the address space of the test ROM is located within the address space of the user ROM, and the method of the invention provides a switching device so that either the user ROM or the test ROM is accessed. In a preferred further development of the invention, its switching means can be shifted into an irreversible state allowing only access to the user ROM. In this way, the test ROM can be closed after the test phase and no longer occupies the previous address space. Therefore, there is no space in the existing available address range, and the closed memory range can be placed in the above-mentioned available address, so that there is no interference.

In a development of the invention, the test ROM has only a test start program which is necessary to start the test work. In this regard, the own test program is written in an additional RAM called X-RAM outside the CPU, and the program is executed from then on during work.

The method of the invention is given in claim 7 . There is an advantage that the test program is only stored in the X-RAM. Since the X-RAM is volatile, the test program can be deleted as long as the power supply voltage is cut off after the test is completed.

Due to the limited number of connection points between the chip card and the outside world, usually only one serial input/output port is used. The serial/parallel or parallel/serial conversion is taken over by the CPU controlled accumulator. It requires software control and is slow. For this purpose, a development of the invention includes an activatable and deactivatable register, which are connected to the input/output ports and to an internal bus. So test programs can be written to X-RAM very quickly.

In another embodiment of the present invention, the register can be used to transmit the signal generated by the test to an external test instrument for monitoring. In this way, the testing work is both safe and fast. The signals are preferably encoded before transmission, and they can be fed back linearly or non-linearly through registers, eg, an XOR gate can be used for feedback. However, other gate functions may also be used.

The invention is explained below with reference to typical embodiments of the drawings. in:

Accompanying drawing 1 is the block circuit diagram of integrated circuit of the present invention,

Figure 2 is a detailed circuit diagram of a preferred embodiment of the present invention.

Figure 1 shows a CPU with its RAM, an additional X-RAM and a non-failable EEPROM interconnected by a bus. The serial input/output port I/O is connected with the accumulator (not shown) in the CPU through the bus, and the accumulator is also used for serial/parallel conversion. A ROM containing a large amount of user software and a test ROM are connected to the bus through a switching device MUX, and the switching tool MUX can be a variety of converters. Typically, the switching device MUX is controlled by the CPU through the input/output port I/O, indicated by an arrow St in the figure.

According to the method of the present invention, only one of the ROM and the test ROM is connected to the bus through the switching device MUX and addressed. The addressing of the ROM is at least partially equal to the addressing of the test ROM. Therefore, this part of the address cannot determine whether it is the addressing of the ROM or the addressing of the test ROM.

When the bus is connected to the ROM through the switching device MUX, it is irreversible, so during the test, the test ROM is completely isolated from the bus.

Preferably, the test ROM only stores a test start program for starting the test. After power-on reset, this program is invoked, and then the test program in the external X-RAM can be loaded and executed here. An advantage of writing the test program in X-RAM is that the running process is faster and only short-term. Therefore, when the power supply voltage is cut off, the test program in X-RAM can be quickly deleted. After the test is over, the switching device MUX enters an irreversible state, and the test ROM cannot be accessed through the bus.

Figure 2 shows in more detail another preferred integrated circuit of the present invention. As mentioned above, the CPU can program the SFR (Special Function Register) address to the input/output port I/O through the bus through the address decoder, and one side of it is connected to the bus in parallel. When the input/output port I/O is controlled through the SFR address, the input and output data will flow into or out of the CPU through the bus. Inside the CPU, through programming control, the serial/parallel or parallel/serial conversion of the accumulator generates input or output data.

According to the method of the invention, a shift register SR is connected in parallel in the transmission circuit, so that the serial/parallel or parallel/serial conversion becomes faster during the test. Similarly, the CPU responds and reads the shift register SR through the SFR address. For this purpose, the shift register SR correspondingly requires an address decoder SFR. The CPU can also activate and deactivate the shift register through these SFR addresses.

The counter Z counts the pulse Cl, and sends a signal to the CPU after each word to control the writing work of the X-RAM, and also uses the counter Z to write the information into the shift register SR, so that we can know what Write the word to be converted to the shift register SR.

Usually, since the CPU in the integrated circuit works in 8-bit parallel mode, an 8-bit long shift register can meet the requirements in principle. In order to synchronize the data flow, a start bit must be set aside. After every 8 pulses counted by the counter Z, reading in produces a serial/parallel conversion, thus sending the contents of the shift register SR to the bus in parallel.

Of course, it is also possible to send a start bit before reading each byte, so that the personal microcomputer as a tester is simplified. But this requires a 9-bit long shift register. In addition, the data transfer rate will also be reduced.

In principle, the present invention is applicable to various CPU working word widths, specifically, it is also applicable to 16-bit and 32-bit central processing machines. And the shift register only needs a corresponding length.

The running process of the test work is generally as follows: First, the tester sends out a logic "0" signal, indicating that the data transmission starts. At this time, the counter Z is turned on, and it shows that a byte is received every 8 pulses. CPU can learn above-mentioned situation by a dedicated signal, but also can adjust this time with a software, like this is more accurate, and effect is better. During the wait period, the CPU waits for the transfer to start, while the address counter of the X-RAM has been adjusted to the start state before. Immediately after the transmission is completed, the test program is called, and then the CPU jumps into the receiving waiting period again.

During the two transfer intervals, the counter Z can continue to run. Like this, in the 8 pulse time after the system pulse C1, through any functional device, the internal signal can be connected with the contents in the shift register (collection stage), and then the signal is sent out in the next 8 pulses ( output stage), typically, the above functional devices may employ an XOR. This connection is indicated by a double arrow pointing from the shift register SR to the XOR gate. In fact, the output signal of the shift register SR is fed back to its input loop through XOR. XOR can be turned on or off by CPU control through coding. This is indicated here by an arrow Pf. During each collection phase, the process is interrupted by a start bit to receive an updated data stream. Internal signals are connected to the shift register during the collection phase for two reasons. First, it can be verified whether the 8 values generated by the connection in the collection phase are correct. Second, since no source signal is transmitted to the outside world, it is impossible for this information to be misused as a source of potential interference.

This improvement of the present invention improves the protection function of the test, as long as the fault is identified by observing the internal signal, the chip with the fault can be found earlier.

Claims (8)

1. Integrated circuit with a CPU, a user ROM and a bus connecting them, characterized in that The test ROM is also connected to the bus, its address space is located within the address space of the user ROM, the CPU external RAM (XRAM) is connected to the bus, and the switching device (MUX) makes access only to one of the user ROM or the test ROM. 2. An integrated circuit, with a CPU, a user ROM, and a bus connecting them, which can be accessed only through at least one serial input/output port (I/O), and controlled by CPU programming, by internal Serial/parallel conversion produces input data, or parallel/serial conversion produces output data, characterized in that, The test ROM is also connected to the bus, and its address space is located within the address space of the user ROM. There is a CPU external RAM (XRAM) and a switching device (MUX). The switching device makes access only to one of the user ROM or the test ROM. 3. An integrated circuit according to claim 1 or 2, characterized in that, The switching device (MUX) can be moved to an irreversible state allowing only access to user ROM. 4. An integrated circuit according to claim 2 or 3, characterized in that, The serial input/output port (I/O) is also connected to the internal bus through an activatable and deactivatable shift register (SR) to generate serial/parallel conversion. 5. Integrated circuit according to claim 4, characterized in that the deactivation of the shift register (SR) is effected irreversibly. 6. Integrated circuit according to claim 4, characterized in that the shift register (SR) is fed back by logic gates (XOR). 7. The method for testing integrated circuits, the method contains a CPU, a test ROM and a CPU external RAM, the steps are as follows: - after power-on-reset, enabling the test boot program activation in the test ROM, - Loading of the test program into RAM is controlled by the test launcher, and the program is executed from there by the CPU, - After the test is over, delete the test program in the RAM, and realize the interrupt execution of the test startup program in the test ROM, and the interrupt is in an irreversible state. 8. The method as claimed in claim 7, characterized in that the test program is written into the RAM via a serial input/output port (I/O) and a switchable serial/parallel converter.

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