CN111475426A - Method for managing flash memory module and related flash memory controller and electronic device - Google Patents

Abstract

The invention discloses a flash memory controller, wherein the flash memory controller is used to access a flash memory module and includes a read-only memory, a microprocessor and a timer. The read-only memory is used to store program code, the microprocessor is used to execute the program code to control access to the flash memory module, and the timer is used to generate time information. In the operation of the flash memory controller, the microprocessor performs a redundant read operation on at least a part of the plurality of blocks according to the time information generated by the timer, wherein The redundant read operation is not triggered by a read command from the master device. The flash memory controller of the present invention actively detects the read status of blocks and actively performs redundant read operations on blocks that have not been read within a period of time, which can effectively prevent the data in the block from being read for a long time. Deterioration occurs due to reading, in order to improve storage quality and reading efficiency.

Description

Method for managing flash memory module and related flash memory controller and electronic device

technical field

The present invention relates to improvements in flash memory controllers.

Background technique

With the evolution of flash memory technology, the memory cells in a flash memory chip are changed from a planar arrangement to a multi-layer stack mode, so that a single chip can include more memory cells to increase the capacity of the flash memory chip. However, the above-mentioned 3D flash memory will encounter some problems in reading quality. For example, if the data in a block is not read for a long time, the quality of the data in the block will deteriorate rapidly. As a result, it is difficult to decode the data of the subsequent blocks, or even cannot be read correctly. Therefore, how to propose an efficient management method to avoid the problem of data preservation is an important technical direction.

SUMMARY OF THE INVENTION

Therefore, one of the objectives of the present invention is to provide a method for managing flash memory, which can effectively avoid the deterioration of the data in the above-mentioned blocks due to long time not being read, so as to solve the problems in the prior art.

In one embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller includes a read-only memory, a microprocessor and a timer device. The read-only memory is used to store a program code, the microprocessor is used to execute the program code to control access to the flash memory module, and the timer is used to generate time information. In the operation of the flash memory controller, the microprocessor performs a redundant read operation on at least a part of the plurality of blocks according to the time information generated by the timer, Wherein the redundant read operation is not triggered by a read command of a master device.

In another embodiment of the present invention, a method for managing a flash memory module is disclosed, wherein the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, and each block includes a plurality of flash memory chips. a data page, and the method includes: using a timer to generate a time information; and according to the time information generated by the timer, performing processing on at least a part of the plurality of blocks. A redundant read operation, wherein the redundant read operation is not triggered by a read command from a master device.

In another embodiment of the present invention, an electronic device is disclosed, which includes a flash memory module and a flash memory controller, wherein the flash memory module includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks , each block includes multiple data pages. In the operation of the flash memory controller, the flash memory controller performs a redundant read operation on at least a part of the plurality of blocks according to time information generated by a timer, wherein the redundant read operation is performed. The remaining read operations are not triggered by a read command from a master device.

Description of drawings

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a block in a flash memory according to an embodiment of the present invention.

3 is a schematic diagram illustrating a plurality of write voltage levels and a plurality of threshold voltages in each memory cell of the three-layer memory block.

FIG. 4 is a schematic diagram of a block record table according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a block read time record table according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of a block read time record table according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of an update block read time record table according to an embodiment of the present invention.

FIG. 8 is a flowchart of a method for managing a flash memory module according to an embodiment of the present invention.

Among them, the reference numerals are described as follows:

100 Memory Devices

110 Flash Controller

112 Microprocessor

112C program code

112M read only memory

114 Control logic

116 Buffer memory

118 Interface logic

119 Timer

120 flash module

130 Main unit

132 encoder

134 decoder

N1～NK pins

200. Block B1～BN

202 floating gate transistor

BL1, BL2, BL3 bit lines

WL0～WL2, WL4～WL6 word lines

L1～L8 voltage level

Vt1～Vt7 threshold voltage

400 block record table

500, 600 block read time record table

800～804 steps

Detailed ways

With the evolution of flash memory technology, the memory cells in a flash memory chip are changed from a planar arrangement to a multi-layer stack mode, so that a single chip can include more memory cells to increase the capacity of the flash memory chip. However, the above-mentioned 3D flash memory will encounter some problems in reading quality. For example, if the data in a block is not read for a long time, the quality of the data in the block will deteriorate rapidly. As a result, it is difficult to decode the data of the subsequent blocks, or even cannot be read correctly. Therefore, how to propose an efficient management method to avoid the problem of data preservation is an important technical direction.

[Content of the invention]

Therefore, one of the objectives of the present invention is to provide a method for managing flash memory, which can effectively avoid the deterioration of the data in the above-mentioned blocks due to long time not being read, so as to solve the problems in the prior art.

In one embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller includes a read-only memory, a microprocessor and a timer device. The read-only memory is used to store a program code, the microprocessor is used to execute the program code to control access to the flash memory module, and the timer is used to generate time information. In the operation of the flash memory controller, the microprocessor performs a redundant read operation on at least a part of the plurality of blocks according to the time information generated by the timer, Wherein the redundant read operation is not triggered by a read command of a master device.

In another embodiment of the present invention, a method for managing a flash memory module is disclosed, wherein the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, and each block includes a plurality of flash memory chips. a data page, and the method includes: using a timer to generate a time information; and according to the time information generated by the timer, performing processing on at least a part of the plurality of blocks. A redundant read operation, wherein the redundant read operation is not triggered by a read command from a master device.

In another embodiment of the present invention, an electronic device is disclosed, which includes a flash memory module and a flash memory controller, wherein the flash memory module includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks , each block includes multiple data pages. In the operation of the flash memory controller, the flash memory controller performs a redundant read operation on at least a part of the plurality of blocks according to time information generated by a timer, wherein the redundant read operation is performed. The remaining read operations are not triggered by a read command from a master device.

[Simple description of the diagram]

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a block in a flash memory according to an embodiment of the present invention.

3 is a schematic diagram illustrating a plurality of write voltage levels and a plurality of threshold voltages in each memory cell of the three-layer memory block.

FIG. 4 is a schematic diagram of a block record table according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a block read time record table according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of a block read time record table according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of an update block read time record table according to an embodiment of the present invention.

FIG. 8 is a flowchart of a method for managing a flash memory module according to an embodiment of the present invention.

[implementation]

FIG. 1 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110 , and the flash memory controller 110 is used for accessing the flash memory module 120 . According to the present embodiment, the flash memory controller 110 includes a microprocessor 112 , a read only memory (ROM) 112M, a control logic 114 , a buffer memory 116 , an interface logic 118 and a timer 119 . The ROM 112M is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control access to the flash memory module 120 . The control logic 114 includes an encoder 132 and a decoder 134, wherein the encoder 132 is used to encode the data written into the flash memory module 120 to generate a corresponding check code (or error correction code). Code), ECC), and the decoder 134 is used to decode the data read out from the flash memory module 120.

In addition, both the flash memory controller 110 and the flash memory module 120 include a plurality of interconnected pins N1 ˜ NK for transmitting data and commands between each other. Since the functions of pins N1 to NK can refer to the relevant specifications of the flash memory, the details will not be described here.

In a typical situation, the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks, and the flash memory controller 110 performs an operation of erasing data on the flash memory module 120 in units of blocks. conduct. In addition, a block can record a specific number of data pages, wherein the operation of the flash memory controller 110 to write data to the flash memory module 120 is performed in units of data pages. In this embodiment, the flash memory module 120 is a 3D NAND-type flash (3D NAND-type flash) module.

In practice, the flash memory controller 110 that executes the program code 112C through the microprocessor 112 can use its own internal components to perform various control operations, for example, use the control logic 114 to control the access operation of the flash memory module 120 (especially for at least one block or at least one data page access operation), using the buffer memory 116 to perform required buffering, and using the interface logic 118 to communicate with a host device (Host Device) 130 . The buffer memory 116 is implemented as a random access memory (Random Access Memory, RAM). For example, the buffer memory 116 may be a static random access memory (Static RAM, SRAM), but the present invention is not limited thereto.

In one embodiment, the memory device 100 may be a portable memory device (eg, a memory card conforming to SD/MMC, CF, MS, XD standards), and the host device 130 is an electronic device that can be connected to the memory device, Such as mobile phones, laptops, desktop computers...etc. In another embodiment, the memory device 100 may be a solid state drive or an embedded storage device conforming to the Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications, so as to set In an electronic device, such as a mobile phone, a notebook computer, or a desktop computer, the main device 130 may be a processor of the electronic device.

2 is a schematic diagram of a block 200 in the flash memory module 120 according to an embodiment of the present invention, wherein the flash memory module 120 is a three-dimensional NAND flash memory. As shown in FIG. 2, the block 200 includes a plurality of memory cells (such as the floating gate transistor 202 shown in the figure or other charge trap components), which pass through a plurality of bit lines (only BL1 is shown in the figure). ~BL3) and a plurality of word lines (such as WL0~WL2, WL4~WL6 in the figure) to form a three-dimensional NAND flash memory structure. In FIG. 2, taking the uppermost plane as an example, all floating gate transistors on word line WL0 constitute at least one data page, all floating gate transistors on word line WL1 constitute another at least one data page, and word line All the floating gate transistors of WL2 constitute at least one more data page...and so on. In addition, the definition between the word line WL0 and the data page (logical data page) will be different according to the different flash memory writing methods. When writing in the multi-level memory (MLC) method, all floating gate transistors on the word line WL0 correspond to only a single logical data page; when writing in the Multi-Level Cell (MLC) method, all floating gate transistors on the word line WL0 Corresponding to two logical data pages; when using triple-level storage (Triple-Level Cell, TLC) to write, all floating gate transistors on word line WL0 correspond to three logical data pages; and when using four layers When writing in a Quad-Level Cell (QLC) manner, all floating gate transistors on the word line WL0 correspond to four logical data pages. Since those skilled in the art should be able to understand the structure of the 3D NAND flash memory and the relationship between word lines and data pages, the relevant details are not repeated here.

During the operation of the memory device 100, since a block in the flash memory module 120 is in the state of data writing, if the block has not been read for a long time, the data quality of the block will be greatly improved drop, thereby causing decoding difficulties for the decoder 134. Therefore, in this embodiment, the microprocessor 112 performs a dummy read operation on at least a part of the blocks in the flash memory module 120 storing data according to the time information generated by the timer 119 , In order to avoid the deterioration of the data in the block because it has not been read for a long time. Specifically, the above redundant read operation refers to that the microprocessor 112 does not actually obtain the content of the block from the flash memory module 120 , and the redundant read operation is not performed by the host device 130 . (that is, the microprocessor 112 does not perform a redundant read operation on the block because of the request of the host device 130).

In this embodiment, when the microprocessor 112 performs a redundant read operation on the block, the microprocessor 112 sends a read request to the flash memory module 120, but at this time, the microprocessor 112 closes the flash memory control A read enable pin of the device 110 (eg, pin N2 shown in FIG. 1 ), that is, the flash controller 110 cannot obtain the required read data from the flash memory module 120 . After receiving the read request from the flash memory controller 110, the flash memory module 120 reads one or more data pages of the block, and only temporarily stores the read content in its own temporary into the memory area without transferring the read data to the flash memory controller 110 . As described above, by performing redundant read operations on the block, the data quality in the block can be prevented from being degraded due to no reading for a long time.

In one embodiment, since the purpose of the redundant read operation is only to prevent the data quality in the block from being degraded due to no reading for a long time, the flash controller 110 may only request to read the data of the block. One data page is sufficient to speed up redundant read operations.

In another embodiment, the microprocessor 112 can control/instruct the flash memory module 120 to use a single-level cell (SLC) read mode to perform the redundant read operation on the block, Regardless of whether the block is a single-level storage block, a multi-level cell (MLC) block, a triple-level cell (TLC) block, or a four-level storage ( Any of the Quad-Level Cell, QLC) blocks. As an illustration, the block is a three-layer memory block, please refer to the plurality of write voltage levels L1-L8 and the plurality of thresholds of each memory cell in the three-layer memory block shown in FIG. 3 . A schematic diagram of the voltages (or read voltages) Vt1 to Vt7. As shown in FIG. 3, each floating gate transistor 202 may be programmed (to have a voltage level L1 (ie (MSB, CSB, LSB)=(1, 1, 1)), a voltage level L2 (ie (MSB, CSB, LSB) = (1, 1, 0), voltage level L3 (ie (MSB, CSB, LSB) = (1, 0, 0)), voltage level L4 (ie (MSB, CSB, LSB)=(0,0,0)), voltage level L5 (ie (MSB,CSB,LSB)=(0,1,0)), voltage level L6 (ie (MSB,CSB,LSB)=( 0,1,1)), voltage level L7 (ie (MSB,CSB,LSB)=(0,0,1)) or voltage level L8 (ie (MSB,CSB,LSB)=(1,0) , 1)). When the flash memory controller 110 needs to read the least significant bit (LSB) of the floating gate transistor 202, the flash memory controller 110 uses the threshold voltages Vt1 and Vt5 to read the floating gate transistor 202, and according to the floating gate transistor 202 The conduction state of transistor 202 (whether current is generated) generates a "1" or "0". Similarly, when the flash memory controller 110 needs to read the middle valid bit (CSB) in the floating gate transistor 202, the flash memory control The device 110 will use the threshold voltages Vt2, Vt4 and Vt6 to read the floating gate transistor 202, and generate "1" or "0" according to the conduction state of the floating gate transistor 202 (whether current is generated) for the decoder 134 for decoding. Similarly, when the flash memory controller 110 needs to read the most significant bit (MSB) in the floating gate transistor 202, the flash memory controller 110 uses the threshold voltages Vt3 and Vt7 to read the floating gate transistor 202, and according to The conduction state of the floating gate transistor 202 (whether current is generated) determines whether the most significant bit is "1" or "0" for the decoder 134 to decode.

As shown in FIG. 3 , when reading a three-layer storage block, a plurality of threshold voltages Vt1 to Vt7 are generally required to read data content. block) for redundant read operations, only a single threshold voltage is used to read each memory cell. For example, the flash memory module 120 only uses the threshold voltage Vt4 to read each memory cell, while the rest of the threshold voltages are used to read each memory cell. The voltages Vt1-Vt3 and Vt5-Vt7 are not used in the redundant read operation.

The timing of the redundant read operation and various embodiments of how the microprocessor 112 selects the blocks that need to perform the redundant read operation are described below.

In the first embodiment, the microprocessor 112 can create a block record table to record which blocks in the flash memory module 120 have stored data. Referring to the schematic diagram of the block record table 400 shown in FIG. 4 , assuming that the flash memory module 120 includes a plurality of blocks B1 -BN, the microprocessor 112 can update the blocks during the process of writing data to the flash memory module 120 The content of the block record table 400, that is, when data is written to a block in the flash memory module 120, the block number is written into the block record table 400 (for example, B1, B2, B12, B13 shown in the figure) , B14), and when a block in the flash memory module 120 is erased or marked as invalid, the corresponding block serial number is removed from the block record table 400 . Therefore, the microprocessor 112 can periodically, for example, every 30 minutes, perform redundant read operations on the blocks recorded in the block record table 400 according to the time information generated by the timer 119 to maintain these The data quality of the block where the data is stored.

In this embodiment, the block record table 400 can be temporarily stored in the buffer memory 116 or an external dynamic random access memory, and the block record table 400 can be written to the memory device 100 when the memory device 100 is shut down or needs to release memory space. in the flash memory module 120 .

In the second embodiment, the microprocessor 112 may establish a block reading time record table to record the blocks that have been read in the flash memory module 120 and the corresponding time information. Referring to the schematic diagram of the block read time record table 500 shown in FIG. 5 , assuming that the flash memory module 120 includes a plurality of blocks B1 -BN, the microprocessor 112 can read each block in the flash memory module 120 The time information of the block (eg, the time stamp obtained by the host device 130 or the timer 119 ) is recorded. In one embodiment, the content of the block read time record table 500 is continuously updated, that is, the block read time record table 500 records the time point when each block was last read. Therefore, the microprocessor 112 can select the unread data according to the content of the block read time record table 500 periodically, for example, every 30 minutes, when it is idle, or according to the time information generated by the timer 119. Take longer blocks for redundant read operations. For example, assuming that the block read time record table 500 records that blocks B_4 and B_5 are more than 20 minutes away from the last read time point, the microprocessor 112 can prioritize the block B_4 and block B_5 B_5 performs redundant read operations.

In this embodiment, the block read time record table 500 can be temporarily stored in the buffer memory 116 or an external dynamic random access memory, and the block read time is recorded when the memory device 100 is powered off or needs to release memory space. The log table 500 is written into the flash memory module 120 .

In the third embodiment, the microprocessor 112 can create a block reading time record table to record the block serial number and corresponding time information in real time when a block is read, and the block is read The time log table can be further updated/organized for subsequent redundant read operations. Referring to the schematic diagram of the block reading time record table 600 shown in FIG. 6 , it is assumed that the microprocessor 112 sequentially reads blocks B_123, B_75, B_67, B_123, B_4, B_5, B_67, B_123 from 14:01 , the microprocessor 112 will simultaneously record the read blocks and the corresponding time information (for example, the time stamp shown in the figure) in sequence in the block read time record table 600 , wherein the read blocks of the above blocks are read in sequence. The fetch operation is performed according to the read request of the master device 130 . Next, the microprocessor 112 may periodically, eg, every 5 minutes, sort out the block read time record table 600 according to the time information generated by the timer 119 to delete duplicate block numbers. For example, referring to FIG. 7 , since block B_123 has three read records, the microprocessor 112 can directly delete the first two read records; and block B_67 has two read records, the microprocessor 112 can directly delete the first two read records. 112 can directly delete the previous read record to generate a sorted block read time record table 600 .

Then, the microprocessor 112 may periodically, for example, every 10 minutes, generate a not to do list according to the block read time record table 600 according to the time information generated by the timer 119, to list blocks with shorter read times that do not require redundant read operations. For example, assuming that the current time point is 14:40, and the microprocessor 112 sets that blocks that have been read within 15 minutes do not need to perform redundant read operations, then the do not list can be Blocks B5, B67, B123 are included. Next, if the microprocessor 112 needs to operate, the microprocessor 112 can use the block record table 400 shown in FIG. 4 and the do not make list to record the blocks in the flash memory module 120 that have data storage, but do not include The blocks B5, B67, and B123 included in the do not list can be used for redundant read operations.

Finally, after the redundant read operation is completed, the microprocessor 112 directly removes the block for which the redundant read operation is performed from the block read time record table 600. For the embodiment of FIG. 7, the block The read time record table 600 can directly delete the records of the blocks B_75 and B4, that is, it is not necessary to record the block serial numbers and corresponding time information for redundant read operations.

It should be noted that the above-mentioned time points of the redundant read operation and the three embodiments of how the microprocessor 112 selects the blocks that need to perform the redundant read operation are only for illustrative purposes, as long as the microprocessor 112 can establish the correlation. The table is used to determine which blocks need to perform redundant read operations. The content of the table can be expressed in different ways according to the design of the engineer, and the changes in the relevant design should belong to the scope of the present invention.

FIG. 8 is a flowchart of a method for managing a flash memory module according to an embodiment of the present invention. With reference to the content described in the above embodiments, the flow is as follows.

Step 800: The process starts.

Step 802: Use a timer to generate time information.

Step 804: Perform a redundant read operation on at least a part of the blocks according to the time information generated by the timer, wherein the redundant read operation is not performed by a master Triggered by a read command from the device.

To briefly summarize the present invention, in the flash memory controller of the present invention, by actively detecting the read state of the block, and actively performing redundant read operations on the blocks that have not been read for a period of time, it can effectively avoid The data in the block is degraded because it is not read for a long time, so as to improve the storage quality and the reading efficiency.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (20)

1. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, and each block includes A plurality of data pages, and the characteristics of the flash memory controller include: a read-only memory for storing a program code; a microprocessor for executing the program code to control access to the flash memory module; and a timer for generating time information; The microprocessor performs a redundant read operation on at least a part of the plurality of blocks according to the time information generated by the timer, wherein the redundant read operation is not Triggered by a read command from a master device. 2. The flash memory controller of claim 1, wherein when the microprocessor performs the redundant read operation on the at least a part of the blocks, the flash memory controller does not automatically The flash memory module receives the data read by the flash memory module on the at least a part of the block. 3. The flash memory controller of claim 2, wherein the flash memory controller comprises a read enable pin connected to the flash memory module, and when the microprocessor responds to the at least one read enable pin During the redundant read operation for a part of the blocks, the read enable pin is turned off so that the flash controller does not receive the flash memory module from the flash memory module for the at least part of the The data read by the block. 4. The flash memory controller of claim 1, wherein when the microprocessor performs the redundant read operation on the at least a part of the blocks, the microprocessor can only read One data page of each block in the at least a portion of the blocks is fetched. 5. The flash memory controller of claim 1, wherein the microprocessor uses a single-level memory read mode to perform the redundant read operation on the at least a portion of the blocks. 6 . The flash memory controller of claim 5 , wherein the at least a part of the blocks comprises at least one of a two-layer storage block, a three-layer storage block, and a four-layer storage block. 7 . one. 7. The flash memory controller of claim 5, wherein the microprocessor uses only a single read voltage to read the at least a portion of the block for the redundant read operation. 8. The flash memory controller of claim 1, wherein the flash memory controller comprises a buffer memory, the buffer memory stores a block record table to record which of the plurality of blocks are A block has stored data; and the microprocessor refers to the block record table to select a block with stored data as the at least a part of the block. 9 . The flash memory controller of claim 8 , wherein the microprocessor periodically performs the redundancy on the at least a portion of the blocks according to the time information generated by the timer. 10 . remaining read operations. 10. The flash memory controller of claim 1, wherein the flash memory controller comprises a buffer memory, the buffer memory stores a block read time record table to record the plurality of blocks There are read blocks and corresponding time information; and the microprocessor refers to the block read time record table to select the at least a part of the blocks from the plurality of blocks . 11 . The flash memory controller of claim 10 , wherein the block read time record table records the blocks that have been read in the plurality of blocks and the latest time of each block. 12 . The point in time when it was read. 12 . The flash memory controller of claim 10 , wherein the block read time record table records the blocks in the plurality of blocks that have been read by a master device and each block. 13 . The point in time when the block was last read. 13. A method of managing a flash memory module, wherein the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, and each block includes a plurality of data pages, and the method features Yes, including: using a timer to generate a time message; and According to the time information generated by the timer, a redundant read operation is performed on at least a part of the plurality of blocks, wherein the redundant read operation is not performed by a read operation of a master device Triggered by a fetch command. 14. The method of claim 13, further comprising: During the redundant read operation on the at least a portion of the blocks, the data read by the flash memory module on the at least a portion of the blocks is not received from the flash memory module. 15. The method of claim 13, wherein the step of performing the redundant read operation on the at least a portion of the blocks comprises: The redundant read operation is performed on the at least a portion of the blocks using a single-level memory read mode. 16. The method of claim 15, wherein the at least a portion of the blocks comprises at least one of a two-layer storage block, a three-layer storage block, and a four-layer storage block. 17. An electronic device, characterized in that it comprises: a flash memory module, wherein the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, and each block includes a plurality of data pages; and a flash memory controller for accessing the flash memory module; The flash controller performs a redundant read operation on at least a part of the plurality of blocks according to time information generated by a timer, wherein the redundant read operation is not performed by a master device triggered by the read command. 18. The electronic device of claim 17, wherein when the flash memory controller performs the redundant read operation on the at least a part of the blocks, the flash memory controller does not The flash memory module receives the data read by the flash memory module on the at least a part of the block. 19. The electronic device of claim 18, wherein the flash memory controller comprises a read enable pin connected to the flash memory module, and when the flash memory controller controls the at least part of the During the redundant read operation of the block, the read enable pin is turned off so that the flash memory controller does not receive the flash memory module from the flash memory module for the at least a portion of the block. The data read by the block. 20. The electronic device of claim 17, wherein when the flash memory controller performs the redundant read operation on the at least a part of the blocks, the flash memory controller can only read One data page of each of the at least a portion of the blocks.

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