TWI852008B - Flash memory controller and electronic device - Google Patents

Abstract

The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, and the flash memory controller includes a ROM, a microprocessor and a time management circuit. The ROM stores a program code, the microprocessor is configured to execute the program code to control the access of the flash memory module, and the time management circuit is configured to generate current time information. In the operations of the flash memory controller, when the microprocessor writes data into last pages of a specific block of the flash memory module, the microprocessor writes the time information generated by the time management circuit into one of the last pages of the specific block.

Description

Flash memory controller and electronic device

The present invention relates to a flash memory controller.

With the evolution of flash memory technology, the memory cells in flash memory chips have changed from a planar arrangement to a multi-layer stacking mode, so that a single chip can contain more memory cells to increase the capacity of the flash memory chip. However, the above-mentioned 3D flash memory will encounter data retention problems, that is, soon after the data is written to the flash memory chip, its data quality will drop significantly, and the data may not be read correctly. Therefore, how to propose an efficient management method to avoid data retention problems is an important technical direction.

Therefore, the present invention proposes a method for managing flash memory, which can efficiently and quickly find the block where data storage problems are about to occur and perform appropriate processing to solve the problems in the prior art.

In one embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of data pages, and the flash memory controller includes a read-only memory, a microprocessor and a time management circuit. The read-only memory is used to store a program code, the microprocessor is used to execute the program code to control access to the flash memory module, and the time management circuit is used to generate current time information. In the operation of the flash memory controller, when the microprocessor writes data to the last multiple data pages of a specific block, the microprocessor writes the time information generated by the time management circuit to one of the last multiple data pages.

In another embodiment of the present invention, a method for managing a flash memory module is disclosed, wherein the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of data pages, and the method includes the following steps: generating current time information; and when data is written to the last plurality of data pages of a specific block of the flash memory module, writing the time information generated by the time management circuit to one of the last plurality of data pages.

In another embodiment of the present invention, an electronic device is disclosed, comprising a flash memory module and a flash memory controller. The flash memory module comprises a plurality of flash memory chips, each of which comprises a plurality of blocks, each of which comprises a plurality of data pages; and the flash memory controller is used to access the flash memory module, wherein the flash memory controller generates a current time information; and when the flash memory controller writes data to the last plurality of data pages of a specific block of the flash memory module, the flash memory controller writes the time information generated by the time management circuit to one of the last plurality of data pages.

100,500,600:Memory device

110,510,610: Flash memory controller

112: Microprocessor

112C:Program code

112M: Read-only memory

114: Control Logic

116: Buffer memory

118: Interface Logic

119,519,619: Time management circuit

120: Flash memory module

130: Main device

132: Encoder

134:Decoder

N1, N2: specific pins

200,710: Block

202: Floating gate transistor

BL1, BL2, BL3: bit lines

WL0~WL2,WL4~WL6: character line

P0, P1, P2, P3, P(N-1), PN: data page

400: Time information comparison table

517,617:Timer

302,712: Time information

800~808: Steps

Figure 1 is a schematic diagram of a memory device according to a first embodiment of the present invention.

Figure 2 is a schematic diagram of a block in a flash memory module according to an embodiment of the present invention.

Figure 3 is a schematic diagram of the block and data page.

Figure 4 is a schematic diagram of a time information comparison table according to an embodiment of the present invention.

Figure 5 is a schematic diagram of a memory device according to a second embodiment of the present invention.

Figure 6 is a schematic diagram of a memory device according to a third embodiment of the present invention.

Figure 7 is a timing diagram of the flash memory controller powering off and on.

Figure 8 is a flow chart of a method for managing a flash memory module according to an embodiment of the present invention.

FIG. 1 is a schematic diagram of a memory device 100 according to a first embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. In this embodiment, the flash memory controller 110 includes a microprocessor 112, a read-only memory (ROM) 112M, a control logic 114, a buffer memory 116, an interface logic 118, and a time management circuit 119. The read-only memory 112M is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access to the flash memory module 120. The control logic 114 includes an encoder 132 and a decoder 134, wherein the encoder 132 is used to encode the data written into the flash memory module 120 to generate a corresponding checksum (or error correction code, ECC), and the decoder 134 is used to decode the data read from the flash memory module 120.

In a typical case, the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks, and the flash memory controller 110 performs data erasure operations on the flash memory module 120 in units of blocks. In addition, a block can record a specific number of data pages, wherein the flash memory controller 110 performs data writing operations on the flash memory module 120 in units of data pages. In this embodiment, the flash memory module 120 is a 3D NAND-type flash module.

In practice, the flash memory controller 110 executing the program code 112C through the microprocessor 112 can use its own internal components to perform a variety of control operations, such as using the control logic 114 to control the access operation of the flash memory module 120 (especially the access operation of at least one block or at least one data page), using the buffer memory 116 to perform the required buffer processing, and using the interface logic 118 to communicate with a host device (Host Device) 130. In addition, the time management circuit 119 is connected to a specific pin N2 of the host device through a specific pin N1 of the flash memory controller. The buffer memory 116 is implemented as a random access memory (RAM). For example, the buffer memory 116 may be a static random access memory (SRAM), but the present invention is not limited thereto.

In one embodiment, the memory device 100 may be a portable memory device (e.g., a memory card conforming to SD/MMC, CF, MS, XD standards), and the host device 130 is an electronic device connectable to the memory device, such as a mobile phone, a laptop, a desktop computer, etc. In another embodiment, the memory device 100 may be a solid state drive or an embedded storage device conforming to Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications, to be set in an electronic device, such as a mobile phone, a laptop, or a desktop computer, and the host device 130 may be a processor of the electronic device.

FIG. 2 is a schematic diagram of a block 200 in a flash memory module 120 according to an embodiment of the present invention, wherein the flash memory module 120 is a three-dimensional NAND flash memory. As shown in FIG. 2, the block 200 includes a plurality of memory cells (e.g., floating gate transistors 202 or other charge trap elements shown in the figure), which are connected to a three-dimensional NAND flash memory architecture through a plurality of bit lines (only BL1 to BL3 are shown in the figure) and a plurality of word lines (e.g., WL0 to WL2, WL4 to WL6 shown in the figure). In FIG. 2 , taking the top plane as an example, all floating gate transistors on word line WL0 constitute at least one data page, all floating gate transistors on word line WL1 constitute at least another data page, and all floating gate transistors on word line WL2 constitute at least another data page... and so on. In addition, depending on the flash memory writing method, the definition between word line WL0 and data page (logical data page) will also be different. Specifically, when using single-level storage (SLC) writing, all floating gate transistors on word line WL0 correspond to only a single logical data page; when using double-level storage (MLC) writing, all floating gate transistors on word line WL0 correspond to two logical data pages; when using triple-level storage (TLC) writing, all floating gate transistors on word line WL0 correspond to three logical data pages; and when using quad-level storage (MLC) writing, all floating gate transistors on word line WL0 correspond to three logical data pages. When writing in a QLC (Quadrature Cell) mode, all floating gate transistors on word line WL0 correspond to four logical data pages. Since a person with ordinary knowledge in this technical field should be able to understand the structure of a 3D NAND flash memory and the relationship between word lines and data pages, the relevant details will not be elaborated here.

The structure shown in FIG. 2 is only a simple description of the basic structure of the 3D flash memory. In actual manufacturing, there will be more layers of stacking to achieve a higher density storage capacity. Since the 3D flash memory adopts the stacking structure shown in FIG. 2, the data storage will encounter a very serious data retention problem, that is, after the data is written into block 200, after a period of time, the memory cells therein will encounter data writing level changes, critical voltage drift, etc., and data quality problems, so that the data in block 200 may encounter difficulties in decoding when it is subsequently read, or even fail to successfully complete the decoding, resulting in data loss. Therefore, this embodiment proposes a management method for a flash memory module 120, which can set a time management circuit 119 in the flash memory controller 110 to efficiently record the time information of each block for quality judgment and subsequent appropriate processing. The specific operation content is described in detail as follows.

FIG. 3 shows a schematic diagram of a block 200 including a plurality of data pages P0-PN. When the flash memory controller 110 needs to write data from the host device 130, data from other blocks in the flash memory module 120, and/or data temporarily stored in the flash memory controller 110 itself into the block 200, the flash memory controller 110 will sequentially write these data from the first data page P0 to the last data page PN. In this embodiment, when the flash memory controller 110 is ready to write data to the last data page PN, or to write data to the last multiple data pages, the time management circuit 119 sends a request command to the host device 130 through the specific pin N1 to request the host device 130 to provide the current time information. Since the host device 130 is connected to the operating system, it can provide the current time information (for example, month, day, minute, second, etc.) 302 to the time management circuit 119. After receiving the time information 302, the time management circuit 119 will provide the time information 302 to the microprocessor 112, so that the microprocessor 112 can write it into the data page PN together with other data after being processed by the encoder 132.

Since the last data page PN of the block 200 records an absolute time (e.g., a timestamp), when the subsequent flash memory controller 110 and the flash memory module 120 are in an idle state, the flash memory controller 110 can scan each block and obtain the time point when the block is completed by directly reading the last data page PN of each block. Afterwards, the flash memory controller 110 uses the current time obtained by the time management circuit 119 from the host device 130 to determine how long the data in each block has been stored (i.e., the time difference between the completion of the write operation of each block and the current block scan). In this embodiment, if the storage time of the data in a block is higher than a critical value (for example, a month or several weeks have passed since the block was written), the flash memory controller 110 can determine that the block may encounter data preservation problems, and therefore, the block is placed in the garbage collection operation process, and at a suitable time point in the future, the valid data in the block is moved to another block and the content of the block is erased.

As described above, through the management method of this embodiment, the flash memory controller 110 can simply and efficiently know how long the data in each block has been stored, so as to determine whether each block is about to encounter data storage problems and make appropriate subsequent treatments.

In another embodiment of the present invention, in addition to writing the time information in the last data page PN of each block, the microprocessor 112 also establishes a time information comparison table 400 as shown in FIG. 4, which records the time information written to each block (for example, block 1, block 2, block 3, block 4 in FIG. 4) (for example, time information 1, time information 2, time information 3, time information 4 in FIG. 4). In this embodiment, the time information comparison table 400 can be temporarily stored in an external dynamic random access memory or the internal buffer memory 116 of the flash memory controller 110, so that the flash memory controller 110 can quickly determine how long the data in each block has been stored without reading each block of the flash memory module 120, and perform appropriate subsequent processing.

In addition, when the flash memory controller 110 is ready to shut down or the memory needs to release space, the time information comparison table 400 can be written to the appropriate address in the flash memory module 120 to avoid data loss.

In another embodiment, in order to use memory space more efficiently, the content of the time information mapping table 400 can be integrated into other mapping tables/mapping tables, such as a logical address to physical address mapping table or a physical address to logical address mapping table.

FIG. 5 is a schematic diagram of a memory device 500 according to a second embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 510, and the flash memory controller 510 is used to access the flash memory module 120. In this embodiment, the flash memory controller 510 includes a microprocessor 112, a read-only memory 112M, a control logic 114, a buffer memory 116, an interface logic 118, a timer 517 and a time management circuit 519. The read-only memory 112M stores a program code 112C, and the control logic 114 includes an encoder 132 and a decoder 134. The components with the same numbers in FIG. 5 and FIG. 1 have similar operations, so the details will not be repeated. Therefore, the following description is only for the timer 517 and the time management circuit 519.

In this embodiment, the time management circuit 519 can be integrated into the microprocessor 112, and when the flash memory controller 510 is powered on (that is, when the memory device 500 is turned on and the flash memory controller 510 starts to connect to the host device 130), the time management circuit 519 receives the initial time (that is, the time point when the flash memory controller 510 is powered on) from the host device 130, and since the host device 130 itself is connected to the operating system, it can provide the initial time (for example, information such as month, day, minute, second, etc.) to the time management circuit 519. After that, the timer 517 starts to continuously calculate the time that has passed since the flash memory controller 510 was powered on.

Meanwhile, referring to block 200 shown in FIG. 3 , when the flash memory controller 510 needs to write data from the host device 130, data from other blocks in the flash memory module 120, and/or data temporarily stored in the flash memory controller 510 itself into block 200, the flash memory controller 510 will sequentially write these data from the first data page P0 to the last data page PN. In this embodiment, when the flash memory controller 510 is ready to write data to the last data page PN, or to write data to the last multiple data pages, the time management circuit 519 adds the initial time to the time after the flash memory controller 510 is powered on, calculated by the current timer 517, to generate a time information. After the time management circuit 119 calculates the time information, it will provide this information to the microprocessor 112, so that the microprocessor 112 can write it into the data page PN together with other data after processing by the encoder 132.

In the embodiment shown in FIG. 5 , the time management circuit 519 obtains the absolute time information (i.e., the initial time mentioned above) from the main device 130 only when the flash memory controller 510 is powered on, and thereafter the absolute time is calculated by its own timer 517.

Since the last data page PN of block 200 records the absolute time (the absolute time calculated by the content of the initial time timer 517), when the subsequent flash memory controller 510 and the flash memory module 120 are in an idle state, the flash memory controller 510 can scan each block and obtain the time point when the block completes the write operation by directly reading the last data page PN of each block. Afterwards, the time management circuit 519 calculates the current time by adding the initial time to the content of the timer 517 to determine how long the data in each block has been stored (that is, the time difference between the completion of the write operation of each block and the current block scan). In this embodiment, if the storage time of the data in a block is higher than a critical value (for example, a month or several weeks have passed since the block was written), the flash memory controller 510 can determine that the block may encounter data preservation problems, and therefore, the block is placed in the garbage collection operation process, and at a subsequent appropriate time point, the valid data in the block is moved to another block and the block is erased.

As described above, through the management method of this embodiment, the flash memory controller 510 can simply and efficiently know how long the data in each block has been stored, so as to determine whether each block is about to encounter data storage problems and make appropriate subsequent treatments.

In the embodiment shown in FIG. 5 , the microprocessor 112 may also establish a time information mapping table 400 as shown in FIG. 4 , or integrate the content of the time information mapping table 400 into other mapping tables/mapping tables, such as a logical address to physical address mapping table or a physical address to logical address mapping table.

FIG6 is a schematic diagram of a memory device 600 according to a third embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 610, and the flash memory controller 610 is used to access the flash memory module 120. In this embodiment, the flash memory controller 610 includes a microprocessor 112, a read-only memory 112M, a control logic 114, a buffer memory 116, an interface logic 118, a timer 617 and a time management circuit 619. The read-only memory 112M stores a program code 112C, and the control logic 114 includes an encoder 132 and a decoder 134. The components with the same numbers in FIG. 6 and FIG. 1 have similar operations, so the details will not be repeated. Therefore, the following description is only for the timer 617 and the time management circuit 619.

In this embodiment, the time management circuit 619 can be integrated into the microprocessor 112, and when the flash memory controller 610 is powered on (that is, when the memory device 600 is turned on and the flash memory controller 610 starts to connect with the host device 130), the time management circuit 619 will obtain a reference time at an appropriate time point, and the timer 617 will start to continuously calculate the time that has passed since the flash memory controller 610 was powered on.

In this embodiment, the time management circuit 619 does not obtain any absolute time information from the host device 130, but estimates the current time from the content stored in the flash memory module 120. For example, referring to FIG. 7 , assuming that the flash memory controller 610 is powered off at time t0, and the flash memory controller 610 is powered on at time t1, the microprocessor 112 can read the time information 712 stored in the last block 710 that completed the write operation before time t0, and then estimate a predicted time to represent the power-off time length (i.e., (t1-t0)), and finally add the time information 712 to the predicted time to obtain the reference time. In one embodiment, since the flash memory controller 610 itself cannot accurately know the length of the power-off time (i.e., (t1-t0)), the flash memory controller 610 can estimate the predicted time by reading the data content of block 710 and based on the data quality of block 710, wherein the worse the data quality means the longer the data is stored, i.e., the longer the power-off time. For example, the microprocessor 112 can read the data of block 710 and generate the predicted time according to the bit error rate of the data, wherein the higher the bit error rate, the longer the estimated predicted time; the microprocessor 112 can also read the data of block 710 and determine the voltage distribution of the memory cells in block 710. The predicted time is generated, wherein the more dispersed the voltage distribution is, the longer the estimated predicted time is; or the microprocessor 112 can also read the data of block 710 and determine the critical voltage offset of the memory cell in block 710 to generate the predicted time, wherein the higher the critical voltage offset is, the longer the estimated predicted time is.

Meanwhile, referring to block 200 shown in FIG. 3 , when the flash memory controller 610 needs to write data from the main device 130, data from other blocks in the flash memory module 120, and/or data temporarily stored in the flash memory controller 610 itself into block 200, the flash memory controller 610 will sequentially write these data from the first data page P0 to the last data page PN. In this embodiment, when the flash memory controller 610 is ready to write data to the last data page PN, or to write data to the last multiple data pages, the time management circuit 619 adds the reference time to the time after the flash memory controller 610 is powered on, calculated by the current timer 617, to generate a time information. After the time management circuit 619 calculates the time information, it provides the information to the microprocessor 612, so that the microprocessor 112 can write it into the data page PN together with other data after processing by the encoder 132.

When the subsequent flash memory controller 610 and the flash memory module 120 are in an idle state, the flash memory controller 610 can scan each block and obtain the time point when the block is completed by directly reading the last data page PN of each block. Afterwards, the time management circuit 619 calculates the current time by adding the content of the timer 617 to the reference time to determine how long the data in each block has been stored (that is, the time difference between the completion of the write operation of each block and the current block scan). In this embodiment, if the storage time of the data in a block is higher than a critical value (for example, a month or several weeks have passed since the block was written), the flash memory controller 610 can determine that the block may encounter data preservation problems, so the block is placed in the garbage collection operation process, and at a suitable time point in the future, the valid data in the block is moved to another block and the block is erased.

As described above, through the management method of this embodiment, the flash memory controller 610 can simply and efficiently know how long the data in each block has been stored, so as to determine whether each block is about to encounter data storage problems and make appropriate subsequent treatments.

Figure 8 is a flow chart of a method for managing a flash memory module according to an embodiment of the present invention. With reference to the contents described in the above embodiment, the process is as follows.

Step 800: The process starts.

Step 802: Generate current time information.

Step 804: When data is written to the last multiple data pages of a specific block of the flash memory module, write the time information to one of the last multiple data pages.

Step 806: Create/update a lookup table/mapping table to store each block and the corresponding time information.

Step 808: Determine the data quality of each block based on the time information of the block, and decide whether to move the data of the block to other blocks accordingly.

To simply summarize the present invention, in the flash memory controller of the present invention, by recording the time information of each block, it is possible to quickly and efficiently determine whether the data retention time is too long and may cause data quality problems, and accordingly perform appropriate subsequent operations in advance to avoid data loss problems.

The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Memory device

110: Flash memory controller

112: Microprocessor

112C:Program code

112M: Read-only memory

114: Control Logic

116: Buffer memory

118: Interface Logic

119: Time management circuit

120: Flash memory module

130: Main device

132: Encoder

134:Decoder

N1, N2: specific pins

Claims (6)

A flash memory controller is used to access a flash memory module, wherein the flash memory module includes a plurality of flash memory chips, each of which includes a plurality of blocks, each of which includes a plurality of data pages, and the flash memory controller includes: a read-only memory for storing a program code; a microprocessor for executing the program code to control the flash memory module; wherein when the flash memory controller and the flash memory module are in an idle state, the microprocessor scans at least a portion of the multiple blocks, and directly reads the last data page of each block in the at least a portion of the blocks to obtain the time information when the block completes the write operation, so as to determine whether there are any blocks in the at least a portion of the blocks that may encounter data storage problems. A flash memory controller as described in Item 1 of the patent application, wherein the time information of the block when the write operation is completed is an absolute time. The flash memory controller as described in item 1 of the patent application scope further includes: a time management circuit coupled to the microprocessor for generating a current time information; wherein the microprocessor calculates a time difference between the time information of each block in the at least a portion of the blocks and the current time according to the current time generated by the time management circuit, and determines whether the block may encounter data preservation problems according to the time difference. An electronic device includes: a flash memory module, wherein the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of data pages; and a flash memory controller for accessing the flash memory module; wherein when the flash memory controller and the flash memory module When the group is in an idle state, the flash memory controller scans at least a portion of the multiple blocks, and directly reads the last data page of each block in the at least a portion of the blocks to obtain the time information when the block completes the write operation, so as to determine whether there are blocks in the at least a portion of the blocks that may encounter data storage problems. An electronic device as described in Item 4 of the patent application, wherein the time information of the block when the write operation is completed is an absolute time. As described in item 4 of the patent application scope, the flash memory controller calculates a time difference between the time information of each block in the at least part of the blocks and the current time based on a current time generated by a time management circuit, and determines whether the block may encounter data preservation problems based on the time difference.

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