CN118484150B - Storage device and fault processing method thereof - Google Patents
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1435—Saving, restoring, recovering or retrying at system level using file system or storage system metadata
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- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0253—Garbage collection, i.e. reclamation of unreferenced memory
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/0644—Management of space entities, e.g. partitions, extents, pools
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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Abstract
The invention provides a storage device and a fault processing method thereof, wherein the storage device comprises: the flash memory comprises a plurality of blocks for storing host data, wherein the plurality of blocks are of multi-layer storage unit type, and a plurality of idle blocks form an idle block pool; the main controller is electrically connected with the flash memory, and is used for monitoring the time interval of the adjacent two times of power-up of the storage device and comparing the time interval with a time threshold; when the time interval is smaller than or equal to a time threshold value, the main controller selects a plurality of blocks from the idle block pool and sets the blocks as pseudo single-layer memory cell blocks, wherein the service performance of the pseudo single-layer memory cell blocks is the same as that of the blocks of the single-layer memory cell types; the host controller stores host data and a data mapping table associated with the host data in the pseudo-single layer storage unit. The invention can enable the storage device to quickly finish disk recognition and enter the system under the condition that the storage device is powered off and on continuously.
Description
Technical Field
The invention relates to the technical field of static storage, in particular to storage equipment and a fault processing method thereof.
Background
Memory chips are a specific application of the concept of embedded system chips in the memory industry. Whether a system chip or a memory chip, the system chip and the memory chip are realized by embedding software in a single chip, so that the system chip can realize multifunction, high performance and support to various protocols, various hardware and different applications. The memory chip is widely applied to the fields of computers, mobile equipment, internet of things and the like, and is used for storing various data such as an operating system, application programs, music, videos, photos and the like.
Under the condition that the storage device is powered off and powered on continuously, the garbage collection treatment time of the storage device is too long, and the storage device can not successfully recognize a disk and enter a system. Therefore, there is a need for improvement.
Disclosure of Invention
The invention provides a storage device and a fault processing method thereof, which are used for solving the technical problems that the storage device cannot successfully recognize a disk and enter a system under the condition of continuous power-off and power-on of the storage device.
The present invention provides a storage device comprising:
The flash memory comprises a plurality of blocks for storing host data, wherein the blocks are of a multi-layer storage unit type, and a plurality of idle blocks form an idle block pool;
The main controller is electrically connected with the flash memory, and is used for monitoring the time interval of the adjacent two times of power-on of the storage device and comparing the time interval with a time threshold;
When the time interval is smaller than or equal to the time threshold, the main controller selects a plurality of blocks from the idle block pool and sets the blocks as pseudo single-layer memory unit blocks, wherein the use performance of the pseudo single-layer memory unit blocks is the same as that of blocks of single-layer memory unit types;
The main controller stores host data and a data mapping table associated with the host data into the pseudo-single layer storage unit.
In one embodiment of the present invention, the main controller is configured to power off during the process of storing the host data and the data mapping table in the pseudo single-layer storage unit, and write a preset value or invalid data in the pseudo single-layer storage unit that is not stored when the storage device is powered up again, so as to avoid performing garbage collection operation.
In one embodiment of the present invention, the number of abnormal power-off data recovery times is recorded in the main controller, and when the time interval is less than or equal to a time threshold and the storage device is powered up again to perform data recovery, the main controller updates the number of abnormal power-off data recovery times.
In one embodiment of the present invention, the main controller is configured to store host data and a data mapping table associated with the host data into the block when the time interval is greater than a time threshold.
In one embodiment of the present invention, the main controller is configured to set the usage performance of the pseudo single-layer memory cell block to be the same as the usage performance of the multi-layer memory cell type block when the time interval is greater than the time threshold, and store host data and a data mapping table associated with the host data into the pseudo single-layer memory cell.
In one embodiment of the present invention, the main controller is configured to form a static block pool from the plurality of pseudo single-layer memory cell blocks, and select a plurality of blocks from the spare block pool again when the memory space of the static block pool is used up, and divide the blocks into the static block pool.
The invention also provides a storage device fault processing method, which comprises the following steps:
Receiving host data, storing the host data into a plurality of blocks of a flash memory, and forming a plurality of idle blocks into an idle block pool, wherein the plurality of idle blocks are of a multi-layer storage unit type;
monitoring the time interval of two adjacent times of power-on of the storage equipment, and comparing the time interval with a time threshold;
When the time interval is smaller than or equal to the time threshold, selecting a plurality of blocks from the idle block pool, and setting the blocks as pseudo single-layer memory unit blocks, wherein the service performance of the pseudo single-layer memory unit blocks is the same as that of blocks of single-layer memory unit types;
and storing the host data and a data mapping table associated with the host data into the pseudo single-layer storage unit.
In one embodiment of the present invention, after the step of storing host data and the data mapping table associated with the host data in the pseudo single layer memory unit, the method includes:
and when power is cut off in the process of storing the host data and the data mapping table into the pseudo single-layer storage unit and the storage equipment is powered on again, writing preset values or invalid data into the pseudo single-layer storage unit which is not stored, so as to avoid executing garbage recycling operation.
In one embodiment of the present invention, after the step of storing host data and the data mapping table associated with the host data in the pseudo single layer memory unit, the method includes:
And when the time interval is greater than the time threshold, storing host data and a data mapping table associated with the host data into the block.
In one embodiment of the present invention, after the step of storing host data and the data mapping table associated with the host data in the pseudo single layer memory unit, the method includes:
Setting the use performance of the pseudo single-layer memory cell block to be the same as the use performance of the multi-layer memory cell type block when the time interval is larger than the time threshold;
and storing the host data and a data mapping table associated with the host data into the pseudo single-layer storage unit.
The invention has the beneficial effects that: according to the storage device and the fault processing method thereof, provided by the invention, under the condition that the storage device is powered off and on continuously, the storage device can be enabled to finish disc recognition and enter the system rapidly, so that the service performance and the service life of the storage device can be further improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a memory device according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a free block pool according to an embodiment of the present invention.
Fig. 3 is a schematic diagram illustrating the movement of the free block pool and the static block pool according to an embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating the partitioning of free block pools and static block pools according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of steps of a method for handling a failure of a storage device according to an embodiment of the present invention.
Fig. 6 is a schematic diagram illustrating steps following step S40 in fig. 5 according to an embodiment of the present invention.
Description of the reference numerals
10. A host; 20. a storage device; 30. a main controller; 40. a flash memory; 41. a block; 42. a page; 401. a free pool of blocks; 402. a static block pool; 410. a data mapping block; 411. a host block; 412. a garbage collection block.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In the following description, numerous details are set forth in order to provide a more thorough explanation of embodiments of the present invention, it will be apparent, however, to one skilled in the art that embodiments of the present invention may be practiced without these specific details, in other embodiments, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present invention.
Referring to fig. 1 to 6, the present invention provides a storage device and a fault handling method thereof, which can be applied to storage devices 20 such as eMMC (Embedded Multi MEDIA CARD), SSD (Solid STATE DISK ), UFS (Univeral Flash Storage, universal flash memory) and the like. The invention solves the problem of overlong garbage recovery processing time of the storage device 20 under the condition that the storage device 20 is powered off and powered on continuously, and can enable the storage device 20 to finish disk recognition and enter a system rapidly, thereby further improving the service performance and service life of the storage device 20. The following is a detailed description of specific embodiments.
Referring to fig. 1, in an embodiment of the present invention, a memory device 20 is provided, a bus interface is provided on the memory device 20, and the memory device 20 is electrically connected to a host 10 through the bus interface. The host 10 may write host data, which refers to application data written by the host 10, to the storage device 20 and send instructions, or the host 10 may read host data and receive instructions from the storage device 20. The host 10 may be a communication device such as a personal computer (PC, personal Computer), a tablet (Pad), a mobile Phone (Cell Phone), etc.
Referring to fig. 1, in one embodiment of the present invention, a memory device 20 may include a main controller 30 and a flash memory 40. The main controller 30 is provided with a flash memory interface, and the main controller 30 is electrically connected with the flash memory 40 through the flash memory interface. The main controller 30 is mainly used for operating and managing the flash Memory 40, and the main controller 30 also provides functions of Cache (Cache), memory array (Memory array), and interleaving (interleaving). The main controller 30 can control various functions of the flash memory 40, such as bad flash management, wear leveling, error Checking and Correction (ECC), etc., and the main controller 30 can greatly improve the read-write and moving operation performance of host data in the flash memory 40.
Referring to fig. 1 and 2, in one embodiment of the present invention, the flash memory 40 is a non-volatile memory, which is commonly used to store host data, system programs, and the like, in the memory device 20. The flash memory 40 may include a plurality of blocks (blocks) 41, the blocks 41 may be used to store a data mapping table and host data written by the host 10, and one Block 41 may further include a plurality of pages (pages) 42.
Specifically, the memory granule on the plurality of blocks 41 is a multi-layer memory cell type, wherein the multi-layer memory cell type is compared to the single-layer memory cell (SLC, single Level Cell) type. For example, the Multi-layer memory cell may be a dual layer memory cell (MLC, multi LEVEL CELL), a triple layer memory cell (TLC, trinary Level Cell), a Quad layer memory cell (QLC, quad LEVEL CELL), or a five layer memory cell (PLC, PENTA LEVEL CELL) that has not yet been developed. The multi-layer memory cell as a memory means in the present embodiment can store multi-bit information, increases memory capacity, and has lower cost and moderate use performance.
Specifically, as shown in fig. 2, the free block pool 401 may be formed by a plurality of free blocks 41, and the plurality of free blocks 41 in the free block pool 401 are unused blocks 41, i.e., host data may be written into the plurality of free blocks 41 in the free block pool 401. According to the functional partitioning, the free block pool 401 may include a data mapping block 410, a host block 411, and a garbage collection block 412. The data mapping block 410 is represented as a block 41 for storing a data mapping table storing mapping information of logical addresses and physical addresses of host data. The host block 411 is represented as block 41 for storing host data. Garbage collection block 412 is shown as block 41 where garbage collection is required.
Referring to fig. 1 and 2, in one embodiment of the present invention, the main controller 30 may monitor the time interval between two adjacent power-up of the storage device 20 and compare the time interval with a time threshold to determine whether the storage device 20 is in a continuous power-down power-up condition. The time threshold is a non-zero constant and is used for comparing with the time interval to judge the value of the time interval. For example, after the storage device 20 is first powered up into the system, the first power up time is recorded and updated into a storage snapshot (snapshot), which functions to perform online data backup and restore. The first power-up time may be read and the time interval between power-ups may be calculated at the next power-up of the memory device 20. The time threshold may be set to 2 minutes, and when the time interval is less than or equal to 2 minutes, the phenomenon that the storage device 20 is powered up, powered down, and powered up again occurs within 2 minutes may indicate that the storage device 20 is in a continuously powered down and powered up state.
Specifically, for example, if the storage device 20 is suddenly powered off, and if operations such as garbage collection processing or updating the data mapping table are not completed, the data may be in an inconsistent state, so that the storage device 20 cannot normally identify and load the data, which affects the start-up and data reading of the system. Therefore, after the storage device 20 is powered up again, the main controller 30 performs a recovery operation, completes the incomplete garbage collection process, and repairs the data mapping table. After ensuring the consistency and integrity of all data, the storage device 20 is normally identified and allowed access to the data therein.
Specifically, if the storage apparatus 20 is in the continuously powered-off and powered-on state, the garbage collection process cannot be successfully completed every time the storage apparatus 20 tries to perform the garbage collection process. The power-off condition is encountered again each time garbage collection processing is started, so that the garbage collection process needs to be restarted from the place where the power-off is last time when the power-on is next time. In the state where the storage device 20 is continuously powered off and powered on, it takes a lot of time to recycle garbage, thereby extending the time for the storage device to start up and even resulting in failure of the storage device 20 to successfully recognize a disk and enter the system.
Referring to fig. 1 and 2, in one embodiment of the present invention, the main controller 30 selects a plurality of blocks 41 from the free block pool 401 based on the comparison result of the time interval and the time threshold, and marks as pseudo single-layer flash memory cell blocks (pSLC, pseudo SINGLE LEVEL CELL), and sets the usage performance of the pseudo single-layer flash memory cell blocks to be the same as that of the blocks 41 of the single-layer flash memory cell (SLC, single Level Cell) type.
Specifically, after selecting a plurality of blocks 41 from the free block pool 401 to be pseudo single-layer flash memory cell blocks, the physical structure of the plurality of blocks 41 is not changed. Instead, for Multi-layer memory cells such as a dual-layer memory cell (MLC, multi LEVEL CELL), a triple-layer memory cell (TLC, trinary Level Cell), and a Quad-layer memory cell (QLC, quad LEVEL CELL), the Multi-layer memory cell is switched to a single-bit mode, and the single-bit mode is that the Multi-layer memory cell stores only one bit of information, instead of storing multiple bits of information originally, so that writing and reading speeds can be improved.
In particular, the integrity of the data mapping table and other critical metadata is critical to proper operation within the storage device 20. When writing data mapping tables or other critical metadata using single-level memory cells, even if the metadata is not completely written during power down, the remainder is considered an invalid or unknown state, not an error state, due to the characteristics of the single-level memory cells.
Specifically, the performance of the pseudo single-layer flash memory cell block is set to be the same as that of the single-layer flash memory cell type block 41. In the continuous power-down power-up state of the storage device 20, the main controller 30 selects to fill dummy (dummy) data instead of uncertain data content when the main controller 30 detects a dummy single-layer flash memory cell block in which metadata writing is not completed by checking. The dummy data may be a preset value or invalid data. By writing preset values or invalid data into the pseudo single-layer flash memory unit blocks, the pseudo single-layer flash memory unit blocks can be marked as valid and used continuously, so that complex garbage collection processing is not required to be executed to clean and sort metadata. The embodiment can simplify the recovery process, and avoid the time required for waiting for garbage recovery to be completed, thereby accelerating the starting speed and disk recognition time of the storage device 20 after power failure, and improving the stability and response capability of the storage device 20.
Referring to fig. 1 and 2, in one embodiment of the present invention, the main controller 30 is configured to store the host data and the data mapping table associated with the host data in the pseudo single layer memory unit when the time interval is less than or equal to the time threshold.
Specifically, the time interval of the storage device 20 may be equal to or less than the time threshold, that is, the time interval of two adjacent power-up, that is, the case that the storage device 20 is powered up, powered down, and powered up again. In other embodiments, it may also occur that the storage device 20 is powered down more than once and powered up again after power down. It is considered that the continuous power-off and power-on condition of the storage device 20 can be considered as long as the time interval between the adjacent two powers-on is equal to or less than the time threshold. When the time interval is less than or equal to the time threshold, that is, when the storage device 20 is powered off continuously, the data mapping table associated with the host data is stored in the pseudo single-layer storage unit, so that the starting speed and the disk recognition time of the storage device 20 can be increased when the storage device 20 is powered on to recover the data.
Referring to fig. 1 and 2, in one embodiment of the present invention, the main controller 30 is configured to power off during the process of storing the host data and the data mapping table in the pseudo single-layer memory unit, and write the preset value or invalid data in the pseudo single-layer memory unit that is not stored when the memory device 20 is powered up again, so as to avoid performing the garbage collection operation.
Specifically, power failure occurs during the process of storing the host data and the data mapping table in the pseudo single layer storage unit, and when the storage device 20 is powered up again, recovery data processing is required for the storage device 20. In the case of storing the host data and the data mapping table associated with the host data in the pseudo single-layer memory cells, when the recovery data processing is performed on the storage device 20, the pseudo single-layer flash memory cell blocks can be quickly marked as valid and used continuously by writing the preset value or invalid data into the pseudo single-layer flash memory cell blocks, so that complicated garbage collection processing is not required to clean up and sort the metadata.
Referring to fig. 1 and 2, in one embodiment of the present invention, a data recovery register is provided in the main controller 30, and records the number of abnormal power-off data recovery times (SPOR, software Power Off Recovery), and when the time interval is less than or equal to the time threshold, and the storage device 20 is powered up again to perform data recovery, the data recovery register updates the number of abnormal power-off data recovery times.
Specifically, the number of abnormal power-off data recovery reflects the data recovery condition of the storage device 20 after power-off and power-on, that is, an increase in the number of abnormal power-off data recovery indicates that the storage device 20 needs to perform data recovery after power-on. If the storage device 20 is normally powered off, then the storage device 20 does not need to be data recovery processed after the next normal power up. In this embodiment, the storage device 20 is not powered down continuously in the event that the time interval is greater than the time threshold. In the case where the time interval is greater than the time threshold, it may also happen that an abnormal power failure of the storage device 20 belongs to the case where the abnormal power failure is considered in combination with the actual situation, and the case where the time interval is greater than the time threshold is taken as an example of normal power failure of the storage device 20 in this embodiment.
Specifically, when the time interval of the storage device 20 is less than or equal to the time threshold and the number of times of recovering the abnormal power-off data is abnormal, the data mapping table associated with the host data and the host data may be stored in the pseudo single layer storage unit. That is, in a state that the storage device 20 is continuously powered off and powered on, and the increase of the number of times of recovering abnormal power-off data indicates that the storage device 20 needs to recover data after being powered on, storing the host data and the data mapping table associated with the host data in the pseudo single-layer storage unit can avoid performing garbage collection operation after the storage device 20 is powered on again.
Referring to fig. 1 and 2, in one embodiment of the present invention, the main controller 30 is configured to store the host data and the data mapping table associated with the host data in the block 41 when the time interval is greater than the time threshold.
Specifically, when the time interval of the storage device 20 is greater than the time threshold, it indicates that the storage device 20 is not powered on continuously, and at this time, the host data and the data mapping table associated with the host data may be stored in the block 41, that is, the host data and the data mapping table are stored on the block 41 in the free block pool 401 according to the normal procedure.
Referring to fig. 1 and 2, in one embodiment of the present invention, the main controller 30 is configured to set the usage performance of the pseudo single-layer memory cell block to be the same as the usage performance of the multi-layer memory cell type block when the time interval is greater than the time threshold, and store the host data and the data mapping table associated with the host data into the pseudo single-layer memory cell.
Specifically, since a plurality of blocks 41 are selected from the free block pool 401, they are denoted as pseudo single layer memory cell blocks. The selection of the plurality of pseudo single-layer memory cell blocks is to consider that if the memory device 20 is powered down and powered up continuously, the memory device 20 cannot be successfully read and enter the system in order to avoid the problem that the garbage collection operation is performed for too long after the memory device 20 is powered up again. However, if the memory device 20 is not in a continuous power-down power-up state at all times, then there are instances where multiple blocks of pseudo single-layer memory cells have not been used, a wear leveling operation (WEAR LEVELING) may occur.
Thus, to avoid a wear leveling operation that may occur, when the time interval of the storage device 20 is greater than the time threshold, it is indicated that the storage device 20 is not continuously powered down. Setting the service performance of the pseudo single-layer memory cell block to be the same as that of the multi-layer memory cell type block, and storing the host data and a data mapping table associated with the host data into the pseudo single-layer memory cell. Namely, the pseudo single-layer memory cell block keeps the original service performance, namely, the multi-layer memory cell stores multi-bit information, and the storage bit number is kept the same as the number of the memory cell layers. For example, a dual-layer memory cell stores two bits of information and a triple-layer memory cell stores three bits of information.
Referring to fig. 1,2,3 and 4, in one embodiment of the present invention, the main controller 30 is configured to form a static block pool 402 from a plurality of pseudo single-layer memory cell blocks, and select a plurality of blocks 41 from the free block pool 401 again when the memory space of the static block pool 402 is used up, and divide the blocks into the static block pool 402.
Specifically, as shown in fig. 3 and 4, a plurality of pseudo single-layer memory cell blocks are formed into a static block pool 402, and the static block pool 402 is used to distinguish from a spare block pool 401, where in practice, the static block pool 402 and the spare block pool 401 are all blocks 41 on the flash memory 40. The marking of the free block pool 401 and the static block pool 402 from the flash memory 40 is to enable the host data and the data mapping table associated with the host data to be correspondingly stored in the free block pool 401 or the static block pool 402 under different states such as normal power-off or continuous power-off and power-on of the storage device 20.
Specifically, when the storage space of the static block pool 402 is used up, a plurality of blocks 41 may be selected from the free block pool 401 again and divided into the static block pool 402. The selection of a plurality of blocks 41 from the spare block pool 401 to be divided into the static block pool 402 can leave a margin in the storage space in the static block pool 402, so as to prevent the problem that the storage device 20 cannot successfully recognize a disk and enter the system when the storage device 20 is powered off and powered on continuously.
Referring to fig. 5, in an embodiment of the present invention, a method for handling a storage device failure is provided, which may include the following steps.
Step S10, receiving host data, storing the host data into a plurality of blocks of the flash memory, and forming a plurality of idle blocks into an idle block pool, wherein the plurality of blocks are of a multi-layer storage unit type.
And step S20, monitoring the time interval of two adjacent times of power-up of the storage device, and comparing the time interval with a time threshold.
And S30, selecting a plurality of blocks from the idle block pool and setting the blocks as pseudo single-layer memory cell blocks when the time interval is smaller than or equal to a time threshold, wherein the use performance of the pseudo single-layer memory cell blocks is the same as that of the blocks of the single-layer memory cell type.
Step S40, storing the host data and the data mapping table associated with the host data into the pseudo single layer storage unit.
The following is a detailed description of specific embodiments.
Step S10, receiving host data, storing the host data into a plurality of blocks of the flash memory, and forming a plurality of idle blocks into an idle block pool, wherein the plurality of blocks are of a multi-layer storage unit type.
In one embodiment of the present invention, the memory granule on the plurality of blocks 41 is a multi-layer memory cell type, wherein the multi-layer memory cell type is compared to a single-layer memory cell (SLC, single Level Cell) type. For example, the Multi-layer memory cell may be a dual layer memory cell (MLC, multi LEVEL CELL), a triple layer memory cell (TLC, trinary Level Cell), a Quad layer memory cell (QLC, quad LEVEL CELL), or a five layer memory cell (PLC, PENTA LEVEL CELL) that has not yet been developed. The multi-layer memory cell as a memory means in the present embodiment can store multi-bit information, increases memory capacity, and has lower cost and moderate use performance.
And step S20, monitoring the time interval of two adjacent times of power-up of the storage device, and comparing the time interval with a time threshold.
In one embodiment of the present invention, the time interval between two adjacent power-up of the storage device 20 may be monitored and compared to a time threshold to determine if the storage device 20 is in a continuous power-down power-up condition. For example, after the storage device 20 is first powered up into the system, the first power up time is recorded and updated into a storage snapshot (snapshot), which functions to perform online data backup and restore. The first power-up time may be read and the time interval between power-ups may be calculated at the next power-up of the memory device 20. The time threshold may be set to 2 minutes, and when the time interval is less than or equal to 2 minutes, the phenomenon that the storage device 20 is powered up, powered down, and powered up again occurs within 2 minutes may indicate that the storage device 20 is in a continuously powered down and powered up state.
And S30, selecting a plurality of blocks from the idle block pool and setting the blocks as pseudo single-layer memory cell blocks when the time interval is smaller than or equal to a time threshold, wherein the use performance of the pseudo single-layer memory cell blocks is the same as that of the blocks of the single-layer memory cell type.
In one embodiment of the present invention, the physical structure of the blocks 41 is not changed after the blocks 41 are selected from the free block pool 401 to be written as pseudo single layer flash memory cell blocks. Instead, for Multi-layer memory cells such as a dual-layer memory cell (MLC, multi LEVEL CELL), a triple-layer memory cell (TLC, trinary Level Cell), and a Quad-layer memory cell (QLC, quad LEVEL CELL), the Multi-layer memory cell is switched to a single-bit mode, and the single-bit mode is that the Multi-layer memory cell stores only one bit of information, instead of storing multiple bits of information originally, so that writing and reading speeds can be improved.
Step S40, storing the host data and the data mapping table associated with the host data into the pseudo single layer storage unit.
In one embodiment of the present invention, the use performance of the pseudo single-layer flash memory cell block is set to be the same as the use performance of the single-layer flash memory cell type block 41, and the host data and the data mapping table associated with the host data are stored in the pseudo single-layer memory cell. In the continuous power-down power-up state of the storage device 20, the main controller 30 selects to fill dummy (dummy) data instead of uncertain data content when the main controller 30 detects a dummy single-layer flash memory cell block in which metadata writing is not completed by checking. The dummy data may be a preset value or invalid data. By writing preset values or invalid data into the pseudo single-layer flash memory unit blocks, the pseudo single-layer flash memory unit blocks can be marked as valid and used continuously, so that complex garbage collection processing is not required to be executed to clean and sort metadata.
In one embodiment of the present invention, after step S40, power failure may occur during the process of storing the host data and the data mapping table in the pseudo single-layer memory unit, and when the memory device 20 is powered up again, a preset value or invalid data is written in the pseudo single-layer memory unit that is not stored, so as to avoid performing the garbage collection operation.
Specifically, in the case where the storage device 20 is powered up and needs to recover data, when storing host data and the data mapping table in the pseudo single layer memory unit, dummy (virtual) data may be filled in the blank page 42 in the pseudo single layer memory unit to replace the uncertain data content. The dummy data may be a preset value or invalid data. By writing preset values or invalid data into the pseudo single-layer flash memory unit blocks, the pseudo single-layer flash memory unit blocks can be marked as valid and used continuously, so that complex garbage collection processing is not required to be executed to clean and sort metadata.
Referring to fig. 6, in an embodiment of the present invention, step S40 may be followed by step S510, step S520 and step S530. Step S510 may be represented as storing host data and a data mapping table associated with the host data in the block 41 of the free block pool 401 when the time interval of the storage device 20 is greater than the time threshold.
Specifically, when the time interval of the storage device 20 is greater than the time threshold, it indicates that the storage device 20 is not powered on continuously, and at this time, the host data and the data mapping table associated with the host data may be stored in the block 41, that is, the host data and the data mapping table are stored on the block 41 in the free block pool 401 according to the normal procedure.
Step S520 may represent setting the usage performance of the pseudo single layer memory cell block to be the same as the usage performance of the multi layer memory cell type block when the time interval of the memory device 20 is greater than the time threshold. Step S530 may be represented as storing host data and a data mapping table associated with the host data in a pseudo-single layer storage unit.
In particular, to avoid a wear leveling operation that may occur, when the time interval of the storage device 20 is greater than the time threshold, it is indicated that the storage device 20 is not powered up continuously. Setting the service performance of the pseudo single-layer memory cell block to be the same as that of the multi-layer memory cell type block, and storing the host data and a data mapping table associated with the host data into the pseudo single-layer memory cell. Namely, the pseudo single-layer memory cell block keeps the original service performance, namely, the multi-layer memory cell stores multi-bit information, and the storage bit number is kept the same as the number of the memory cell layers. For example, a dual-layer memory cell stores two bits of information and a triple-layer memory cell stores three bits of information.
In summary, the invention provides a storage device and a fault processing method thereof, which can solve the problem of overlong garbage recycling time of the storage device under the condition that the storage device is powered off and powered on continuously. The invention can enable the storage device to quickly finish disc recognition and enter the system, thereby further improving the service performance and service life of the storage device.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Claims (8)
1. A memory device, comprising:
The flash memory comprises a plurality of blocks for storing host data, wherein the blocks are of a multi-layer storage unit type, and a plurality of idle blocks form an idle block pool;
The main controller is electrically connected with the flash memory, and is used for monitoring the time interval of the adjacent two times of power-on of the storage device and comparing the time interval with a time threshold;
When the time interval is smaller than or equal to the time threshold, the main controller selects a plurality of blocks from the idle block pool and sets the blocks as pseudo single-layer memory unit blocks, wherein the use performance of the pseudo single-layer memory unit blocks is the same as that of blocks of single-layer memory unit types;
The main controller stores host data and a data mapping table associated with the host data into the pseudo single-layer storage unit;
The main controller is used for generating power failure in the process of storing the host data and the data mapping table in the pseudo single-layer storage unit, and writing preset value or invalid data in the pseudo single-layer storage unit which is not stored when the storage device is powered up again, so that garbage collection operation is avoided.
2. The storage device of claim 1, wherein the number of abnormal power-off data recovery times is recorded in the main controller, and the main controller updates the number of abnormal power-off data recovery times when the time interval is less than or equal to a time threshold and the storage device is powered up again for data recovery.
3. The storage device of claim 1, wherein the master controller is to store host data and a data mapping table associated with the host data into the block when the time interval is greater than a time threshold.
4. The memory device of claim 1, wherein the main controller is configured to set the usage performance of the dummy single-layer memory cell block to be the same as the usage performance of the multi-layer memory cell type block when the time interval is greater than the time threshold, and store host data and a data mapping table associated with the host data into the dummy single-layer memory cell.
5. The memory device of claim 1, wherein the main controller is configured to form a static block pool from a plurality of the pseudo single-layer memory cell blocks, and to select a plurality of the blocks from the free block pool again when the memory space of the static block pool is used up, and divide the blocks into the static block pool.
6. A storage device failure handling method, comprising:
Receiving host data, storing the host data into a plurality of blocks of a flash memory, and forming a plurality of idle blocks into an idle block pool, wherein the plurality of idle blocks are of a multi-layer storage unit type;
monitoring the time interval of two adjacent times of power-on of the storage equipment, and comparing the time interval with a time threshold;
When the time interval is smaller than or equal to the time threshold, selecting a plurality of blocks from the idle block pool, and setting the blocks as pseudo single-layer memory unit blocks, wherein the service performance of the pseudo single-layer memory unit blocks is the same as that of blocks of single-layer memory unit types;
Storing host data and a data mapping table associated with the host data into the pseudo single-layer storage unit;
and when power is cut off in the process of storing the host data and the data mapping table into the pseudo single-layer storage unit and the storage equipment is powered on again, writing preset values or invalid data into the pseudo single-layer storage unit which is not stored, so as to avoid executing garbage recycling operation.
7. The storage device failure handling method of claim 6, wherein after the step of storing host data and the data mapping table associated with the host data in the pseudo-single layer storage unit, comprising:
And when the time interval is greater than the time threshold, storing host data and a data mapping table associated with the host data into the block.
8. The storage device failure handling method of claim 6, wherein after the step of storing host data and the data mapping table associated with the host data in the pseudo-single layer storage unit, comprising:
Setting the use performance of the pseudo single-layer memory cell block to be the same as the use performance of the multi-layer memory cell type block when the time interval is larger than the time threshold;
and storing the host data and a data mapping table associated with the host data into the pseudo single-layer storage unit.
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