CN111415906A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method for forming the same, the forming method includes: etching a substrate of a first area to form a first fin and a first groove between the first fins; etching the substrate of a second area to form a second fin and a second groove located between the second fins, the second fins include a bottom fin and a top fin located on the bottom fin, in the extension direction perpendicular to the second fin, the width of the bottom fin is greater than the width of the first fin; wherein, the depth of the second groove is greater than the depth of the first groove; a first isolation layer is formed in the second groove, and the first isolation layer at least covers the bottom fin. In the embodiment of the present invention, by increasing the width of the bottom fin, the rigidity of the second fin is greater, and the ability of the second fin to withstand the stress of the first isolation layer is correspondingly greater, thereby reducing the second fin. The probability of the fins being bent due to the stress of the first isolation layer is beneficial to improve the performance and performance uniformity of the device.

Description

Semiconductor structure and method of forming the same

technical field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

In semiconductor manufacturing, with the development trend of VLSI, the feature size of integrated circuits continues to decrease. In order to adapt to the smaller feature size, the Metal-Oxide-Semiconductor Field-Effect Transistor , MOSFET) channel length is correspondingly shortened. However, with the shortening of the channel length of the device, the distance between the source electrode and the drain electrode of the device is also shortened, so the control ability of the gate structure to the channel becomes worse, and the gate voltage pinch off the channel. The difficulty of the channel is also increasing, making the phenomenon of subthreshold leakage (subthreshold leakage), the so-called short-channel effects (SCE), more likely to occur.

Therefore, in order to better accommodate the reduction of feature size, the semiconductor process gradually begins to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as Fin Field Effect Transistors (FinFETs). In FinFET, the gate structure can control the ultra-thin body (fin) from both sides at least. Compared with the planar MOSFET, the gate structure has stronger control of the channel and can well suppress the short-channel effect; And compared with other devices, FinFET has better compatibility with existing integrated circuit manufacturing.

SUMMARY OF THE INVENTION

The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to optimize the electrical performance of the semiconductor structure.

In order to solve the above problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a first region and a second region, the first region is used for forming a first device, and the first region is used to form a first device. The second region is used to form a second device, and the power of the second device is lower than that of the first device; the substrate of the first region is etched to form a first fin and a space between the first fins the first groove; the base of the second area is etched to form a second fin and a second groove between the second fins, the second fin includes a bottom fin and a bottom fin For the top fins on the fins, in the extension direction perpendicular to the second fins, the width of the bottom fins is greater than the width of the top fins; wherein, the depth of the second grooves is greater than that of the second fins. the depth of the first groove; a first isolation layer is formed in the second groove, and the first isolation layer covers at least the bottom fin.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate, the substrate includes a first region and a second region, the first region is used to form a first device, and the second region is used for In forming a second device, the power of the second device is lower than the power of the first device; the first fins are located on the substrate of the first region, and the region between the first fins is a first groove; a second fin, located on the substrate of the second area, the area between the second fins is a second groove, and the second fin includes a bottom fin and a For the top fins on the bottom fins, in the extending direction perpendicular to the second fins, the width of the bottom fins is greater than the width of the top fins; wherein, the depth of the second grooves is greater than the depth of the first groove; an isolation layer is located in the first groove and the second groove, and the isolation layer covers at least the bottom fin.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

After the first isolation layer is formed in the embodiment of the present invention, the first isolation layer is generally annealed to make the material of the first isolation layer denser, but correspondingly, the first isolation layer has a larger thickness. The second fin includes a bottom fin and a top fin located on the bottom fin, and along an extension direction perpendicular to the second fin, the bottom fin is wider than the top fin Compared with the case where the overall width of the second fin is equal to the width of the top fin, the embodiment of the present invention increases the width of the bottom fin to make the second fin more rigid. The ability to withstand the stress of the first isolation layer is correspondingly greater, thereby reducing the probability of the second fin portion being bent due to the stress of the first isolation layer, thereby facilitating the improvement of device performance and performance uniformity.

Description of drawings

1 to 2 are schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure;

3 to 13 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention;

14 to 20 are schematic structural diagrams corresponding to steps in another embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention.

Detailed ways

It can be known from the background art that the devices formed at present still have the problem of poor performance. Now combined with a method of forming a semiconductor structure, the reasons for the poor performance of the device are analyzed.

Referring to FIG. 1 to FIG. 2 , schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure are shown.

Referring to FIG. 1, a substrate 4 and fins protruding from the substrate 4 are formed, the substrate 4 includes a first region I and a second region II, and the first region I is used to form a first device, The second region II is used to form a second device, and the power of the second device is lower than that of the first device; the region between the fins of the first region is a first groove, and the power of the second device is lower than that of the first device. The area between the two-region fins is a second groove, and the depth of the second groove 6 is greater than the depth of the first groove 3 .

In a direction perpendicular to the extending direction of the second fins 5 , the widths of the first fins 2 and the second fins 5 are equal.

Referring to FIG. 2 , an isolation layer is formed in the first groove 3 (as shown in FIG. 1 ) and the second groove 6 (as shown in FIG. 1 ) using a flow chemical vapor deposition process (Flowable Chemical Vapor Deposition, FCVD). 7.

After the isolation layer 7 is formed, the isolation layer 7 is usually annealed. The annealing treatment breaks the Si-H bond and the Si-O bond in the isolation layer 7, so that the isolation layer 7 is easily deformed, thereby becoming more dense, and correspondingly, the isolation layer 7 has larger stress. Because the second groove 6 is deeper than the first groove 3, the thickness of the isolation layer 7 in the second groove 6 is greater than the thickness of the isolation layer 7 in the first groove 3, so the The second fin portion 5 is subjected to greater stress, and the second fin portion 5 is more flexible than the first fin portion 2; and because the height of the second fin portion 5 is greater than that of the first fin portion 2, the rigidity of the second fin portion 5 is less than that of the first fin portion 2, and under the same stress, the second fin portion 5 is more flexible.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a first region and a second region, and the first region is used to form a first device, so The second region is used to form a second device, and the power of the second device is lower than the power of the first device; the substrate of the first region is etched to form a first fin and a fin located in the first fin A first groove between the parts; etching the base of the second region to form a second fin and a second groove between the second fins, the second fin includes a bottom fin and For the top fins on the bottom fins, in the extending direction perpendicular to the second fins, the width of the bottom fins is greater than the width of the top fins; wherein, the depth of the second grooves greater than the depth of the first groove; a first isolation layer is formed in the second groove, and the first isolation layer covers at least the bottom fin.

After the first isolation layer is formed in the embodiment of the present invention, the first isolation layer is generally annealed to make the material of the first isolation layer denser, but correspondingly, the first isolation layer has a larger thickness. stress; the second fin includes a bottom fin and a top fin located on the bottom fin, along an extension direction perpendicular to the second fin, and the bottom fin is wider than the top fin For the fin, compared with the case where the overall width of the second fin is equal to the width of the top fin, the embodiment of the present invention increases the width of the bottom fin to make the second fin more rigid. The ability of the second fin to withstand the stress of the first isolation layer is correspondingly greater, thereby reducing the probability of the second fin portion being bent due to the stress of the first isolation layer, thereby improving device performance and performance uniformity.

In order to make the above objects, features and advantages of the embodiments of the present invention more clearly understood, specific embodiments of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

3 to 13 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

3, a substrate 100 is provided, the substrate 100 includes a first region I and a second region II, the first region I is used to form a first device, the second region II is used to form a second device, so The power of the second device is lower than the power of the first device.

The substrate 100 is used to provide a process basis for forming fins.

In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. In other embodiments, in order to improve the performance of the device, SiGe channel technology may also be used, that is, the material of the substrate includes silicon germanium, and the material of the corresponding subsequently formed fin and channel layer is SiGe. An interface layer can also be formed on the surface of the substrate 100 , and the material of the interface layer is silicon oxide, silicon nitride or silicon oxynitride.

The subsequent step further includes patterning the substrate 100, forming a first fin in the first region I, and forming a second fin in the second region II.

In this embodiment, the first fin portion is formed first, and then the second fin portion is formed as an example for description. In other embodiments, the first fins may also be formed after the second fins are formed.

Referring to FIG. 4 , the substrate 100 of the first region I (as shown in FIG. 3 ) is etched to form first fins 101 and first grooves 102 between the first fins 101 . The first groove 102 is used to prepare for the subsequent formation of the second isolation layer.

The step of forming the first fin portion 101 includes: etching the base 100 of the first region I and the second region II to form a first substrate 104 and an initial fin portion located on the first substrate 104, wherein The initial fins on the first region I serve as the first fins 101 .

The step of forming the first fins 101 further includes: after the substrate 100 is provided, and before the substrate 100 is etched, a mask layer 103 is formed on the substrate 100 . The mask layer 103 is used as an etching mask for etching the substrate 100 to form the first fins 101 .

In this embodiment, the material of the mask layer 103 is SiN. In other embodiments, the material of the mask layer may also be SiON, SiCN, SiOCN or SiBCN.

5 to 6 , it should be noted that after forming the initial fins, the method further includes: forming a second isolation layer 105 on the first substrate 104 exposed by the first fins 101 (as shown in FIG. 6 ). shown).

The material of the second isolation layer 105 is an insulating material, and the second isolation layer 105 is used to electrically isolate the adjacent first fins 101 on the first region I.

In this embodiment, the material of the second isolation layer 105 is silicon oxide. In other embodiments, the material of the second isolation layer may also be silicon oxynitride, silicon nitride, silicon oxycarbonitride or amorphous carbon.

The steps of forming the second isolation layer 105 include: forming a second isolation material layer 106 covering the first fins 101 ; planarizing the second isolation material layer 106 until the mask layer 103 is exposed; After the mask layer 103 is formed, the mask layer 103 is used as a mask to etch back a partial thickness of the second isolation material layer 106 , and the remaining second isolation material layer 106 is used as the second isolation layer 105 .

In this embodiment, the second isolation material layer 106 is formed by a Flowable Chemical Vapor Deposition (FCVD).

It should be noted that the second isolation layer 105 is also formed on the first substrate 104 in the second region II.

Referring to FIGS. 7 to 8 , the substrate 100 of the second region II is etched to form second fins 107 (as shown in FIG. 8 ) and second grooves 110 between the second fins 107 (eg 8); the depth of the second groove 110 is greater than the depth of the first groove 102 (shown in FIG. 2); the second fin 107 includes a bottom fin 1071 and a For the top fins 1072 on the fins 1071 , the width of the bottom fins 1071 is greater than the width of the top fins 1072 in the direction perpendicular to the extending direction of the second fins 107 .

A first isolation layer is subsequently formed in the second groove 110. After the first isolation layer is formed, Si-H bonds and Si-O bonds usually exist in the first isolation layer, and the first isolation layer is annealed Treatment, annealing treatment breaks Si-H bonds and Si-O bonds, the material of the first isolation layer becomes more dense, but it is also easy to cause deformation of the first isolation layer, so that the first isolation layer is have greater stress. The second fin portion 107 includes a bottom fin portion 1071 and a top fin portion 1072 located on the bottom fin portion 1071, along the extending direction perpendicular to the second fin portion 107, and the bottom fin portion 1071 is wider than For the top fins 1072, compared with the case where the overall width of the second fins 107 is equal to the width of the top fins 1072, the embodiment of the present invention increases the width of the bottom fins 1071 to increase the rigidity of the second fins 107. larger, the ability of the second fins 107 to withstand the stress of the first isolation layer is correspondingly greater, thereby reducing the probability of the second fins 107 being bent due to the stress of the first isolation layer, thereby helping to improve the performance of the device. performance and performance uniformity.

Moreover, the heat dissipation coefficient of the first isolation layer is generally smaller than the heat dissipation coefficient of the second fins 107 . By making the width of the bottom fin portion 1071 larger than the width of the top fin portion 1072 , the volume of the bottom fin portion 1071 , the volume of the bottom fin portion 107 , and the second fin portion 107 and the first fin portion 107 located below the second fin portion 107 are increased. The contact area of the two substrates 109 accordingly improves the heat dissipation performance of the device, improves the self-heating effect of the device, and further optimizes the electrical performance of the semiconductor structure.

As shown in FIGS. 7 to 8 , specifically, the step of forming the second fins 107 includes: in the second region II, forming a cap layer 108 on the sidewalls of the initial fins (as shown in FIG. 8 ) shown); using the cap layer 108 as a mask, the first substrate 104 exposed by the initial fins in the second region II is etched, and the remaining first substrate after etching is used as the second The substrate 109 , the protrusions on the second substrate 109 serve as the second fins 107 .

In this embodiment, using the cap layer 108 as a mask, the first substrate 104 exposed by the initial fins in the second region II is etched to form the second fins 107 and the second fins 107 located in the second region II. The second groove 110 between the two fins 107 . Because the cap layer 108 on the sidewalls of the initial fins is used as a mask in the process of forming the second fins 107 by etching, the bottom fins 1071 are perpendicular to the extending direction of the initial fins than The top fin portion 1072 is wide, and the thickness of the cap layer 108 determines the width difference between the bottom fin portion 1071 and the top fin portion 1072 in the second fin portion 107 .

In the process of forming the second fins 1047, the etching rate of the capping layer 108 is lower than the etching rate of the first substrate 104, so that the capping layer 108 can serve as an etching mask , so that the bottom fin portion 1071 is wider than the top fin portion 1072 .

In this embodiment, the material of the cap layer 108 includes SiN. In other embodiments, the material of the capping layer includes SiCN, SiOCN or SiBCN.

It should be noted that the cap layer 108 should not be too thick or too shallow. If the cap layer 108 is too thick, it takes too much process time to form the cap layer 108 , and the bottom fin 1071 is too wide compared to the top fin 1072 , correspondingly, perpendicular to the second fin In the direction of the fins 107, the width of the second grooves 110 is too narrow, and the subsequent first isolation layer formed on the second substrate 109 exposed by the second fins 107 cannot well realize the electrical power of adjacent devices. Isolation; if the cap layer 108 is too shallow, the width of the bottom fin portion 1071 will be too small. After the first isolation layer is annealed, the second fin portion 107 is easy to bend under the stress of the first isolation layer, making the semiconductor The uniformity of device performance is poor. In this embodiment, the thickness of the cap layer 108 is 3 nanometers to 10 nanometers.

The steps of forming the capping layer 108 include: forming a capping material layer 114 (as shown in FIG. 7 ) conformally covering the initial fins; in the second region II, removing the caps on top of the initial fins For the material layer 114 , the capping material layer 114 on the sidewall of the initial fin portion of the second region II is reserved as the capping layer 108 .

In this embodiment, the capping material layer 114 is formed by chemical vapor deposition (Chemical Vapor Deposition, CVD) or atomic layer deposition (Atomic Layer Deposition, ALD).

It should be noted that after the initial fins are formed and before the capping layer 108 is formed, the second isolation layer 105 has been formed on the first substrate 104 exposed by the initial fins, so the capping material layer 114 In addition to conformally covering the initial fin, it also conformally covers the second isolation layer 105 exposed by the initial fin.

It should be noted that in the process of etching the first substrate 104 exposed by the initial fins in the second region II using the cap layer 108 as a mask, the mask layer 103 also acts as a mask. Etch mask. That is, the cap layer 109 and the mask layer 103 together serve as an etching mask for etching the first substrate 104 in the second region II.

The method for forming the semiconductor structure further includes: after forming the capping material layer 114 and before removing the capping material layer 114 on top of the initial fins, forming a protection on the capping material layer 114 in the first region I Layer 111.

The protective layer 111 is used to protect the first fins 101 in the first region I during the process of forming the second fins 107 to prepare for the subsequent formation of devices on the first fins 101 The protective layer 111 also protects the capping material layer 114 in the first region I during the process of forming the second fins 107, and the capping material layer 114 protects the second isolation layer 105 from avoiding the subsequent formation of the first isolation layer. damaged.

In this embodiment, the material of the protective layer 111 is an organic material. The protective layer 111 of the material is easy to remove in the subsequent process, and is not easy to have residues.

Specifically, in this embodiment, the material of the protective layer 111 may be BARC (bottom anti-reflective coating) material, ODL (organic dielectric layer, organic dielectric layer) material, photoresist, DARC (dielectric anti-reflective coating, dielectric anti-reflective coating) material, DUO (Deep UV Light Absorbing Oxide, deep ultraviolet light absorbing oxide layer) material or APF (Advanced Patterning Film, advanced graphics film) material.

In this embodiment, the protective layer 111 is formed on the cap material layer 114 in the first region I by using a spin coating process.

Correspondingly, the step of forming the second fins 107 includes: using the protective layer 111 as a mask, etching the capping material layer to form the capping layer 108 ; after forming the capping layer 108 , using the capping layer 108 and the protective layer 111 are used as masks to etch the second isolation layer 105; after the second isolation layer 105 is etched, the second region is etched using the cap layer 108 and the protective layer 111 as masks In the first substrate 104 in II, the second fins 107 and the second grooves 110 between the second fins 107 are formed.

Referring to FIG. 9 , after forming the second fins 107 , the capping layer 108 (as shown in FIG. 8 ) is removed.

The capping layer 108 is removed to prepare for subsequent device formation on the second fins 107 .

In this embodiment, the cap layer 108 is removed by a wet etching process. In the process of removing the capping layer 108 by wet etching, the etching rate of the capping layer 108 is greater than the etching rate of the second fins 107 .

In this embodiment, the material of the capping layer 108 is silicon nitride, and correspondingly, a phosphoric acid solution is used to remove the capping layer 108 .

Referring to FIG. 10 , after the capping layer 108 is removed, the protective layer 111 is removed.

In this embodiment, the material of the protective layer 111 is a BARC material, and the BARC material is an organic material. The organic material is volatile at high temperature and pollutes the machine. Therefore, the protective layer 111 is removed before forming the first isolation layer, so as to avoid the volatilization of the protective layer 111 during the process of forming the first isolation layer to contaminate the machine.

In this embodiment, the protective layer 111 is removed by an ashing process or a dry etching process.

Referring to FIGS. 11 and 12 , a first isolation layer 112 (as shown in FIG. 12 ) is formed in the second groove 110 (as shown in FIG. 10 ), and the first isolation layer 112 covers at least the bottom fin Section 1071.

Generally speaking, the thickness of the first isolation layer 112 is greater than the thickness of the second isolation layer 105 , so the source and drain electrodes formed in the top fin portion 1072 are not easily penetrated, and the The thickness of the first isolation layer 112 can better isolate the device.

Specifically, the step of forming the first isolation layer 112 includes: forming the first isolation material layer 113 (as shown in FIG. 11 ) covering the second fins 107 ; flattening the first isolation material layer 113 Chemical treatment until the mask layer 103 is exposed; after the mask layer 103 is exposed, the mask layer 103 is used as a mask to etch back a partial thickness of the first isolation material layer 113, and the remaining first isolation material layer 113 is etched back. The material layer 113 serves as the first isolation layer 112 .

In this embodiment, the first isolation material layer 113 is formed by a flow chemical vapor deposition process.

In this embodiment, after the first isolation layer 112 is formed, the top of the first isolation layer 112 is lower than the top of the second isolation layer 105 to prepare for the subsequent removal of the capping material layer 114 in the first region I. Specifically, the capping material layer 114 is higher than the first isolation layer 112 and the second isolation layer 105 , so that the capping material layer 114 is easier to remove.

It should be noted that, the first isolation material layer 113 is also formed on the cap material layer 114 in the first region I. In the process of etching back the first isolation material layer 113 to form the first isolation layer 105 , the capping material layer 114 functions as an etching resist layer, so that the second isolation layer 105 is prevented from being etched by mistake .

It should be noted that, in other embodiments, after the initial fins are formed, the second isolation layer may not be formed. Correspondingly, in the step of forming the first isolation layer, the first isolation layer is further formed in the first groove, and the tops of the isolation layers in the first groove and the second groove are flush.

Referring to FIG. 13 , after the first isolation layer 112 is formed, the capping material layer 114 is removed.

The capping material layer 114 is removed in preparation for subsequent semiconductor fabrication.

In this embodiment, the cap material layer 114 is removed by a wet etching process. During the wet etching process, the etching speed of the capping material layer 114 is greater than the etching speed of the first isolation layer 112 and the second isolation layer 105 . In other embodiments, the capping material layer may also be removed by a combination of wet and dry processes.

In this embodiment, the material of the cap material layer 114 is silicon nitride, and correspondingly, the used etching solution is phosphoric acid solution.

14 to 20 are schematic structural diagrams corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention.

The similarities between this embodiment and the previous embodiment will not be repeated here. The difference between this embodiment and the previous embodiment is that after the second fins 202 (as shown in FIG. 15 ) are formed, the first fins 210 (as shown in FIG. 19 ) are formed.

14 and 15 , the base 200 of the second region II is etched to form a second substrate 201 (as shown in FIG. 15 ) and initial fins 202 protruding from the second substrate 201 (eg Figure 15).

Specifically, the step of forming the initial fins 202 includes: forming a first mask layer 204 on the second region II, and etching the first mask layer 204 in the second region II by using the first mask layer 204 as a mask The base 200 forms the second substrate 201 and the initial fins 202 protruding from the second substrate 201 .

In this embodiment, the material of the first mask layer 204 is silicon nitride. In other embodiments, the material of the first mask layer may also be one or more of silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride.

The step of forming the semiconductor structure includes: before etching the substrate 200 in the second region II, further forming a first blocking layer 203 on the substrate 200 in the first region I.

During the process of forming the second fins 202, the first shielding layer 203 protects the substrate 200 in the first region I from being etched.

The steps of forming the first shielding layer 203 and the first mask layer 204 include: forming a shielding material layer covering the substrate 200; forming a photoresist layer (not shown in the figure) on the shielding material layer, so that the The photoresist layer is a mask to etch the shielding material layer to form a first shielding layer 203 located in the first area I and a first mask layer 204 located in the second area II.

Referring to FIG. 16 , a protective layer 205 is formed on the second substrate 201 exposed by the initial fins 202 (as shown in FIG. 15 ), and the protective layer 205 covers part of the sidewalls of the initial fins 202 .

In the subsequent process of oxidizing the initial fins 202 with the protective layer 205 exposed, the sidewalls of the initial fins 202 covered by the protective layer 205 are not oxidized, which is used for the subsequent formation of the second fins. Prepare.

In this embodiment, the protective layer 205 is an organic material. The protective layer 205 is removed in the subsequent process, and it is difficult to have residues.

Specifically, the material of the protective layer 205 is BARC material. In other embodiments, the material of the protective layer may also be ODL material, photoresist, DARC material, DUO material or APF material.

Continuing to refer to FIG. 16 and referring to FIG. 17 , the sidewalls of the initial fins 202 exposed by the protective layer 205 are oxidized, and the partial width of the initial fins 202 is converted into the oxide layer 207 , and the remaining initial fins 202 are used as all The second fin portion 206 is described.

In this embodiment, a thermal oxidation process is used to oxidize the sidewalls of the initial fins 202 to convert a partial width of the initial fins 202 into an oxide layer 207 .

Specifically, the process parameters of the thermal oxidation treatment include: the process temperature is 700°C to 1000°C, the process time is 100S to 1000S; the chamber pressure is 50torr to 300torr; the flow rate of oxygen is 1/20 liters/minute to 1/5 L/min; nitrogen flow rate is 1/20 liter/min to 1/5 liter/min.

In this embodiment, the material of the initial fin portion 202 is silicon, and the material of the oxide layer 207 is correspondingly silicon oxide.

Because the sidewalls of the partial thickness of the initial fins 202 exposed to the protective layer 205 are converted into oxide layers 207 , the top fins 2062 in the second fins 206 that expose the protective layer 205 are located in the protective layer In 205 is the bottom fin 2061 . After the oxide layer 207 is subsequently removed, the bottom fin 2061 is wider than the top fin 2062 perpendicular to the extending direction of the second fin 206 .

In the second area II, the area between the second fins 206 is the second groove 214 (as shown in FIG. 17 ). The subsequent process further includes forming an isolation layer in the second groove 214. Generally, the The heat dissipation coefficient of the isolation layer is smaller than the heat dissipation coefficient of the second fins 206 . By making the width of the bottom fins 2061 larger than the width of the top fins 2062, the volume of the bottom fins 2062 and the contact area between the second fins 206 and the second substrate 201 are increased, and the corresponding increase The heat dissipation performance of the device is improved, the self-heating effect of the device is improved, and the electrical performance of the semiconductor structure is optimized.

After the isolation layer is subsequently formed, Si-H bonds and Si-O bonds usually exist in the isolation layer, and the isolation layer is annealed, and the annealing treatment breaks the Si-H bonds and Si-O bonds, and the isolation The material of the layer becomes denser, but it also tends to cause deformation of the isolation layer, so that there is a greater stress in the isolation layer. The second fin portion 206 includes a bottom fin portion 2061 and a top fin portion 2062 located on the bottom fin portion 2061, along the extending direction perpendicular to the second fin portion 206, and the bottom fin portion 2061 is wider than For the top fins 2062, compared with the case where the overall width of the second fins 206 is equal to the width of the top fins 2062, the embodiment of the present invention increases the width of the bottom fins 2061 to increase the rigidity of the second fins 206. larger, the ability of the second fin portion 206 to withstand the stress of the isolation layer is correspondingly greater, thereby reducing the probability of the second fin portion 206 being bent due to the stress of the isolation layer, which is beneficial to improve the performance and uniformity of the device. sex.

It should be noted that, in the first region I, the sidewall of the substrate exposing the protective layer 205 is also oxidized and converted into the oxide layer 207, but this part of the oxide layer is removed in the subsequent process of forming the first fin, Therefore, the oxidation treatment will not affect the subsequent formation of the first fins.

Continuing to refer to FIG. 17 , the oxide layer 207 (as shown in FIG. 15 ) and the protective layer 205 (as shown in FIG. 15 ) are removed.

Removing the oxide layer 207 exposes the sidewalls of the top fins 2062 in the second fins 206 to prepare for subsequent device formation on the second fins 206 .

In this embodiment, the oxide layer 207 is removed by a wet etching process. During the wet etching process, the etching rate of the oxide layer 207 is greater than the etching rate of the second fin portion 206 .

In this embodiment, the wet etching solution is a hydrofluoric acid solution.

The protective layer 205 is removed to prepare for the subsequent formation of the first fins in the first region I.

In this embodiment, the protection 205 is removed by an ashing process.

It should be noted that, in the process of removing the oxide layer 207 and the protective layer 205, the first mask layer 204 and the first shielding layer 203 are also removed.

Referring to FIG. 18 , after removing the oxide layer 207 and the protective layer 205 , a filling layer 208 is formed on the second substrate 201 exposed by the second fins 206 , and the filling layer 208 covers the second fins 206 sidewall.

A fin protection layer is subsequently formed on the filling layer 208, and the filling layer 208 provides support for the subsequent formation of the fin protection layer.

In this embodiment, the material of the filling layer 208 is an organic material, which is easy to be removed in the subsequent process and is unlikely to be left behind.

Specifically, the material of the filling layer 208 is BARC material. In other embodiments, the material of the filling layer may also be ODL material, photoresist, DARC material, DUO material or APF material.

Referring to FIG. 19 , after the filling layer 208 is formed, the base 200 of the first region I is etched to form a first substrate 209 and a first fin 210 protruding from the first substrate 209 . Between the first fins 210 are first grooves 215 .

The steps of forming the first fins 210 include: forming a second mask layer 211 on the substrate 200 in the first region I; etching the first region by using the second mask layer 211 as a mask The base 200 of I forms the first fins 210 .

In this embodiment, the material of the second mask layer 211 is silicon nitride. In other embodiments, the material of the second mask layer may also be one or more of silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride.

It should be noted that, in the process of forming the second mask layer 211, a fin protection layer 212 is formed on the filling layer 208 in the second region II.

During the process of etching the substrate 200 in the first region I to form the first fins 210 , the fin protection layer 212 protects the second fins 206 from being easily etched.

It should be noted that, after the first fins 210 are formed, the filling layer 208 is removed.

In this embodiment, the filling layer 208 is removed by an ashing process.

Referring to FIG. 20 , isolation layers 213 are formed in the first grooves 215 (shown in FIG. 19 ) and the second grooves 214 (shown in FIG. 17 ).

The isolation layer 213 is used to achieve electrical isolation of adjacent devices.

In this embodiment, the step of forming the isolation layer 213 includes: forming an isolation material layer (not shown in the figure) covering the first fin part 210 and the second fin part 206 , and performing a planarization process on the isolation material layer Until the fin protection layer 212 and the second mask layer 211 are exposed; after the fin protection layer 212 and the second mask layer 211 are exposed, the fin protection layer 212 and the second mask layer 211 are used as The mask is etched back to a partial thickness of the isolation material layer, the remaining isolation material layer located in the second region II is used as the isolation layer, and the remaining isolation material layer located in the first region I is used as the second isolation layer.

In this embodiment, the isolation material layer is formed by a flow chemical vapor deposition process.

The method for forming the semiconductor structure includes: after forming the filling layer 208 and before forming the isolation layer 213 , removing the fin protection layer 212 and the second mask layer 211 .

In this embodiment, the second mask layer 211 and the fin protection layer 212 are removed by a wet etching process.

Specifically, the material of the first fin portion 210 and the fin portion protective layer 212 is silicon nitride, and correspondingly, the wet etching solution is phosphoric acid solution.

It should be noted that, in this embodiment, the first isolation layer is formed in the second groove 214 , and the second isolation layer is formed in the first groove 215 .

Correspondingly, an embodiment of the present invention further provides a semiconductor structure. Referring to FIG. 13 , a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown.

The semiconductor structure includes a substrate, the substrate includes a first region I and a second region II, the first region I is used to form a first device, the second region II is used to form a second device, so The power of the second device is lower than the power of the first device; the first fins 101 are located on the substrate of the first region I, and the region between the first fins 101 is the first groove 110 (as shown in FIG. 10 ); the second fins 107 are located on the substrate of the second area II, and the area between the second fins 107 is the second groove 102 (as shown in FIG. 4 ) ), the second fin portion 107 includes a bottom fin portion 1071 and a top fin portion 1072 located on the bottom fin portion 1071. In the extending direction perpendicular to the second fin portion 107, the bottom fin portion 1071 The width is greater than the width of the first fins 101; wherein, the depth of the second groove 102 is greater than the depth of the first groove 110; the isolation layer is located between the first groove 110 and the second groove In the groove 102 , the isolation layer covers at least the bottom fin portion 1071 .

The isolation layer is generally subjected to an annealing treatment, and the annealing treatment causes the Si-H bonds and Si-O bonds in the isolation layer to be broken, so that the material of the isolation layer becomes denser, but it is also easy to cause the isolation layer. The layer is deformed so that there is greater stress in the isolation layer. The second fin portion 107 includes a bottom fin portion 1071 and a top fin portion 1072 located on the bottom fin portion 1071, along the extending direction perpendicular to the second fin portion 107, and the bottom fin portion 1071 is wider than For the top fins 1072, compared with the case where the overall width of the second fins 107 is equal to the width of the top fins 1072, the embodiment of the present invention increases the width of the bottom fins 1071 to increase the rigidity of the second fins 107. larger, the ability of the second fins 107 to withstand the stress of the isolation layer is correspondingly larger, thereby reducing the probability of the second fins 107 being bent due to the stress of the isolation layer, which is beneficial to improve the performance and uniformity of the device performance sex.

In this embodiment, the first device is located in the first region I, the second device is located in the second region II, and the power of the second device is lower than that of the first device.

In this embodiment, the materials of the substrate, the first fins 101 and the second fins 107 are the same. In other embodiments, the materials of the substrate, the first fins 101 and the second fins 107 may also be different.

In this embodiment, the material of the substrate is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. In other embodiments, in order to improve the performance of the device, SiGe channel technology may also be used, that is, the material of the substrate includes silicon germanium, and the material of the corresponding subsequently formed fin and channel layer is SiGe. An interface layer can also be formed on the surface of the substrate, and the material of the interface layer is silicon oxide, silicon nitride or silicon oxynitride.

In this embodiment, the widths of the top fins 1072 and the first fins 101 are equal.

It should be noted that, the width difference between the top fin portion 1072 and the bottom fin portion 1071 should not be too large or too small. If the width difference between the top fin portion 1072 and the bottom fin portion 1071 is too large, the rigidity difference between the formed top fin portion 1072 and the bottom fin portion 1071 is too great. Insufficient rigidity; if the width difference between the top fins 1072 and the bottom fins 1071 is too small, the width of the bottom fins 1071 will be too small, the rigidity of the bottom fins 1071 will be insufficient, and the stress in the isolation layer will make the The bottom fin 1071 is curved, so that the uniformity of the performance of the semiconductor device is poor. In this embodiment, the width difference between the top fins 1072 and the bottom fins 1071 is 6 nm to 20 nm.

In this embodiment, the material of the isolation layer is an insulating material, and the isolation layer is used to achieve electrical isolation between the fins on the substrate.

In this embodiment, the material of the isolation layer is silicon oxide. In other embodiments, the material of the isolation layer may also be an insulating material such as silicon oxynitride, silicon nitride, silicon oxycarbonitride, or amorphous carbon.

The heat dissipation coefficient of the isolation layer is generally smaller than the heat dissipation coefficient of the second fins 107 . By making the width of the bottom fin portion 1071 larger than the width of the top fin portion 1072 , the volume of the bottom fin portion 1071 , the second fin portion 107 and the second fin portion 107 at the bottom of the second fin portion 107 are increased. The contact area of the two substrates correspondingly improves the heat dissipation performance of the device, improves the self-heating effect of the device, and further optimizes the electrical performance of the semiconductor structure.

The heat dissipation coefficient of the silicon is greater than the heat dissipation coefficient of the silicon oxide, and the bottom fin 1071 is wider than the top fin 1072 along the extending direction perpendicular to the second fin 107 , and the second fin 1071 is wider than the top fin 1072 . The volume of the second fins 107 is larger than that in the case where the overall width of the second fins is equal to the top fins 1072 , so the heat dissipation capability of the second fins 107 is stronger.

It should be noted that the isolation layer located in the first groove 110 is the second isolation layer 105 , and the isolation layer located in the second groove 102 is the second isolation layer 105 . The top surface of the second isolation layer 105 is lower than the top surface of the first isolation layer 112 . In other embodiments, the top surfaces of the isolation layer in the first groove 110 and the isolation layer in the second groove 102 are flush.

In this embodiment, the depth of the first groove 110 is greater than the depth of the second groove 102. Generally speaking, the thickness of the second isolation layer 105 in the first groove 110 is smaller than that of the second groove 102. The thickness of the first isolation layer 112 in the groove 102 . The first isolation layer 112 is thicker than the second isolation layer 105, so the source electrode and the drain electrode in the second region II are not easily penetrated, and the first isolation layer 112 can be better device isolation.

The semiconductor structure may be formed by the formation method described in the foregoing embodiments, or may be formed by other formation methods. For the specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be repeated in this embodiment.

Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention should be based on the scope defined by the claims.

Claims (20)

1. A method for forming a semiconductor structure, comprising: A substrate is provided, the substrate including a first region for forming a first device and a second region for forming a second device, the second device having a lower power than the the power of the first device; etching the substrate of the first region to form first fins and first grooves between the first fins; etching the base of the second region to form a second fin and a second groove between the second fins, the second fin includes a bottom fin and a top fin on the bottom fin In the extending direction perpendicular to the second fin, the width of the bottom fin is greater than the width of the top fin; wherein, the depth of the second groove is greater than the depth of the first groove depth; A first isolation layer is formed in the second groove, and the first isolation layer covers at least the bottom fin. 2. The method for forming a semiconductor structure according to claim 1, wherein: forming the second fin after forming the first fin; Alternatively, the first fins are formed after the second fins are formed. 3. The method for forming a semiconductor structure according to claim 1, wherein the step of forming the first fin portion and the second fin portion comprises: etching the substrates of the first region and the second region to form a first substrate and an initial fin on the first substrate, wherein the initial fin on the first region serves as the first fin; forming a capping layer on the initial fin sidewalls of the second region; Using the cap layer as a mask, the first substrate exposed by the initial fins in the second region is etched, and the remaining first substrate after etching is used as a second substrate, located in the The protrusions on the second substrate serve as the second fins; After forming the second fin, the capping layer is removed. 4. The method for forming a semiconductor structure according to claim 3, wherein the step of forming the capping layer comprises: forming a capping material layer conformally covering the initial fins; In the second region, the capping material layer on the top of the initial fin is removed, and the capping material layer on the sidewall of the initial fin in the second region is retained as the capping layer. 5 . The method for forming a semiconductor structure according to claim 4 , wherein after the capping material layer is formed and before removing the capping material layer on the top of the initial fin, the method further comprises: in the first A protective layer is formed on the capping material layer of the area; After removing the capping layer, the protective layer is removed. 6 . The method for forming a semiconductor structure according to claim 3 , wherein after forming the initial fins and before forming the cap layer, the method further comprises: on the first substrate exposed by the initial fins. 7 . forming a second isolation layer; In the step of forming a first isolation layer in the second groove, the top of the first isolation layer is lower than the top of the second isolation layer. 7 . The method of claim 1 , wherein in the step of forming a first isolation layer, the first isolation layer is further formed in the first groove. 8 . 8 . The method for forming a semiconductor structure according to claim 3 , wherein the material of the capping layer is one or more of SiN, SiCN, SiOCN or SiBCN. 9 . 9 . The method for forming a semiconductor structure according to claim 4 , wherein the capping material layer is formed by a chemical vapor deposition process or an atomic layer deposition process. 10 . 10 . The method for forming a semiconductor structure according to claim 3 , wherein the cap layer has a thickness of 3 nanometers to 10 nanometers. 11 . 11 . The method for forming a semiconductor structure according to claim 3 , wherein the capping layer is removed by a wet etching process. 12 . 12 . The method for forming a semiconductor structure according to claim 11 , wherein the capping layer is removed by using a phosphoric acid solution. 13 . 13 . The method for forming a semiconductor structure according to claim 5 , wherein the protective layer is made of an organic material. 14 . 14 . The method for forming a semiconductor structure according to claim 5 , wherein the material of the protective layer is BARC material, ODL material, photoresist, DARC material, DUO material or APF material. 15 . 15. The method of claim 1, wherein the step of forming the first fin and the second fin comprises: etching the base of the second region to form a second substrate and an initial fin protruding from the second substrate; forming a protective layer on the second substrate exposed by the initial fin, the protective layer covering part of the sidewall of the initial fin; performing oxidation treatment on the sidewalls of the initial fins exposed by the protective layer, converting a partial width of the initial fins into an oxide layer, and the remaining initial fins as the second fins; removing the oxide layer and protective layer; After removing the oxide layer and the protective layer, a filling layer is formed on the exposed second substrate of the second fin, and the filling layer covers the sidewall of the second fin; After the filling layer is formed, the base of the first region is etched to form a first substrate and a first fin protruding from the first substrate. 16. The method for forming a semiconductor structure according to claim 15, wherein the oxidation treatment process is a thermal oxidation process. 17. A semiconductor structure, characterized in that it comprises: a substrate, the substrate includes a first region and a second region, the first region is used to form a first device, the second region is used to form a second device, the power of the second device is lower than the the power of the first device; a first fin, located on the substrate of the first area, and the area between the first fins is a first groove; The second fin is located on the substrate of the second area, the area between the second fins is a second groove, the second fin includes a bottom fin and is located on the bottom fin The top fin portion, in the extending direction perpendicular to the second fin portion, the width of the bottom fin portion is greater than the width of the top fin portion; Wherein, the depth of the second groove is greater than the depth of the first groove; An isolation layer is located in the first groove and the second groove, and the isolation layer covers at least the bottom fin. 18. The semiconductor structure of claim 17, wherein the top fin and the first fin have the same width. 19. The semiconductor structure of claim 17, wherein the top surface of the isolation layer in the second groove is lower than the top surface of the isolation layer in the first groove; Alternatively, the top surfaces of the isolation layer in the first groove and the isolation layer in the second groove are flush. 20 . The semiconductor structure of claim 17 , wherein the difference in width between the top fin and the bottom fin is 6 nm to 20 nm. 21 .

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