CN110875186B - Semiconductor structure and forming method thereof - Google Patents

Abstract

The invention provides a semiconductor structure and a forming method thereof, wherein the forming method of the semiconductor structure comprises the following steps: providing a substrate, wherein the substrate comprises a first area and a second area, the first area is used for forming a first device, the second area is used for forming a second device, and the power of the second device is higher than that of the first device; etching a substrate of the first region to form a first substrate and a plurality of first fin parts separated from the first substrate, wherein first grooves are formed between adjacent first fin parts; etching the substrate of the second region to form a second substrate and a plurality of second fin parts separated from the second substrate, wherein second grooves are formed between adjacent second fin parts; the depth of the second groove is smaller than the depth of the first groove. In the embodiment of the invention, the second substrate in the second device is closer to the external space than the first substrate in the first device, and the depth-to-width ratio of the second groove in the second device is smaller than that of the first groove in the first device, so that the heat dissipation performance of the second device is better than that of the first device.

Description

Semiconductor structures and methods of forming them

technical field

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a forming method thereof.

Background technique

In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, metal-oxide-semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor , MOSFET) channel length has been shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the ability of the gate structure to control the channel becomes worse, and the gate voltage pinches off the channel. The channel becomes more and more difficult, making subthreshold leakage (subthreshold leakage), the so-called short-channel effect (SCE: short-channel effects) more likely to occur.

Therefore, in order to better adapt to the reduction of the feature size, the semiconductor process gradually begins to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as Fin Field Effect Transistors (FinFETs). In FinFET, the gate structure can control the ultra-thin body (fin) from at least two sides. Compared with the planar MOSFET, the gate structure has a stronger ability to control the channel and can well suppress the short channel effect; Moreover, compared with other devices, FinFET has better compatibility with existing integrated circuit manufacturing.

In the FinFET device, in order to enhance the control of the channel, the width of the Fin is getting smaller and smaller, and in order to obtain better device performance, a silicon germanium channel is used.

Contents of the invention

The invention provides a semiconductor structure and a forming method thereof, which optimize the electrical performance of the semiconductor structure.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a first region and a second region, the first region is used to form a first device, and the second region For forming a second device, the power of the second device is higher than the power of the first device; etching the base of the first region to form a first substrate and a plurality of devices separated from the first substrate The first fin on the first fin, the first groove is between the adjacent first fins; the base of the second region is etched to form a second substrate and a plurality of discrete fins on the second substrate. The second fin portion is adjacent to the second fin portion and there is a second groove; the depth of the second groove is smaller than the depth of the first groove.

Correspondingly, the present invention also provides a semiconductor structure, including: a substrate, the substrate includes a second region and a first region, the second region is used to form a second device, and the first region is used to form a first device, the power of the second device is higher than that of the first device; the first region includes a first substrate and a plurality of first fins separated on the first substrate, adjacent to the first There is a first groove between one fin; the second region includes a second substrate and a plurality of second fins separated on the second substrate, and a second groove is formed between adjacent second fins. A groove; the depth of the second groove is smaller than the depth of the first groove.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

In an embodiment of the present invention, a substrate is provided, and the substrate includes a first region and a second region, the first region is used to form a first device, the second region is used to form a second device, and the second device The power is higher than the power of the first device; a first fin and a first groove between adjacent first fins are formed in the first region; a second fin is formed in the second region portion and a second groove located between adjacent second fins; the depth of the second groove is smaller than the depth of the first groove, and the second substrate in the second device is compared to the second substrate The first substrate in the first device is closer to the external space, the aspect ratio of the second groove in the second device is smaller than the aspect ratio of the first groove in the first device, therefore, the second The heat dissipation performance of the device is better than the heat dissipation performance of the first device, so that even if the power of the second device is higher, the heat dissipation performance is better, thereby ensuring that the entire semiconductor structure (the first device and the second device) is not easy to generate self-dissipation. Thermal effects, thereby optimizing the performance of the semiconductor structure.

In an optional solution, a first isolation layer is formed in the first groove, a second isolation layer is formed in the second groove, and the thickness of the second isolation layer is smaller than the thickness of the first isolation layer , the density of the second isolation layer is greater than the density of the first isolation layer, and in the subsequent process, the etching rate of the second isolation layer is lower than the etching rate of the first isolation layer, Therefore, the second isolation layer is not easily damaged, and the devices in the second groove are not prone to electric leakage.

Description of drawings

Fig. 1 is a structural schematic diagram in a method for forming a semiconductor structure;

2 to 11 are structural schematic diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention;

12 to 17 are structural diagrams corresponding to each step in another embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention.

Detailed ways

It can be seen from the background technology that in FinFET devices, in order to enhance the control of the channel, the width of Fin is getting smaller and smaller, and in order to obtain better device performance, FinFET devices use silicon germanium channels, now combined with a semiconductor structure The formation method analyzes the reason why the electrical performance of the semiconductor structure needs to be improved.

Referring to FIG. 1 , there is shown a schematic structural view of a method for forming a semiconductor structure.

Referring to FIG. 1, the substrate includes a first region I and a second region II, the first region I is used to form a first device, the second region II is used to form a second device, and the second device's The power is higher than the power of the first device. The base is etched to form a substrate 1 and a plurality of discrete fins 2 on the substrate 1 , and an isolation layer 3 is formed on the substrate 1 between the fins 2 .

In order to enhance the control of the channel, the width of Fin is getting smaller and smaller, and more Fins are formed per unit area, which makes it difficult for the heat generated by FinFET devices to dissipate quickly; on the other hand, in order to obtain better device performance, Using the silicon germanium channel, the heating power of the germanium silicide channel is higher than that of the conventional silicon channel.

Because the surface heights of the substrate 1 in the first region I and the second region II tend to be the same, that is to say, the structures of the devices in the first region I and the second region II are the same, the first device Same heat dissipation capability as the second device. However, the power of the second device is higher than that of the first device, and the heat generation of the second device is higher than that of the first device, and the heat in the second device cannot be removed in time so that the device performance degradation.

In order to solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a first region and a second region, the first region is used to form a first device, the The second region is used to form a second device, and the power of the second device is higher than that of the first device; the base of the first region is etched to form the first substrate and multiple First fins on the first substrate, and first grooves between adjacent first fins; etch the base of the second region to form a second substrate and a plurality of fins separated from the second substrate. The second fins on the bottom have second grooves between adjacent second fins; the depth of the second grooves is smaller than the depth of the first grooves.

In an embodiment of the present invention, a substrate is provided, and the substrate includes a first region and a second region, the first region is used to form a first device, the second region is used to form a second device, and the second device The power is higher than the power of the first device; a first fin and a first groove between adjacent first fins are formed in the first region; a second fin is formed in the second region portion and a second groove located between adjacent second fins; the depth of the second groove is smaller than the depth of the first groove, and the second substrate in the second device is compared to the second substrate The first substrate in the first device is closer to the external space, the aspect ratio of the second groove in the second device is smaller than the aspect ratio of the first groove in the first device, therefore, the second The heat dissipation performance of the device is better than the heat dissipation performance of the first device, so that even if the power of the second device is higher, the heat dissipation performance is better, thereby ensuring that the entire semiconductor structure (the first device and the second device) is not easy to generate self-dissipation. Thermal effects, thereby optimizing the performance of the semiconductor structure.

In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, specific embodiments of the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

2 to 11 are structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention.

Referring to FIG. 2 , a substrate 100 is provided, the substrate 100 includes a first region I and a second region II, the first region I is used to form a first device, and the second region II is used to form a second device, so The power of the second device is higher than the power of the first device.

A substrate 100 is provided, and the substrate 100 provides a process platform for subsequent formation of the first groove and the second groove.

In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Semiconductor devices such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors or inductors can also be formed in the substrate 100 . An interface layer can also be formed on the surface of the substrate 100, and the material of the interface layer is silicon oxide, silicon nitride, or silicon oxynitride.

In this embodiment, the first area I and the second area II are adjacent areas. In other embodiments, the first region I and the second region II may also be isolated from each other.

In this embodiment, the first device is a PMOS device, and the second device is an NMOS device. In other embodiments, the first device may also be an NMOS device, and the second device may be a PMOS device.

Referring to FIG. 3 to FIG. 7, the base 100 of the second region II is etched to form a second substrate 200 and a plurality of second fins separated on the second substrate 200, adjacent to the second Between the fins is a second groove 202 . The second groove 202 is used to provide space for filling the isolation layer in the subsequent process.

That is to say, in this embodiment, the base of the second region II is first etched to form the second fin and the second groove 202; after the formation of the second fin, the base of the first region I is etched. , forming the first fin and the first groove.

As shown in FIG. 3 , the step of forming the second fin and the second groove includes: forming a mask material layer 110 covering the substrate 100, forming a plurality of discrete cores on the mask material layer 110 Layer 120. The mask material layer 110 is used to prepare for a subsequent mask layer. The core layer 120 is used to prepare for subsequent formation of mask sidewalls covering the sidewalls of the core layer 120 .

In this embodiment, the mask material layer 110 is a laminated structure, and the mask material layer 110 includes a base protection material layer 1102, a hard mask material layer 1101 formed on the base protection material layer 1102, and a hard mask material layer formed on the base protection material layer 1102. A high performance metal oxide material layer 1103 on the hard mask material layer 1101 .

The substrate protection material layer 1102 is used to reduce the influence of the stress of the hard mask material layer 1101 on the substrate 100 . The high-performance metal oxide material layer 1103 is used to protect the hard mask material layer 1101, and when the core layer 120 and the mask spacer 130 are removed in a subsequent process, the impact on the hard mask material layer can be reduced. 1101 caused damage.

In this embodiment, the material of the base protection material layer 1102 is silicon oxide.

In this embodiment, the material of the hard mask material layer 1101 is silicon nitride. In other embodiments, the material of the hard mask material layer 1101 may also be silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride.

In this embodiment, the material of the high-performance metal oxide material layer 1103 is silicon oxide. In other embodiments, the material of the high-performance metal oxide material layer 1103 may also be silicon nitride or silicon oxynitride.

In this embodiment, the material of the core layer 120 is polysilicon. In other embodiments, the material of the core layer 120 may also be amorphous carbon, ODL material, DARC material or BARC material.

The etching rate of the core layer 120 is greater than that of the mask material layer 110 , and the damage to the mask material layer 110 can be reduced when the core layer 120 is removed.

As shown in FIG. 4 , mask sidewalls 130 covering sidewalls of the core layer 120 are formed. In a subsequent process, the material of the substrate 100 is etched using the mask spacer 130 as a mask to form a second groove.

The material of the mask sidewall 130 is different from the material of the high-performance metal oxide material layer 1103, and the material of the mask sidewall 130 is silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, Silicon carbonitride, silicon oxycarbonitride or boron nitride. In this embodiment, the material of the mask spacer 130 is silicon nitride.

As shown in FIG. 5 , a mask protection layer 140 is formed on the mask material layer 110 exposed by the mask spacer 130 and the core layer 120 . The mask protection layer 140 and the core layer 120 are used to provide a process platform for the subsequently formed shielding layer.

In this embodiment, the material of the mask protection layer 140 is bottom anti-reflection coating.

As shown in FIG. 6 , after the mask protection layer 140 is formed, a shielding layer 150 covering the first region I is formed. The shielding layer 150 is used to etch the material of the substrate 100 in the second region II in a subsequent process, so as to avoid etching the substrate material in the first region I when forming the second groove.

In this embodiment, the first region I includes the mask protection layer 140 and the core layer 120, and the shielding layer 150 covers the mask sidewall 130, the mask protection layer 140 and on the core layer 120 . In other embodiments, there is only a mask protection layer or a core layer in the first region I.

In this embodiment, the material of the shielding layer 150 is different from that of the mask protection layer 140 and the core layer 120, and the material of the shielding layer 150 is amorphous carbon. In other embodiments, the shielding layer The material can also be ODL material or DARC material.

As shown in FIG. 7 , in the second region II, the material of the substrate 100 is etched using the mask spacer 130 as a mask to form a second groove 202 .

In this embodiment, in the second region II, there is only one core layer 120 (as shown in FIG. 6 ), and in the process of forming the second groove 202, the core layer 120 is removed. In other embodiments In the process, the mask protective layer may also be removed, or the core layer and the mask protective layer may be removed at the same time to form the second groove.

In this embodiment, the first region I and the second region II are adjacent regions. A second groove 202 is shown in FIG. 7 , and the second fin is not shown. The second fin is in It is formed when the first groove is formed in the subsequent process. The bottom surface of the second groove 202 is the second substrate 200. In other embodiments, a plurality of second grooves are formed on the second substrate, and a first groove is formed between the second grooves. Two fins. In addition to the second grooves between the second fins, the second grooves on both sides of the second fins are also second grooves.

It should be noted that the depth of the second groove 202 cannot be too deep or too shallow. If the second groove 202 is too deep, the distance between the second groove 202 and the external space will be too far. If the aspect ratio of the second groove 202 is too large, it is not conducive to heat dissipation. If the second groove 202 is too shallow, the process space reserved for the isolation layer in the later stage will become smaller, and the thickness of the isolation layer will be thinner, which is not conducive to reducing the heat dissipation. Device leakage problems. Correspondingly, the depth of the second groove 202 is 600 to 900 angstroms.

Referring to FIGS. 8 to 10, the base 100 of the first region I is etched to form a first substrate 300 and a plurality of first fins 301 separated on the first substrate 300, adjacent to the first fins 301. Between the first fins 301 is a first groove 302 ; the depth of the second groove 202 (as shown in FIG. 7 ) is smaller than the depth of the first groove 302 . The first groove 302 is used to provide space for filling the isolation layer in the subsequent process.

As shown in FIG. 8 to FIG. 9, the step of forming the first fin 301 and the first groove 302 includes: forming a groove protection layer 203 in the second groove 202; In region I, the shielding layer 150 is removed, and after removing the shielding layer 150, the core layer 120 and the mask protection layer 140 are removed; the material of the substrate 100 is etched using the mask sidewall 130 as a mask to form The first groove 302 .

In this embodiment, the material of the groove protection layer 203 is bottom anti-reflective coating, silicon oxide, silicon nitride or silicon oxynitride.

It should also be noted that the depth of the first groove 302 cannot be too deep or too shallow, if the first groove 302 is too deep, the distance between the first groove 302 and the external space will be too far , so that the aspect ratio of the first groove 302 is too large, which is not conducive to heat dissipation. If the first groove 302 is too shallow, the process space reserved for the isolation layer in the later stage becomes smaller, and the thickness of the isolation layer is thinner. Therefore, it is not conducive to reducing the leakage problem of the device. Correspondingly, the depth of the first groove 302 is 1000 to 1500 angstroms.

In this embodiment, using the mask sidewall 130 as a mask to etch the material of the substrate 100, the step of forming the first groove 302 includes: using the mask sidewall 130 as a mask to etch the mask material layer 110 to form a mask layer 160 ; the mask spacer 130 is removed, and the substrate 100 is etched using the mask layer 160 as a mask to form the first groove 302 . Because the mask material layer 110 is a stacked structure, correspondingly, the mask layer 160 is also a stacked structure, and the mask layer 160 includes a base protection layer 1602 , a layer formed on the base protection layer 1602 A hard mask layer 1601 and a high-performance metal oxide layer 1603 formed on the hard mask layer 1601 .

In this embodiment, the bottom surface of the first groove 302 is the first substrate 300, on which the first fins 301 are formed, and between the adjacent first fins 301 is the first groove 302 . The depth of the second groove 202 is smaller than the depth of the first groove 302, and the second substrate 200 in the second device is closer to the outside than the first substrate 300 in the first device space, the aspect ratio of the second groove 202 in the second device is greater than the aspect ratio of the first groove 302 in the first device, therefore, the heat dissipation performance of the second device is better than that of the first device .

In this embodiment, in the first region I, besides the first grooves 302 between the first fins 301 , the first grooves 302 on both sides of the first fins 301 are also the first grooves 302 . In other embodiments, the first groove only exists between the first fins.

In this embodiment, the first region I and the second region II are adjacent regions, and the material of the substrate 100 is etched using the mask spacer 130 as a mask, and the step of forming the first groove 302 further includes : In the second region II, a second fin 201 is formed at the junction of the first region I and the second region II. In other embodiments, the first region I and the second region II are not adjacent regions, and in the step of etching the mask material layer and the base material to form the first groove using the mask layer as a mask No second fin is formed.

The first area I and the second area II are adjacent areas. In this embodiment, the junction of the first area I and the second area II is exactly at the position of the side wall of the second groove 202 . In other embodiments, the junction of the first region I and the second region II may be a base material of any height.

As shown in FIG. 10 , after the first groove 302 and the second groove 202 are formed, part of the first fin 301 and the second fin 201 are dummy fins 303 , and the semiconductor The forming method of the structure further includes: removing the dummy fin 303 after forming the second fin 201 and the first fin 301 and before forming the isolation layer.

Referring to FIG. 11 , the method for forming the semiconductor structure includes: after forming the first groove 302 (as shown in FIG. 9 ) and the second groove 202 (as shown in FIG. 7 ), in the first An isolation layer 204 is formed in the first groove 302 and the second groove 202 . The isolation layer 204 is used to isolate adjacent devices.

The step of forming the isolation layer 204 in the first groove 302 and the second groove 202 includes: forming a first isolation material layer covering the first groove 302 and a second isolation material layer covering the second groove 202 , performing mechanical planarization treatment on the first isolation material layer and the second isolation material layer at the same time; after performing mechanical planarization treatment on the first isolation material layer and the second isolation material layer, etch back part of the material thickness , the remaining first isolation material layer and the remaining second isolation material layer after the etching back process are used as the isolation layer 204 .

The step of forming the isolation layer 204 in the first groove 302 and the second groove 202 includes: forming a first isolation layer 206 in the first groove 302, forming a first isolation layer in the second groove 202 Two isolation layers 205 , the density of the second isolation layer 205 is higher than that of the first isolation layer 206 . The depth of the second groove 202 is smaller than the depth of the first groove 302, therefore, the thickness of the second isolation layer 205 is smaller than the thickness of the first isolation layer 206, and the thickness of the second isolation layer 205 The density is greater than the density of the first isolation layer 206, and in the subsequent process, the etching rate of the second isolation layer 205 is lower than the etching rate of the first isolation layer 206, therefore, the second isolation layer 205 The second isolation layer 205 is not easily damaged, and the devices in the second groove 202 are not prone to electric leakage.

In this embodiment, the material of the first isolation layer 206 is silicon oxide, and the material of the second isolation layer 205 is silicon nitride.

The method for forming the semiconductor structure includes: after forming the first groove 302 , removing the groove protection layer 203 (as shown in FIG. 10 ). When the material of the groove protection layer 203 (as shown in FIG. 10 ) is silicon oxide, after the first groove 302 is formed, the groove protection layer 203 is etched back to form the second isolation layer 205 . When the material of the groove protective layer 203 is bottom anti-reflective coating, silicon nitride or silicon oxynitride, after the first groove 302 is formed, the groove protective layer 203 is removed, and then the groove covering layer 203 is formed. The silicon oxide layer of the second groove 202 is etched back, and then the silicon oxide layer is etched back to obtain the second isolation layer 205 .

12 to 17 are structural diagrams corresponding to each step in another embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention.

The similarities between this embodiment and the previous embodiment will not be repeated, and the difference from the previous embodiment lies in the sequence of forming the first groove and the second groove. Specifically, in this embodiment, the base of the first region is first etched to form the first fin and the first groove; after the formation of the first fin, the base of the second region is etched to form The second fin and the second groove.

12 to 13, the base 400 of the first region I is etched to form a first substrate 500 and a plurality of first fins 501 separated on the first substrate 500, adjacent to the first fin 500. Between the fins 501 is a first groove 502 ; the first groove 502 is used to provide a space for filling an isolation layer in a subsequent process.

As shown in FIG. 12 , the step of forming the first fin and the first groove includes: forming a mask material layer 410 covering the substrate 400, forming a plurality of discrete cores on the mask material layer 410 layer 420; forming a mask sidewall 430 covering the sidewall of the core layer 420; forming a mask protection layer 440 on the mask material layer 410 exposed by the mask sidewall 430 and the core layer 420; After the mask protection layer 440 is formed, a shielding layer 450 covering the second region II is formed. The mask material layer 410 is used to prepare for a subsequent mask layer. The core layer 420 is used to prepare for subsequent formation of mask sidewalls 430 covering the sidewalls of the core layer 420 .

In this embodiment, the mask material layer 410 is a laminated structure, and the mask material layer 410 includes a base protection material layer 4102, a hard mask material layer 4101 formed on the base protection material layer 4102, and a hard mask material layer formed on the base protection material layer 4102. A high performance metal oxide material layer 4103 on the hard mask material layer 4101 .

In this embodiment, the material of the core layer 420 is polysilicon. In other embodiments, the material of the core layer 420 may also be amorphous carbon, ODL material, DARC material or BARC material.

The etching rate of the core layer 420 is greater than that of the mask material layer 410 , and the damage to the mask material layer 410 can be reduced when the core layer 420 is removed.

The material of the mask sidewall 430 is different from that of the high-performance metal oxide material layer 4103, and the material of the mask sidewall 430 is silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, Silicon carbonitride, silicon oxycarbonitride or boron nitride. In this embodiment, the material of the mask spacer 430 is silicon nitride.

In this embodiment, the first region I includes the core layer 420 . The shielding layer 450 covers the first region I, that is to say, the shielding layer 450 covers the core layer 420 .

In this embodiment, the material of the mask protection layer 440 is bottom anti-reflection coating.

In this embodiment, the material of the shielding layer 450 is different from that of the mask protection layer 440 and the core layer 420, and the material of the shielding layer 450 is amorphous carbon. In other embodiments, the shielding layer The material can also be ODL material or DARC material.

As shown in FIG. 13 , in the first region I, the core layer 420 and the mask protection layer 440 are removed, and the material of the substrate 400 is etched using the mask spacer 430 as a mask to form a first groove 502 .

In this embodiment, in the process of forming the first groove 502, the core layer 420 and the mask protection layer 440 are removed. In other embodiments, the formation of the first groove may also be the removal of the mask protection layer or the core layer.

In this embodiment, the bottom surface of the first groove 502 is the first substrate 500, except that the first groove 502 between the first fins 501 is the first groove 502, the two sides of the first fin 501 are also is the first groove 502 , and the bottom surface of the first groove 502 is the first substrate 500 . In other embodiments, the first region I and the second region II are adjacent regions, a first groove is formed on the first substrate, and the first fin on the first substrate It is formed when the base material is etched to form the second groove in the subsequent process.

It should be noted that the depth of the first groove 502 cannot be too deep or too shallow. If the first groove 502 is too deep, the distance between the first groove 502 and the external space will be too far. Making the aspect ratio of the first groove 502 too large is not conducive to heat dissipation. If the first groove 502 is too shallow, the process space reserved for the isolation layer in the later stage becomes smaller, and the thickness of the isolation layer is thinner, which is not conducive to heat dissipation. Reduce device leakage problems. Correspondingly, the depth of the first groove 502 is 1000 to 1500 angstroms.

Referring to FIGS. 14 to 16, the base 400 of the second region II (as shown in FIG. 12 ) is etched to form a second substrate 600 and a plurality of second fins separated on the second substrate 600 601 , between adjacent second fins 601 is a second groove 602 ; the depth of the second groove 602 is smaller than the depth of the first groove 502 (as shown in FIG. 13 ). The second groove 602 is used to provide space for filling the isolation layer in the subsequent process.

As shown in FIG. 14 to FIG. 15 , the step of forming the second fin 601 and the second groove 602 includes: forming a groove protection layer 503 in the first groove 502, and forming a groove protection layer 503 in the second region II , remove the shielding layer 450, after removing the shielding layer 450, remove the core layer 420 and the mask spacer 430, and use the mask spacer 430 (as shown in FIG. 14 ) as a mask to etch The material of the base 400 forms the second groove 602 .

In this embodiment, after removing the shielding layer 450 (as shown in FIG. 14 ), the core layer 420 is removed to prepare for subsequent etching of the substrate 400 to form the second groove 602 . In other embodiments, the mask protection layer may be removed, or the mask protection layer or the core layer may be removed at the same time, in preparation for subsequent etching of the substrate to form the second groove.

In this embodiment, the step of using the mask sidewall 430 (as shown in FIG. 14 ) as a mask to etch the material of the substrate 400 to form the second groove 602 includes: using the mask sidewall 430 as a mask Etching the mask material layer 410 to form a mask layer 460; using the mask spacer 430 as a mask to etch the material of the substrate 400 to form a second groove 602; forming the second groove 602 Afterwards, the mask spacer 430 is removed.

In this embodiment, the mask material layer 410 includes a base protection material layer 4102, a hard mask material layer 4101 formed on the base protection material layer 4102, and a high layer formed on the hard mask material layer 4101. Performance metal oxide material layer 4103. Correspondingly, the formed mask layer 460 includes a base protection layer 4602, a hard mask layer 4601 formed on the base protection layer 4602, and a high-performance metal oxide layer 4603 formed on the hard mask layer 4601 .

In this embodiment, the second grooves 602 are formed between the second fins 601 . In other embodiments, there are second grooves between the second fins, and second grooves on both sides of the second fins.

In this embodiment, the material of the groove protection layer 503 is bottom anti-reflective coating, silicon oxide, silicon nitride or silicon oxynitride.

It should also be noted that the depth of the second groove 602 cannot be too deep or too shallow, if the second groove 602 is too deep, the distance between the second groove 602 and the external space will be too far , so that the aspect ratio of the second groove 602 is too large, which is not conducive to heat dissipation. If the second groove 602 is too shallow, the process space reserved for the isolation layer in the later stage becomes smaller, and the thickness of the isolation layer is thinner, so that the It is beneficial to reduce the leakage problem of the device. Correspondingly, the depth of the second groove 602 is 600 to 900 angstroms.

In this embodiment, the bottom surface of the second groove 602 is the second substrate 600, on which the second fins 601 are formed, and between the adjacent second fins 601 is the second groove 602 . The depth of the second groove 602 is smaller than the depth of the first groove 502 (as shown in FIG. 13 ), and the second substrate 600 in the second device is compared to the first groove in the first device. A substrate 500 is closer to the external space, therefore, the heat dissipation performance of the second device is better than that of the first device.

As shown in FIG. 16, after forming the first groove 502 (as shown in FIG. 13) and the second groove 602, part of the first fin 501 and the second fin 601 are dummy. Fin 603 , the method for forming the semiconductor structure further includes: after forming the second fin 601 and the first fin 501 and before forming the isolation layer, removing the dummy fin 603 .

In this embodiment, the method for forming the semiconductor structure includes: removing the groove protection layer 503 after forming the first groove 502 and the second groove 602 and before removing the dummy fins 603 .

Referring to FIG. 17 , the method for forming the semiconductor structure includes: after forming the first groove 502 (as shown in FIG. 16 ) and the second groove 602 (as shown in FIG. 16 ), in the first An isolation layer 504 is formed in the first groove 502 and the second groove 602 .

The step of forming the isolation layer 504 in the first groove 502 and the second groove 602 refers to an embodiment, and will not be repeated here.

The method for forming the semiconductor structure further includes: after forming the first groove 502 , removing the groove protection layer 503 , the specific forming method is the same as that of the previous embodiment, and will not be repeated here.

The invention also provides a semiconductor structure. Referring to FIG. 11 , a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown.

Referring to FIG. 11 , the semiconductor structure includes a substrate, and the substrate includes a second region II and a first region I, the second region II is used to form a second device, and the first region I is used to form a first device, so The power of the second device II is higher than that of the first device; the first region I includes a first substrate 300 and a plurality of first fins 301 separated on the first substrate 300, which are relatively There is a first groove 302 adjacent to the first fin 301; the second region II includes the second substrate 200 and a plurality of second fins 201 separated on the second substrate 200, adjacent to the first fin 301. Between the two fins 201 is a second groove 202 ; the depth of the second groove 202 is smaller than the depth of the first groove 302 .

In this embodiment, the material of the substrate is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Semiconductor devices, such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors, or inductors, can also be formed in the substrate. An interface layer can also be formed on the surface of the substrate, and the material of the interface layer is silicon oxide, silicon nitride, or silicon oxynitride.

In this embodiment, the first area I and the second area II are adjacent areas. In other embodiments, the first region I and the second region II may also be isolated from each other. In this embodiment, the junction of the first region I and the second region II is just at the position of the sidewall of the second groove 202 . In other embodiments, the junction of the first region I and the second region II may be a base material of any height.

In this embodiment, the first device is a PMOS device, and the second device is an NMOS device. In other embodiments, the first device is an NMOS device, and the second device is a PMOS device.

In this embodiment, the depth of the second groove 202 cannot be too deep or too shallow. If the second groove 202 is too deep, the distance between the second groove 202 and the external space will be too far. If the aspect ratio of the second groove 202 is too large, it is not conducive to heat dissipation. If the second groove 202 is too shallow, the process space reserved for the isolation layer in the later stage will be reduced, which is not conducive to reducing the leakage problem of the device. Correspondingly, the depth of the second groove 202 is 600 to 900 angstroms.

In this embodiment, the depth of the first groove 302 cannot be too deep or too shallow. If the first groove 302 is too deep, the distance between the first groove 302 and the external space will be too far. Making the aspect ratio of the first groove 302 too large is not conducive to heat dissipation, if the first groove 302 is too shallow, the process space reserved for the isolation layer in the later stage becomes smaller, and the thickness of the isolation layer is thinner, so that It is not conducive to reducing the leakage problem of the device. Correspondingly, the depth of the first groove 302 is 1000 to 1500 angstroms.

In this embodiment, an isolation layer 204 is formed in the first groove 302 and the second groove 202 .

Specifically, the isolation layer 204 located in the second groove 202 is the second isolation layer 205, the isolation layer located in the first groove 302 is the first isolation layer 206, and the second isolation layer The density of the isolation layer 205 is higher than that of the first isolation layer 206 . The depth of the second groove 202 is smaller than the depth of the first groove 302 , therefore, the thickness of the second isolation layer 205 is smaller than the thickness of the first isolation layer 206 . The density of the second isolation layer 205 is greater than the density of the first isolation layer 206, and the etching rate of the second isolation layer 205 is lower than that of the first isolation layer 206 during the formation of the semiconductor structure. The etching rate is high, the second isolation layer 205 is not easily damaged, and the devices in the second groove 202 are not prone to leakage problems.

Specifically, the material of the first isolation layer 206 is silicon oxide, and the material of the second isolation layer 205 is silicon nitride.

In this embodiment, the depth of the second groove 202 is smaller than the depth of the first groove 302, and the second substrate 200 in the second device is compared with the first substrate in the first device. The bottom 300 is closer to the external space, and the aspect ratio of the second groove 202 in the second device is smaller than the aspect ratio of the first groove 302 in the first device. Therefore, the heat dissipation performance of the second device is better than that of the first device. Describe the heat dissipation performance of the first device.

The semiconductor structure described in this embodiment may be formed using the forming method described in the foregoing embodiments, or may be formed using other forming methods. In this embodiment, for the specific description of the semiconductor structure, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated in this embodiment.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. A method for forming a semiconductor structure, comprising: A substrate is provided, the substrate includes a first region and a second region, the first region is used to form a first device, the second region is used to form a second device, and the power of the second device is higher than that of the the power of the first device; Etching the base of the first region to form a first substrate and a plurality of first fins separated on the first substrate, with first grooves between adjacent first fins; Etching the base of the second region to form a second substrate and a plurality of second fins separated on the second substrate, with second grooves between adjacent second fins; The depth of the second groove is smaller than the depth of the first groove. 2 . The method for forming a semiconductor structure according to claim 1 , wherein the depth of the second groove is 600 to 900 angstroms. 3 . The method for forming a semiconductor structure according to claim 1 , wherein the depth of the first groove is 1000 to 1500 angstroms. 4. The method for forming a semiconductor structure according to claim 1, wherein the base of the second region is first etched to form a second fin and the second groove; after forming the second fin, Etching the base of the first region to form the first fin and the first groove. 5. The formation method of semiconductor structure as claimed in claim 4, is characterized in that, The step of forming the second fin and the second groove includes: forming a layer of masking material overlying the substrate, forming a plurality of discrete core layers on the layer of masking material; forming mask sidewalls covering sidewalls of the core layer; forming a mask protection layer on the mask material layer exposed by the mask sidewall and the core layer; After forming the mask protective layer, forming a shielding layer covering the first region; In the second region, the core layer is removed, and the base material is etched using the mask sidewall as a mask to form a second groove; The step of forming the first fin and the first groove includes: forming a groove protection layer in the second groove; In the first region, removing the blocking layer; After removing the shielding layer, removing the core layer and mask protection layer; Etching the base material by using the mask sidewall as a mask to form the first groove; The method for forming the semiconductor structure includes: after forming the first groove, removing the groove protection layer. 6. The method for forming a semiconductor structure according to claim 1, wherein the base of the first region is first etched to form a first fin and the first groove; after forming the first fin, Etching the base of the second region to form the second fin and the second groove. 7. The formation method of semiconductor structure as claimed in claim 6, is characterized in that, The step of forming the first fin and the first groove includes: forming a layer of masking material overlying the substrate, forming a plurality of discrete core layers on the layer of masking material; forming mask sidewalls covering sidewalls of the core layer; forming a mask protection layer on the mask material layer exposed by the mask sidewall and the core layer; after forming the mask protection layer, forming a shielding layer covering the second region; In the first region, removing the core layer and mask protection layer, etching the base material using the mask sidewall as a mask, to form a first groove; The step of forming the second fin and the second groove includes: forming a groove protection layer in the first groove; In the second region, removing the masking layer; After removing the shielding layer, removing the core layer and mask protection layer; Etching the base material by using the mask sidewall as a mask to form the second groove; The method for forming the semiconductor structure includes: after forming the second groove, removing the groove protection layer. 8. The method for forming a semiconductor structure according to claim 1, wherein the method for forming a semiconductor structure comprises: after forming the first groove and the second groove, forming the first groove and an isolation layer is formed in the second groove. 9. The method for forming a semiconductor structure according to claim 8, wherein some of the first fins and the second fins are dummy fins, and the method for forming the semiconductor structure further comprises: After forming the second fin and the first fin, and before forming the isolation layer, the dummy fin is removed. 10. The method for forming a semiconductor structure according to claim 8, wherein the step of forming an isolation layer in the first groove and the second groove comprises: forming a first isolation layer in the first groove; A second isolation layer is formed in the second groove, and the density of the second isolation layer is higher than that of the first isolation layer. 11. The method for forming a semiconductor structure according to claim 10, wherein the material of the first isolation layer is silicon oxide, and the material of the second isolation layer is silicon nitride. 12. The method for forming a semiconductor structure according to claim 5 or 7, wherein the material of the groove protection layer is bottom anti-reflective coating, silicon oxide, silicon nitride or silicon oxynitride. 13. The method for forming a semiconductor structure according to claim 1, wherein the first device is a PMOS device, and the second device is an NMOS device. 14. A semiconductor structure, characterized in that it comprises: A substrate, the substrate includes a second region and a first region, the second region is used to form a second device, the first region is used to form a first device, and the power of the second device is higher than that of the first device the power of a device; The first region includes a first substrate and a plurality of first fins separated on the first substrate, and a first groove is formed between adjacent first fins; The second region includes a second substrate and a plurality of second fins separated on the second substrate, and a second groove is formed between adjacent second fins; the depth of the second groove is less than the depth of the first groove. 15. The semiconductor structure according to claim 14, wherein the depth of the second groove is 600-900 angstroms. 16. The semiconductor structure according to claim 14, wherein the depth of the first groove is 1000-1500 angstroms. 17. The semiconductor structure of claim 14, wherein the first device is a PMOS device and the second device is an NMOS device. 18. The semiconductor structure according to claim 14, wherein an isolation layer is formed in the first groove and the second groove. 19. The semiconductor structure according to claim 18, wherein the isolation layer located in the second groove is a second isolation layer, and the isolation layer located in the first groove is a first isolation layer. An isolation layer, the density of the second isolation layer is higher than that of the first isolation layer. 20. The semiconductor structure according to claim 19, wherein the material of the first isolation layer is silicon oxide, and the material of the second isolation layer is silicon nitride.