CN106952816B - Method of forming a fin transistor - Google Patents

Abstract

A method of forming a fin transistor, comprising: providing a substrate, wherein the substrate comprises a core area and a peripheral area, and fin parts are respectively arranged on the surfaces of the substrate in the core area and the peripheral area; forming an isolation layer on the surface of the substrate, wherein the isolation layer covers part of the side wall of the fin part, and the surface of the isolation layer is lower than the top surface of the fin part; forming a first gate oxide layer on the side wall and the top surface of the exposed fin part; forming a protective layer on the surface of the first gate oxide layer; forming a pseudo gate layer respectively crossing the fin parts of the core region and the peripheral region on the surface of the protective layer; forming a dielectric layer on the surface of the protective layer; removing the pseudo gate layer, forming a first groove in the dielectric layer of the peripheral region, and forming a second groove in the dielectric layer of the core region; removing the protective layer and the first gate oxide layer at the bottom of the second trench to expose partial side wall and top surface of the fin part in the core region; and forming a second gate oxide layer on the exposed side wall of the fin part at the bottom of the second groove and the surface of the top part. The leakage current of the formed fin type transistor is controlled, and the reliability is improved.

Description

Method of forming a fin transistor

technical field

The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a method for forming a fin transistor.

Background technique

With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. As the most basic semiconductor device, transistors are currently being widely used. Therefore, with the increase in the component density and integration of semiconductor devices, the gate size of planar transistors is getting shorter and shorter, and the traditional planar transistors have the ability to control the channel current. become weaker, resulting in short channel effect and leakage current, which ultimately affects the electrical performance of semiconductor devices.

In order to overcome the short channel effect of the transistor and suppress the leakage current, the prior art proposes a fin field effect transistor (Fin FET), which is a common multi-gate device. The structure of the fin field effect transistor includes: a fin and a dielectric layer located on the surface of the semiconductor substrate, the dielectric layer covers part of the sidewall of the fin, and the surface of the dielectric layer is lower than the top of the fin; and gate structures on the top and sidewall surfaces of the fins; source and drain regions within the fins on both sides of the gate structures.

However, as the density and size of semiconductor devices increase, the manufacturing process of the fin field effect transistor is more difficult, and the performance and reliability of the formed fin field effect transistor deteriorate.

SUMMARY OF THE INVENTION

The problem solved by the present invention is to provide a method for forming a fin transistor, the leakage current of the formed fin transistor is controlled, the driving current is increased, the power consumption is reduced, and the stability is improved.

In order to solve the above problems, the present invention provides a method for forming a fin transistor, including: providing a substrate, the substrate includes a core region and a peripheral region, and the substrate surfaces of the core region and the peripheral region respectively have fins; An isolation layer is formed on the surface of the substrate, the isolation layer covers part of the sidewall of the fin, and the surface of the isolation layer is lower than the top surface of the fin; on the side of the exposed fin A first gate oxide layer is formed on the wall and the top surface; a protective layer is formed on the surface of the first gate oxide layer; a dummy gate layer is formed on the surface of the protective layer respectively across the fins of the core region and the peripheral region, the The dummy gate layer covers part of the sidewalls and the top of the fin; a dielectric layer is formed on the surface of the protective layer, the dielectric layer covers the sidewalls of the dummy gate layer, and the dielectric layer exposes the dummy gate layer top; remove the dummy gate layer, form a first trench in the dielectric layer of the peripheral region, and form a second trench in the dielectric layer of the core region; remove the protective layer at the bottom of the second trench and a first gate oxide layer, exposing part of the sidewall and top surface of the core region fin; forming a second gate oxide layer on the exposed sidewall and top surface of the fin at the bottom of the second trench; forming on the surface of the protective layer A first gate structure filling the first trench; forming a second gate structure filling the second trench on the surface of the second gate oxide layer.

Optionally, the protective layer includes a nitrogen-containing layer.

Optionally, the material of the protective layer includes silicon nitride or silicon oxynitride.

Optionally, the formation process of the protective layer is an atomic layer deposition process; the protective layer is also formed on the surface of the isolation layer.

Optionally, the protective layer further includes a silicon oxide layer on the surface of the nitrogen-containing layer.

Optionally, after removing the protective layer and the first gate oxide layer at the bottom of the second trench, the silicon oxide layer in the first trench is removed.

Optionally, the step of removing the protective layer and the first gate oxide layer at the bottom of the second trench includes: forming a first patterned layer on the surface of the dielectric layer and in the first trench; using the first patterned layer As a mask, the protective layer and the first gate oxide layer in the second trench are etched until part of the sidewalls and the top surface of the fins in the core region are exposed; after the protective layer and the first gate are etched After the oxygen layer is removed, the first patterned layer is removed; after the first patterned layer is removed, the silicon oxide layer in the first trench is removed.

Optionally, the process of removing the dummy gate layer is one or a combination of a wet etching process and a dry etching process.

Optionally, the dry etching process is an isotropic dry etching process.

Optionally, the dry etching process is a plasma dry etching process.

Optionally, the formation process of the first gate oxide layer is an in-situ steam generation process.

Optionally, the formation process of the second gate oxide layer is a thermal oxidation process or a wet oxidation process.

Optionally, after removing the protective layer and the first gate oxide layer at the bottom of the second trench and before forming the second gate oxide layer, pre-cleaning is performed on the inner wall surfaces of the first trench and the second trench.

Optionally, the first gate structure includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer, and the first gate layer fills the first trench; The second gate structure includes a second gate dielectric layer and a second gate layer located on the second gate dielectric layer, and the second gate layer fills the second trench.

Optionally, the step of forming the first gate structure and the second gate structure includes: forming a gate dielectric film on the surface of the dielectric layer, the inner wall surface of the first trench and the inner wall surface of the second trench; After the gate dielectric film is formed, a gate film is formed that fills the first trench and the second trench; the gate film and the gate dielectric film are planarized until the surface of the dielectric layer is exposed. A first gate dielectric layer and a first gate electrode layer are formed in the trench, and a second gate dielectric layer and a second gate electrode layer are formed in the second trench.

Optionally, the top surface of the fin portion further has a mask layer.

Optionally, the steps of forming the substrate and the fins include: providing a semiconductor substrate; forming a mask layer on a part of the surface of the semiconductor substrate, the mask layer covering the corresponding positions and shapes of the fins that need to be formed; The mask layer is a mask, and the semiconductor substrate is etched to form the substrate and the fins.

Optionally, the step of forming the isolation layer includes: forming an isolation film on the surfaces of the substrate and the fin; planarizing the isolation film; after planarizing the isolation film, etch back the isolation film until Part of the sidewall of the fin is exposed.

Optionally, the mask layer is removed while or after the isolation film is etched back.

Optionally, before forming the isolation layer, a pad oxide layer is formed on the surfaces of the substrate and the fin; after the isolation layer is formed, the exposed pad oxide layer is removed.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the formation method of the present invention, after the first gate oxide layer is formed on the sidewalls and the top surface of the fin, a protective layer is formed on the surface of the first gate oxide layer, and the dummy gate layer is formed on the surface of the protective layer. When the dielectric layer is subsequently formed and the dummy gate layer is removed, the protective layer can be used to protect the first gate oxide layer from damage, avoid the time-dependent breakdown effect of the first gate oxide layer, and improve the overall performance of the gate oxide layer. The formed fin transistor has the ability to suppress the short channel effect, increases the driving current, reduces the power consumption of the transistor, and suppresses the influence of the bias temperature instability effect. In addition, the density of the protective layer is high, which can prevent damage to the fins caused by the etching process when the dummy gate layer is removed, thereby improving the quality of the channel region of the fin transistor, reducing leakage current, and improving the performance of the fin transistor. performance and reliability.

Description of drawings

1 to 4 are schematic cross-sectional structural diagrams of a formation process of a fin field effect transistor;

FIG. 5 to FIG. 15 are schematic cross-sectional structural diagrams of a formation process of a fin transistor according to an embodiment of the present invention.

Detailed ways

As described in the background art, as the density and size of semiconductor devices are increased, the performance and reliability of the formed fin field effect transistors are deteriorated.

In order to further reduce the device size and improve the device density, high-K metal gate transistors are introduced on the basis of fin field effect transistors, that is, high-K dielectric materials are used as gate dielectric layers, and metal materials are used as gate electrodes. Moreover, in order to improve the bonding state between the gate dielectric layer of the high-K dielectric material and the fins, a gate oxide layer needs to be formed between the gate dielectric layer of the high-K dielectric material and the fins for bonding. The high-K metal gate transistor is formed by a gate last (Gate Last) process. In one gate last process, after removing the dummy gate layer of polysilicon and forming a gate trench, the inner wall surface of the gate trench is formed. A gate dielectric layer of high-K dielectric material is formed.

However, for the fin field effect transistor in the peripheral region, since the gate oxide layer is formed before the dummy gate layer is formed, the process of removing the dummy gate layer will damage the gate oxide layer. As the size of the fin field effect transistor becomes smaller, the damage of the gate oxide layer has a more obvious influence on the device performance. The following description will be made with reference to the accompanying drawings.

FIG. 1 to FIG. 4 are schematic cross-sectional structural diagrams of a formation process of a fin field effect transistor.

Referring to FIG. 1 , a substrate 100 is provided, the substrate 100 includes a core region 110 and a peripheral region 120 , the surfaces of the substrate 100 of the core region 110 and the peripheral region 120 respectively have fins 101 , and the surfaces of the substrate 100 An isolation layer 102 is formed, the isolation layer 102 covers part of the sidewall surface of the fin 101 , and the surface of the isolation layer 102 is lower than the top surface of the fin 101 .

Referring to FIG. 2 , a first gate oxide layer 103 is formed on the sidewalls and top surfaces of the exposed fins 101 ; and a surface of the first gate oxide layer 103 is formed across the core region 110 and the peripheral region respectively 120 The dummy gate layer 104 of the fin portion 101 , the dummy gate layer 104 covers part of the sidewalls and the top of the fin portion 101 .

Referring to FIG. 3 , a dielectric layer 105 is formed on the surface of the first gate oxide layer 103 , the dielectric layer 105 covers the sidewalls of the dummy gate layer 104 , and the dielectric layer 105 exposes the dummy gate layer 104 top.

Referring to FIG. 4 , the dummy gate layer 104 is removed, a first trench 121 is formed in the dielectric layer 105 of the peripheral region 120 , and a second trench 111 is formed in the dielectric layer 105 of the core region 110 .

Wherein, the formation process of the first gate oxide layer 103 is an atomic layer deposition process, and the material is silicon oxide. The first gate oxide layer 103 is used to protect the sidewalls and top surfaces of the fins 101 of the core region 110 and the peripheral region 120 when the dummy gate layer 104 is removed. Due to the low density of silicon oxide formed by the atomic layer deposition process, defects are easily formed inside. Therefore, the first gate oxide layer 103 is not suitable as the gate oxide layer of the fin field effect transistor in the core region 110, and the core needs to be removed later. The first gate oxide layer 103 of the region 110 .

Secondly, since the fin field effect transistor in the peripheral region 120 has lower requirements on the density of the gate oxide layer and the number of internal defects, the first oxide layer 103 in the peripheral region 120 can be reserved as the fin field effect transistor formed in the peripheral region 120 inside the gate oxide layer. After the dummy gate layer 104 is removed, the first gate oxide layer 103 of the core region 110 needs to be removed subsequently, and a second gate oxide layer is formed on the exposed fins 101 and the bottom surface of the core region 110 by a thermal oxidation process.

However, although the first gate oxide layer 103 can protect the sidewalls and top surfaces of the fins 101 of the core region 110 and the peripheral region 120 when the dummy gate layer 104 is removed, the etching process of removing the dummy gate layer 104 The etching process is also easy to cause damage to the first gate oxide layer 103, and the damaged first gate oxide layer 103 not only easily causes Time Dependent Dielectric Breakdown (TDDB), but also causes short channel effects, reduced Small driving current and increased power consumption are also likely to cause deterioration of transistor performance caused by bias temperature instability (Bias Temperature Instability, BTI for short).

In addition, the process of removing the dummy gate layer 104 can be a dry etching process or a wet etching process. Especially when the dummy gate layer 104 is removed by the plasma dry etching process, not only the first gate oxide layer 103 is easily damaged, but the plasma with energy is also liable to damage the interior of the fins 101; When the width of the fin portion 101 is smaller, the damaged area of the fin portion 101 is larger, and the damage to the fin portion 101 has a greater impact on the formed fin field effect transistor.

In order to solve the above problems, the present invention provides a method for forming a fin transistor, comprising: providing a substrate, the substrate includes a core region and a peripheral region, and the substrate surfaces of the core region and the peripheral region respectively have fins; An isolation layer is formed on the surface of the substrate, the isolation layer covers part of the sidewall of the fin, and the surface of the isolation layer is lower than the top surface of the fin; on the side of the exposed fin A first gate oxide layer is formed on the wall and the top surface; a protective layer is formed on the surface of the first gate oxide layer; a dummy gate layer is formed on the surface of the protective layer respectively across the fins of the core region and the peripheral region, the The dummy gate layer covers part of the sidewalls and the top of the fin; a dielectric layer is formed on the surface of the protective layer, the dielectric layer covers the sidewalls of the dummy gate layer, and the dielectric layer exposes the dummy gate layer top; remove the dummy gate layer, form a first trench in the dielectric layer of the peripheral region, and form a second trench in the dielectric layer of the core region; remove the protective layer at the bottom of the second trench and a first gate oxide layer, exposing part of the sidewall and top surface of the core region fin; forming a second gate oxide layer on the exposed sidewall and top surface of the fin at the bottom of the second trench; forming on the surface of the protective layer A first gate structure filling the first trench; forming a second gate structure filling the second trench on the surface of the second gate oxide layer.

Wherein, after the first gate oxide layer is formed on the sidewalls and the top surface of the fin, a protective layer is formed on the surface of the first gate oxide layer, and the dummy gate layer is formed on the surface of the protective layer. When the dielectric layer is subsequently formed and the dummy gate layer is removed, the protective layer can be used to protect the first gate oxide layer from damage, avoid the time-dependent breakdown effect of the first gate oxide layer, and improve the overall performance of the gate oxide layer. The formed fin transistor has the ability to suppress the short channel effect, increases the driving current, reduces the power consumption of the transistor, and suppresses the influence of the bias temperature instability effect. In addition, the density of the protective layer is high, which can prevent damage to the fins caused by the etching process when the dummy gate layer is removed, thereby improving the quality of the channel region of the fin transistor, reducing leakage current, and improving the performance of the fin transistor. performance and reliability.

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 5 to FIG. 15 are schematic cross-sectional structural diagrams of a formation process of a fin transistor according to an embodiment of the present invention.

Referring to FIG. 5 , a substrate 200 is provided, the substrate 200 includes a core region 220 and a peripheral region 210 , and fins 201 are respectively provided on the surfaces of the substrate 200 of the core region 220 and the peripheral region 210 .

The core area 220 is used to form core devices, and the peripheral area 210 is used to form peripheral devices, such as input-output (I/O) devices. The core device density of the core region 220 is greater than the peripheral device density of the peripheral region 210 , and the critical dimension (Critical Dimention, CD for short) of the core device is smaller than that of the peripheral device. The working current or working voltage of the core device is smaller than the working current or working voltage of the peripheral device. In this embodiment, the surfaces of the substrate 200 in the core region 220 and the peripheral region 210 respectively have fins 201 for forming fin transistors in the core region 220 and the peripheral region 210 respectively.

In this embodiment, the top surface of the fin portion 201 also has a mask layer 202 . The mask layer 202 serves as a mask for forming the fins 201 by etching, and the mask layer 202 can also be used to protect the top surfaces of the fins 201 in subsequent processes.

In this embodiment, the steps of forming the substrate 200 and the fins 201 include: providing a semiconductor substrate; forming a mask layer 202 on a part of the surface of the semiconductor substrate, and the mask layer 202 covers the fins 200 to be formed. The corresponding position and shape of the semiconductor substrate are etched using the mask layer 202 as a mask to form the substrate 200 and the fins 201 .

The semiconductor substrates are silicon substrates, germanium substrates and silicon germanium substrates. In this embodiment, the semiconductor substrate is a single crystal silicon substrate, that is, the materials of the fins 201 and the substrate 200 are single crystal silicon.

The steps of forming the mask layer 202 include: forming a mask material film on the surface of the semiconductor substrate; forming a second patterned layer on the surface of the mask material film; and using the second patterned layer as a mask for etching. The mask material film is formed until the surface of the semiconductor substrate is exposed to form the mask layer 204 .

In one embodiment, the second patterned layer is a patterned photoresist layer, and the second patterned layer is formed by a coating process and a photolithography process. In another embodiment, in order to reduce the feature size of the fins 201 and the distance between adjacent fins 201 , the second patterned layer is formed by a multiple patterning mask process. The multiple patterning mask process includes: a self-aligned double patterned (SaDP) process, a self-aligned triple patterned (Self-aligned triple patterned) process, or a self-aligned quadruple patterning (Self-aligned Double Double Patterned, SaDDP) process.

The process of etching the semiconductor substrate is an anisotropic dry etching process. The sidewalls of the fins 201 are perpendicular or inclined with respect to the surface of the substrate 200 , and when the sidewalls of the fins 201 are inclined with respect to the surface of the substrate 200 , the bottom dimension of the fins 201 is larger than the top dimension. In this embodiment, the sidewalls of the fins 201 are inclined relative to the surface of the substrate 200 .

The peripheral region 210 also has a first well region in the substrate 200 and the fins 201 , and the core region 220 also has a second well region in the substrate 200 and the fins 201 . The first well region and the second well region are formed by an ion implantation process; the first well region and the second well region can be formed before etching the semiconductor substrate to form the fin portion 201; or, the first well region and the second well region can be formed after the fins 201 are formed.

In another embodiment, the fin is formed by etching a semiconductor layer formed on the surface of the substrate; the semiconductor layer is formed on the surface of the substrate by a selective epitaxial deposition process. The substrate is a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate or a III-V compound substrate, such as a gallium nitride substrate or GaAs substrates, etc. The material of the semiconductor layer is silicon, germanium, silicon carbide or silicon germanium.

In this embodiment, before the subsequent formation of the isolation layer, the method further includes forming a pad oxide layer 203 on the surfaces of the substrate 200 and the fins 201 . The formation process of the pad oxide layer 203 is an in-situ steam generation (In-Situ Steam Generation, ISSG for short) process. The parameters of the in-situ steam generation process include: the temperature is 700°C to 1200°C, the gas includes hydrogen and oxygen, the oxygen flow is 1 slm to 50 slm, the hydrogen flow is 1 slm to 10 slm, and the time is 20 seconds to 10 minutes. The pad oxide layer 203 formed by the in-situ steam generation process has good step coverage capability, so that the formed pad oxide layer 203 can tightly cover the sidewall surface of the fin 201, and the formed pad oxide layer 203 The thickness of layer 203 is uniform.

By forming the pad oxide layer 203 , the surface of the substrate 200 and the fins 201 can be repaired from damage during the pre-etching process and the ion implantation process. Moreover, the pad oxide layer 203 can also protect the surfaces of the fins 201 and the substrate 200 in subsequent processes.

Referring to FIG. 6 , an isolation layer 204 is formed on the surface of the substrate 200 , the isolation layer 204 covers part of the sidewalls of the fins 201 , and the surface of the isolation layer 204 is lower than the top surface of the fins 201 .

The steps of forming the isolation layer 204 include: forming an isolation film on the surfaces of the substrate 200 and the fins 201; planarizing the isolation film; after planarizing the isolation film, etch back the isolation film until exposed until part of the side wall of the fins 201 is exposed.

In this embodiment, the material of the isolation layer 204 is silicon oxide; the thickness of the isolation layer 204 is 1/4˜1/2 of the height of the fin portion 201 . The formation process of the isolation film is a fluid chemical vapor deposition process (FCVD, Flowable Chemical Vapor Deposition). In other embodiments, the isolation film can also be formed by other chemical vapor deposition processes or physical vapor deposition processes; the other chemical vapor deposition processes include plasma enhanced chemical vapor deposition (PECVD) or high aspect ratio chemical vapor deposition Process (HARP).

In this embodiment, the steps of the fluid chemical vapor deposition process include: forming a precursor dielectric film on the surfaces of the substrate 200 , the fins 201 and the mask layer 202 ; performing an annealing process to solidify the precursor dielectric film to form the the isolation film.

The material of the precursor dielectric film is a silicon-containing flowable material; the flowable material can be a polymer containing one or more of Si-H bonds, Si-N bonds and Si-O bonds. The process parameters for forming the precursor dielectric film include: the process temperature is 60°C to 70°C, and in this embodiment, it is 65°C.

The annealing process in the fluid chemical vapor deposition process can be a wet annealing process or a dry annealing process; the parameters of the annealing process include: the temperature is less than or equal to 600° C., and the annealing gas includes H ₂ , O ₂ , N ₂ , One or more combinations of Ar and He, and the annealing time is 5 seconds to 1 minute. Wherein, when the annealing gas includes H ₂ and O ₂ , the annealing process is a wet annealing process.

The planarization process is a chemical mechanical polishing process (CMP); in this embodiment, the chemical mechanical polishing process uses the mask layer 202 as a stop layer. The process of etching back the isolation film is an isotropic dry etching process, an anisotropic dry etching process or a wet etching process.

In this embodiment, the mask layer 202 (as shown in FIG. 5 ) is removed while or after the isolation film is etched back. After the isolation layer 204 is formed, the exposed pad oxide layer 203 is removed; since the exposed pad oxide layer 203 will be damaged in the process of etching back the isolation film, the pad oxide layer 203 It is not suitable as a subsequent gate oxide layer, so the pad oxide layer 203 needs to be removed.

Referring to FIG. 7 , a first gate oxide layer 211 is formed on the sidewalls and top surfaces of the exposed fins 201 .

In this embodiment, the first gate oxide layer 211 is used to form the gate oxide layer in the fin transistor in the peripheral region 210 , and is used to enhance the connection between the fin portion 201 and the subsequently formed first gate dielectric layer in the peripheral region 210 . The material of the first gate dielectric layer is a high-K dielectric material (dielectric coefficient is greater than 3.9), and the first gate dielectric layer serves as the gate dielectric layer of the fin field effect transistor in the peripheral region 210 .

The material of the first gate oxide layer 211 is silicon oxide, and the formation process of the first gate oxide layer 211 is an in-situ steam generation process; the thickness of the first gate oxide layer 211 is 20 angstroms to 50 angstroms. In this example, it is 30 angstroms. The parameters of the in-situ steam generation process include: the temperature is 700°C to 1200°C, the gas includes hydrogen and oxygen, the oxygen flow is 1 slm to 50 slm, the hydrogen flow is 1 slm to 10 slm, and the time is 10 seconds to 5 minutes.

In another embodiment, the formation process of the first gate oxide layer 211 is a chemical oxidation process; the chemical oxidation process includes: using an aqueous solution into which ozone is passed to the exposed sidewalls and the fins 201 . The top surface is oxidized, and a first oxide layer is formed on the sidewalls and the top surface of the fins 201 . Wherein, in the ozone-infused aqueous solution, the concentration of ozone in the water is 1% to 15%.

Referring to FIG. 8 , a protective layer is formed on the surface of the first gate oxide layer 211 .

The protective layer is used to protect the fin portion 201 and the first gate oxide layer 211 from being damaged when the dummy gate layer is subsequently removed. In this embodiment, the protective layer includes a nitrogen-containing layer 212, and the nitrogen-containing layer 212 has a high density and hardness, which is beneficial to protect the first gate oxide layer 211 and the fins 201 in subsequent processes. Moreover, since the dielectric coefficient of the nitrogen-containing layer 212 is relatively high, it is beneficial to suppress the carrier tunneling phenomenon between the fin portion 201 and the subsequently formed first gate dielectric layer, and reduce leakage current.

In this embodiment, the material of the nitrogen-containing layer 212 includes silicon nitride or silicon oxynitride; the formation process of the nitrogen-containing layer 212 is an atomic layer deposition process; the thickness of the nitrogen-containing layer 212 is 30 angstroms～ 50 angstroms. The nitrogen-containing layer 212 formed by the atomic layer deposition process has good step coverage, and can closely adhere to the surface of the isolation layer 204 and the first gate oxide layer 211 .

First, since the first gate oxide layer 211 is used to form the gate oxide layer in the fin field effect transistor of the peripheral region 210, the first gate oxide layer 211 of the peripheral region 210 needs to be exposed in the subsequent process. The formed protective layer can reduce the damage to the first gate oxide layer 211 in the subsequent etching process of removing the dummy gate layer.

Secondly, when the subsequent etching process for removing the dummy gate layer includes a plasma dry etching process, the plasma etching process is likely to cause damage to the interior of the fins 201, and the density and hardness of the protective layer are high, Therefore, it can be used to block plasma, so as to avoid damage to the fins 201 , thereby reducing the leakage current in the fin transistors formed in the peripheral region 210 and improving the performance of the fin transistors.

In this embodiment, the protective layer further includes a silicon oxide layer 213 located on the surface of the nitrogen-containing layer 212 . The nitrogen-containing layer 212 needs to be retained in the fin transistor later, and the silicon oxide layer can protect the surface of the nitrogen-containing layer 212 from damage when the first gate oxide layer 211 of the core region 220 is subsequently removed, thereby The stability of the fin transistors in the peripheral region 210 is ensured.

Referring to FIG. 9 , a dummy gate layer 205 is formed on the surface of the passivation layer that spans the core region 220 and the fin portion 201 of the peripheral region 210 respectively, and the dummy gate layer 205 covers part of the sidewall and the fin portion 201 . top.

The material of the dummy gate layer 205 is polysilicon. The steps of forming the dummy gate layer 205 include: forming a dummy gate film on the surface of the protective layer; planarizing the dummy gate film; after the planarization process, forming a dummy gate film on the surface of the dummy gate film forming a third patterned layer covering the position and shape of the dummy gate layer 205 to be formed; using the third patterned layer as a mask, etching the dummy gate film until exposed A dummy gate layer is formed up to the surface of the protective layer.

In this embodiment, spacers are further formed on the sidewall surfaces of the dummy gate layer 205 ; source regions and drain regions are formed in the fins 201 on both sides of the dummy gate layer 205 and the spacers.

The material of the spacer includes one or more combinations of silicon oxide, silicon nitride and silicon oxynitride. The step of forming the spacer includes: forming a spacer film on the surface of the protective layer and the dummy gate layer 205 by a deposition process; etching back the spacer film until the position of the protective layer on the surface of the fins 201 is exposed to form a sidewall film. wall.

In one embodiment, the source and drain regions are formed by an ion implantation process. In another embodiment, the step of forming the source region and the drain region further includes: forming a groove in the dummy gate layer 205 and the fins on both sides of the spacer; using a selective epitaxial deposition process in the groove A stress layer is formed in the stress layer; ions are doped in the stress layer to form a source region and a drain region. The doping process is one or a combination of an ion implantation process and an in-situ doping process. When the formed fin transistor is a PMOS transistor, the material of the stressor layer is silicon germanium, the ions doped in the stressor layer are P-type ions, and the stressor layer is a Σ-type stressor layer. When the formed fin transistor is an NMOS transistor, the material of the stressor layer is silicon carbide, and the ions doped in the stressor layer are N-type ions.

Referring to FIG. 10 , a dielectric layer 206 is formed on the surface of the protective layer, the dielectric layer 206 covers the sidewalls of the dummy gate layer 205 , and the top of the dummy gate layer 205 is exposed by the dielectric layer 206 .

The steps of forming the dielectric layer 206 include: forming a dielectric film on the surface of the protective layer and the dummy gate layer 205 ; planarizing the dielectric film until the top surface of the dummy gate layer 205 is exposed, and forming the dielectric layer 206.

The forming step of the dielectric film is a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. The material of the dielectric layer 206 is silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material (dielectric coefficient is greater than or equal to 2.5, less than 3.9, such as porous silicon oxide or porous silicon nitride) or ultra-low k-dielectric material (dielectric coefficient less than 2.5, such as porous SiCOH).

In this embodiment, the material of the dielectric layer 206 is silicon oxide; the forming process of the dielectric film is a fluid chemical vapor deposition (Flowable Chemical Vapor Deposition, FCVD for short) process, High Density Plasma (High Density Plasma, for short). One or more of HDP) process, plasma enhanced deposition process.

Referring to FIG. 11 , the dummy gate layer 205 is removed, a first trench 214 is formed in the dielectric layer 206 of the peripheral region 210 , and a second trench 221 is formed in the dielectric layer 206 of the core region 220 .

The process of removing the dummy gate layer 205 is one or a combination of a dry etching process and a wet etching process; wherein, the dry etching process is an isotropic dry etching process.

In this embodiment, the material of the dummy gate layer 205 is polysilicon, and the process of removing the dummy gate layer 205 is a plasma dry etching process; the parameters of the plasma dry etching process include: the gas includes A fluorocarbon gas, one or both of HBr and Cl ₂ , and a carrier gas, the fluorocarbon gas including CF ₄ , CHF ₃ , CH ₂ F ₂ , CH ₃ F, the carrier gas being an inert gas such as He, the gas flow is 50sccm-400sccm, and the pressure is 3mtorr-8mtorr.

In the plasma dry etching process, the plasma with energy is likely to cause damage to the interior of the fins 201 , and the density and hardness of the protective layer are high, so that the dummy gate layer 205 can be diffused during the process of diffusing the protective layer. , the bombardment of the plasma is blocked, so as to prevent the fins 201 from being damaged by the plasma.

In another embodiment, the process of removing the dummy gate layer is a wet etching process, and the etching solution of the wet etching process is a hydrofluoric acid solution.

Referring to FIG. 12 , the protective layer at the bottom of the second trench 221 and the first gate oxide layer 211 are removed to expose part of the sidewalls and the top surface of the fin 201 of the core region 220 .

The step of removing the protective layer at the bottom of the second trench 221 and the first gate oxide layer 211 includes: forming a first patterned layer 222 on the surface of the dielectric layer 206 and in the first trench 214; The layer 222 is a mask, and the protective layer and the first gate oxide layer 211 in the second trench 221 are etched until part of the sidewalls and the top surface of the fins 201 of the core region 220 are exposed.

The first patterned layer 222 is a patterned photoresist layer, and the first patterned layer 222 fills the first trench 214 . In this embodiment, the first patterned layer 222 is also located on the surface of the dielectric layer 206 . The process of etching the protective layer and the first gate oxide layer 211 is a wet etching process or an isotropic dry etching process.

In this embodiment, the protective layer includes a nitrogen-containing layer 212 and a silicon oxide layer 213, and the process for removing the nitrogen-containing layer 212 and the silicon oxide 213 is a wet etching process; wherein, the nitrogen-containing layer 212 is removed The etching solution used for removing the silicon oxide layer 213 is a phosphoric acid solution, and the etching solution for removing the silicon oxide layer 213 is a hydrofluoric acid solution.

In this embodiment, the isotropic dry etching process for etching the first gate oxide layer 211 can be a SICONI process. The etching rate of the SICONI process is uniform in different directions, and the first gate oxide layer 211 located on the sidewall and top surface of the fin 201 can be uniformly removed, and the damage to the sidewall and top surface of the fin 201 can be uniformly removed. smaller.

The parameters of the SICONI process include: a power of 10W to 100W, a frequency of less than 100kHz, an etching temperature of 40 to 80 degrees Celsius, a pressure of 0.5 Torr to 50 Torr, and the etching gas includes NH ₃ , NF ₃ , and He, where NH 3 , NF 3 , and He. The flow rate of ₃ is 0sccm~500sccm, the flow rate of NF3 is _20sccm ~200sccm, the flow rate of He is 400sccm~1200sccm, and the flow rate ratio of NF3 to _NH3 is ₁ :20~5:1.

Referring to FIG. 13 , after etching the protective layer and the first gate oxide layer 211 , the first patterned layer 222 is removed (as shown in FIG. 12 ).

In this embodiment, the first patterned layer 222 is a patterned photoresist layer, and the process of removing the first patterned layer 222 is a wet stripping process or an ashing process. During the process of removing the first patterned layer 222 , the silicon oxide layer 213 is used to protect the protective layer 212 to prevent the protective layer 212 from being damaged. After removing the first patterned layer 222, the silicon oxide layer 213 within the first trench 214 is removed. The process of removing the silicon oxide layer 213 is a wet etching process or an isotropic dry etching process.

In this embodiment, after removing the protective layer at the bottom of the second trench 221 and the first gate oxide layer 211, and before forming the second gate oxide layer, the inner wall surfaces of the first trench 214 and the second trench 221 are subjected to Pre-cleaning is used to remove impurities attached to the inner wall surfaces of the first trench 214 and the second trench 221 .

Referring to FIG. 14 , a second gate oxide layer 223 is formed on the sidewalls and top surfaces of the fins 201 exposed at the bottom of the second trenches 221 .

The second gate oxide layer 223 is used as the gate oxide layer of the fin transistor formed in the core region 210 . The material of the second gate oxide layer 223 is silicon oxide; the formation process of the second gate oxide layer 223 is a thermal oxidation process or a wet oxidation process.

The thickness of the second gate oxide layer 223 is 3 nanometers to 10 nanometers. In this embodiment, the formation process of the second gate oxide layer 223 is a chemical oxidation process; the steps of the chemical oxidation process include: using an aqueous solution into which ozone is introduced to the exposed sidewalls and tops of the fins 201 The surface is oxidized, and a second gate oxide layer 223 is formed on the sidewall and top surface of the fin portion 201 . Wherein, in the ozone-infused aqueous solution, the concentration of ozone in the water is 1% to 15%.

Referring to FIG. 15 , a first gate structure filled with the first trench 214 (as shown in FIG. 14 ) is formed on the surface of the protective layer; The second gate structure of the second trench 221 (shown in FIG. 14 ).

The first gate structure includes a first gate dielectric layer 215 and a first gate layer 216 located on the first gate dielectric layer 215, and the first gate layer 216 fills the first trench 214; The second gate structure includes a second gate dielectric layer 224 and a second gate layer 225 located on the second gate dielectric layer 224 , and the second gate layer 225 fills the second trench 221 .

The steps of forming the first gate structure and the second gate structure include: forming a gate dielectric film on the surface of the dielectric layer 206, the inner wall surface of the first trench 214 and the inner wall surface of the second trench 221; After the gate dielectric film, a gate film filled with the first trench 214 and the second trench 221 is formed; the gate film and the gate dielectric film are planarized until the surface of the dielectric layer 206 is exposed. A first gate dielectric layer 215 and a first gate layer 216 are formed in a trench 214 , and a second gate dielectric layer 224 and a second gate layer 225 are formed in the second trench 221 .

The materials of the first gate dielectric layer 215 and the second gate dielectric layer 224 are high-k dielectric materials (dielectric coefficient greater than 3.9); the high-k dielectric materials include hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, Zirconia silicon, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide. The formation process of the gate dielectric film is an atomic layer deposition process.

The materials of the first gate layer 216 and the second gate layer 225 include copper, tungsten, aluminum or silver; the formation process of the gate film includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, Electroplating process or electroless plating process. The process of planarizing the gate film and the gate dielectric film is a chemical mechanical polishing process (CMP).

In one embodiment, before forming the gate film, it further includes forming a work function film on the surface of the gate dielectric film; forming a gate film on the surface of the work function film; after planarizing the gate film , planarizing the work function film until the surface of the dielectric layer 206 is exposed to form a work function layer. The materials of the work function layers formed in the first trench 214 and the second trench 221 can be the same or different.

In this embodiment, after the gate dielectric film is formed and before the gate film is formed, an annealing process is further included. The annealing process is used to remove defects or impurities inside and on the surface of the fin portion 201 , as well as in the first gate oxide layer 211 , the second gate oxide layer 223 , the first gate dielectric layer 215 and the second gate dielectric layer 224 defects or impurities. Furthermore, the annealing process can also be used to activate impurity ions in the source and drain regions within the fin 201 .

To sum up, in this embodiment, after the first gate oxide layer is formed on the sidewalls and the top surface of the fin, a protective layer is formed on the surface of the first gate oxide layer, and the dummy gate layer is formed on the surface of the protective layer. When the dielectric layer is subsequently formed and the dummy gate layer is removed, the protective layer can be used to protect the first gate oxide layer from damage, avoid the time-dependent breakdown effect of the first gate oxide layer, and improve the overall performance of the gate oxide layer. The formed fin transistor has the ability to suppress the short channel effect, increases the driving current, reduces the power consumption of the transistor, and suppresses the influence of the bias temperature instability effect. In addition, the density of the protective layer is high, which can prevent damage to the fins caused by the etching process when the dummy gate layer is removed, thereby improving the quality of the channel region of the fin transistor, reducing leakage current, and improving the performance of the fin transistor. performance and reliability.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (17)

1. A method for forming a fin transistor includes:

providing a substrate, wherein the substrate comprises a core area and a peripheral area, and fin parts are respectively arranged on the surfaces of the substrate in the core area and the peripheral area;

forming an isolation layer on the surface of the substrate, wherein the isolation layer covers part of the side wall of the fin part, and the surface of the isolation layer is lower than the top surface of the fin part;

forming a first gate oxide layer on the side wall and the top surface of the fin part exposed from the core region and the peripheral region;

forming a protective layer on the surfaces of the first gate oxide layers of the core region and the peripheral region, wherein the protective layer comprises a nitrogen-containing layer and a silicon oxide layer positioned on the surface of the nitrogen-containing layer;

forming a pseudo gate layer on the surface of the protective layer and respectively crossing the fin parts of the core region and the peripheral region, wherein the pseudo gate layer covers partial side walls and the tops of the fin parts;

forming a dielectric layer on the surface of the protective layer, wherein the dielectric layer covers the side wall of the pseudo gate layer and is exposed out of the top of the pseudo gate layer;

removing the pseudo gate layer, forming a first groove in the dielectric layer of the peripheral area, and forming a second groove in the dielectric layer of the core area;

removing the protective layer and the first gate oxide layer at the bottom of the second trench to expose partial side wall and top surface of the fin part in the core region;

after the protective layer and the first gate oxide layer at the bottom of the second trench are removed, removing the silicon oxide layer in the first trench;

forming a second gate oxide layer on the side wall of the fin part exposed at the bottom of the second groove and the surface of the top part;

forming a first grid structure which is filled in the first groove on the surface of the nitrogen-containing layer;

and forming a second grid structure filled in the second groove on the surface of the second grid oxide layer.

2. The method of claim 1, wherein the material of the protective layer comprises silicon nitride or silicon oxynitride.

3. The method of claim 1, wherein the formation process of the protective layer is an atomic layer deposition process; the protective layer is also formed on the surface of the isolation layer.

4. The method of claim 1, wherein removing the protective layer and the first gate oxide layer at the bottom of the second trench comprises: forming a first graphical layer in the surface of the dielectric layer and the first groove; etching the protective layer and the first gate oxide layer in the second groove by taking the first patterning layer as a mask until part of the side wall and the top surface of the fin part in the core region are exposed; after the protective layer and the first gate oxide layer are etched, removing the first patterning layer; after removing the first patterned layer, the silicon oxide layer in the first trench is removed.

5. The method of claim 1, wherein the dummy gate layer is removed by one or a combination of a wet etching process and a dry etching process.

6. The method of claim 5, wherein the dry etching process is an isotropic dry etching process.

7. The method of claim 5, wherein the dry etching process is a plasma dry etching process.

8. The method of claim 1, wherein the first gate oxide layer formation process is an in-situ steam generation process.

9. The method of claim 1, wherein the second gate oxide layer is formed by a thermal oxidation process or a wet oxidation process.

10. The method of claim 1, wherein after removing the protective layer and the first gate oxide layer at the bottom of the second trench and before forming the second gate oxide layer, a pre-clean is performed on inner wall surfaces of the first trench and the second trench.

11. The method of claim 1, wherein the first gate structure comprises a first gate dielectric layer and a first gate layer over the first gate dielectric layer, the first gate layer filling the first trench; the second gate structure comprises a second gate dielectric layer and a second gate layer positioned on the second gate dielectric layer, and the second trench is filled with the second gate layer.

12. The method of forming the fin-type transistor of claim 11, wherein the forming of the first and second gate structures comprises: forming a gate dielectric film on the surface of the dielectric layer, the surface of the inner wall of the first groove and the surface of the inner wall of the second groove; after forming the gate dielectric film, forming a gate film which is filled in the first groove and the second groove; and flattening the gate film and the gate dielectric film until the surface of the dielectric layer is exposed, forming a first gate dielectric layer and a first gate layer in the first groove, and forming a second gate dielectric layer and a second gate layer in the second groove.

13. The method of claim 1, wherein a mask layer is further formed on a top surface of the fin.

14. The method of forming the fin-type transistor of claim 13, wherein the forming the substrate and the fin comprises: providing a semiconductor substrate; forming a mask layer on part of the surface of the semiconductor substrate, wherein the mask layer covers the corresponding position and shape of the fin part to be formed; and etching the semiconductor substrate by taking the mask layer as a mask to form the substrate and the fin part.

15. The method of forming the fin-type transistor of claim 13, wherein the forming the isolation layer comprises: forming isolation films on the surfaces of the substrate and the fin part; planarizing the isolation film; and after the isolation film is planarized, etching back the isolation film until part of the fin side wall is exposed.

16. The method of forming the fin-type transistor of claim 15, wherein the mask layer is removed while or after etching back the isolation film.

17. The method of claim 1, wherein a liner oxide layer is formed on the substrate and fin surface prior to forming the isolation layer; after the isolation layer is formed, the exposed pad oxide layer is removed.

Images