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CN111200009A - Superjunction device and method of making the same - Google Patents

Superjunction device and method of making the same Download PDF

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Publication number
CN111200009A
CN111200009A CN201811381200.0A CN201811381200A CN111200009A CN 111200009 A CN111200009 A CN 111200009A CN 201811381200 A CN201811381200 A CN 201811381200A CN 111200009 A CN111200009 A CN 111200009A
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肖胜安
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Shenzhen Sanrise Tech Co ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates

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Abstract

本发明公开了一种超结器件，由保护环氧化膜将电流流动区以及终端区的截止区打开，在电流流动区的超结结构的各P型柱的顶部都形成有P型阱；JFET离子注入由保护环氧化膜自对准定义并同时形成JFET区和包围截止区的电场阻挡层；栅极结构采用分栅平面栅结构，JFET离子注入在分栅平面栅的栅氧化膜的形成工艺之前进行，使JFET离子注入杂质具有经过栅氧化膜的热氧化工艺进行退火推进的结构。本发明还公开了一种超结器件的制造方法。本发明能对JFET区和电场阻挡层实现更好的扩散，从而能降低器件的导通电阻以及提高器件的可靠性，能防止在截止区处发生软击穿，能提高器件的抗电流冲击能力，同时不会增加工艺成本以及降低开关损耗。

Figure 201811381200

The invention discloses a super junction device, wherein a current flow region and a cut-off region of a terminal region are opened by a protective epoxy film, and a P-type well is formed on the top of each P-type column of the super-junction structure in the current flow region; The JFET ion implantation is defined by the self-alignment of the protective epoxy film and simultaneously forms the JFET region and the electric field blocking layer surrounding the cut-off region; the gate structure adopts a split-gate planar gate structure, and the JFET ion implantation is in the gate oxide film of the split-gate planar gate. Before the formation process, the ion-implanted impurities of the JFET have a structure that is annealed and advanced through a thermal oxidation process of the gate oxide film. The invention also discloses a manufacturing method of the super junction device. The invention can achieve better diffusion to the JFET region and the electric field blocking layer, thereby reducing the on-resistance of the device and improving the reliability of the device, preventing soft breakdown at the cut-off region, and improving the current impact resistance of the device. , while not increasing the process cost and reducing switching losses.

Figure 201811381200

Description

Super junction device and manufacturing method thereof
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a super junction (junction) device.
Background
Existing superjunction devices include a current flow region, also commonly referred to as a charge flow region, and a voltage-carrying termination region, and a transition region between the current flow region and the termination region. In the current flowing region, there are alternately arranged P-type columns and N-type columns, i.e., P-N columns, which form a super junction structure, and typically, the P-type columns are composed of P-type epitaxial layers filled in trenches, i.e., super junction trenches, and the N-type columns are composed of N-type epitaxial layers between the P-type columns. Taking the structure of a strip-shaped P-N column as an example, a gate structure is arranged above each N column, and the gate structure comprises a planar gate structure and a trench gate structure. For a planar gate structure, the gate structure can partially cover the peripheral P-type columns or not, a P-type well is arranged above each P-type column, and a source region consisting of an N + region is arranged in each P-type well; a contact hole is formed at the top of the source region, and the source region is connected to a source electrode consisting of a front metal layer, namely a metal source electrode through the contact hole at the top; meanwhile, the bottom of the contact hole of the source region is also connected with the P-type well through a high-concentration P + contact region.
An N-type region is arranged between the adjacent P-type wells, when the device is conducted, the surfaces of the P-type wells covered by the grid structures are inverted and form channels, electrons in the source region flow to the N-type region outside the P-type wells through the inversion layers, namely the channels, on the surfaces of the P-type wells, then flow to the high-concentration drain region on the back side through the N-type epitaxy, namely the N-type columns, and the N-type epitaxy at the bottoms of the N-type columns and flow to the drain electrode formed by the metal layer on the back side, and therefore conducting current is formed.
In the prior art, in order to reduce the on-resistance, a certain amount of N-type ions, such as phosphorus ions, are generally implanted into the N-type region between two adjacent P-type wells to form a region with a higher concentration than the N-type epitaxial layer, thereby reducing the on-resistance (Rdson) of the device.
In order to reduce the switching loss of the device, it is effective to reduce the reverse conducting capacitance (Crss), which is equal to the gate-drain capacitance (Cgd). In order to reduce Cgd, one of the most straightforward ways to reduce the footprint of the gate and JFET regions, a device is designed with a planar gate designed as a split-gate structure, i.e., a split-gate planar gate is used.
In the prior art, after a split-gate planar gate is adopted, JFET ion implantation is carried out once in order to reduce the on-resistance of a device, in the prior art, the JFET ion implantation is placed after polysilicon gate etching is finished, N + ion implantation of a source region is carried out after the JFET ion implantation is finished, then an activation process is carried out, activation of the source region and the JFET region is simultaneously realized through the activation process, the activation temperature is generally 900-950 ℃, in the prior art, the JFET region and the N + source region are subjected to basically the same thermal process, the diffusion effect of the process on the JFET region is limited, the Rdson of the device can be influenced, and meanwhile, the electric field intensity of the JFET region is improved due to the high concentration of the JFET region, and the reliability of the device can be influenced.
The transition region is provided with a P-type ring region connected with the P-type well of the current flowing region, the P-type region is provided with a contact hole, and a high-concentration P + contact region is also arranged below the contact hole; the P-type ring is thus contacted by the P + contact region and the top contact hole and connected to the source electrode consisting of the front metal layer through the top contact hole; thus, the P-type ring and the P-well in the current flow region and the source region are connected to the source.
The termination region is used for bearing voltage between the source region and the drain region in the transverse direction, and in a common super junction MOSFET device, the termination region is mainly composed of P-N columns which are arranged alternately, or a cut-off region composed of an N + region is arranged outside the P-N columns which are arranged alternately. When reverse bias is applied between the source region and the drain region, carriers in the alternating P-N columns are mutually depleted to form a depletion region for bearing the transverse voltage. In order to improve the competitiveness of the device, the minimum terminal size is required, so that the transverse electric field intensity of the P-N column is increased, and the design of the terminal of the device is more important.
The N + cut-off region is a high-concentration N-type region, so that P-N columns in the terminal region of the device are mutually depleted, an N-epitaxial layer close to the N + region is completely depleted, and when the N + region is contacted, a spike of electric field intensity (local electric field intensity is increased) can occur, so that electric leakage of the device is increased, and soft breakdown occurs.
In addition, since the specific on-resistance of a super junction device such as a super junction MOSFET is reduced, the area of a chip of the device adapted to a certain current is continuously reduced, and how to improve the current impact resistance of the device is also a challenge.
Disclosure of Invention
The invention aims to solve the technical problem of providing a super junction device, which can realize a split-gate planar gate structure to reduce the gate-drain capacitance of the device and can realize better diffusion of a JFET (junction field effect transistor) area of the super junction device with the split-gate planar gate structure, thereby reducing the on-resistance of the device and improving the reliability of the device without increasing the process cost; soft breakdown at the cut-off region can be prevented, and the current surge resistance of the device can be improved. Therefore, the invention also provides a manufacturing method of the super junction device.
In order to solve the technical problem, in the super junction device provided by the invention, the middle area of the super junction device is a current flowing area, the terminal area surrounds the periphery of the current flowing area, and the transition area is positioned between the current flowing area and the terminal area; a protective epoxy film formed by photolithographic etching of the first oxide film opens the current flow region and covers the transition region and the termination region within the cut-off region composed of the N + region.
The current flowing region includes the following structure:
the N-type epitaxial layer is subjected to dry etching to form a plurality of grooves; and filling a P-type epitaxial layer in the groove to form a P-type column, forming an N-type column by the N-type epitaxial layer among the P-type columns, and forming a super junction structure by a plurality of alternately arranged N-type columns and P-type columns.
A P-type well is formed at the top of each P-type column and each P-type well extends to the surface of the N-type column on both sides of the corresponding P-type column.
A JFET region formed by JFET ion implantation and the JFET ion implantation region is defined by the guard ring oxide film in a self-aligned mode; the doping concentration of the JFET area is smaller than that of the P-type trap, the surface of the P-type trap with the superposed impurities of JFET ion implantation still keeps P-type doping, and the JFET area is located between the P-type traps in a self-aligning mode.
The split gate planar gate structure is formed by superposing a gate oxide film and a polysilicon gate; a super junction unit is formed by one N-type column and one adjacent P-type column, and two separated split gate plane gate structures are arranged above the N-type column of the same super junction unit.
Each polysilicon gate covers the corresponding P-type well and extends to the surface of the JFET area adjacent to the P-type well, and the surface of the P-type well covered by the polysilicon gate is used for forming a channel; the split-gate planar gate structure reduces the transverse overlapping area between the JFET area and the polysilicon gate, thereby reducing the gate-drain capacitance of the device.
And a source region consisting of an N + region is formed on the surface of the P-type well, and the source region and the side face of the polysilicon gate, which is positioned on the P-type well, are self-aligned.
The JFET ion implantation is carried out before the formation process of the gate oxide film, the gate oxide film is a thermal oxide film, the JFET region is provided with a structure which is subjected to annealing promotion through the thermal oxide process of the gate oxide film, and the thermal oxide process of the gate oxide film increases the diffusion region of the JFET region and can reduce the resistance of a drift region; the diffusion area of the JFET area is increased, and meanwhile, the area of the P-type trap forming the channel is reduced, so that the channel resistance can be reduced; the diffusion area of the JFET area is increased, so that the PN junction slow-changing effect formed by the JFET area and the P-type trap is increased, and the reliability of the device is improved; the threshold voltage required by the channel is determined by the P-type net doping concentration of the superposed JFET area and the P-type well, so that the doping concentration of the P-type well can be improved, and the current breakdown resistance of the device can be improved.
The super junction structure is also formed in the transition region and the termination region.
A P-type ring is formed in the transition region.
An electric field barrier layer which is formed in the terminal area and has the same process as the JFET area and is formed at the same time is formed in the terminal area, the doping concentration of the electric field barrier layer is lower than that of the cut-off area by more than 2 orders of magnitude, the electric field barrier layer is fully diffused under the action of the thermal process of the gate oxide film and fully surrounds the cut-off area in the longitudinal direction and the transverse direction, so that the depletion layer is prevented from contacting the cut-off area and stopping an electric field in the electric field barrier layer when the device is reversely biased, and the soft breakdown characteristic of the device is improved.
In a further improvement, the first oxide film has a thickness of
Figure BDA0001871924730000041
In a further improvement, the process temperature of the first oxide film is above 800 ℃.
In a further improvement, the thickness of the gate oxide film is
Figure BDA0001871924730000042
The thickness of the polysilicon gate is
Figure BDA0001871924730000043
The further improvement is that the conditions of the thermal oxidation process of the gate oxide film are as follows: the process temperature is 1050 ℃, the time of the oxide film deposition process is 60 minutes, the temperature rising rate from 800 ℃ to 1050 ℃ is 5 ℃/minute, and the temperature reduction rate from 1050 ℃ to 800 ℃ is 2 ℃/minute.
The further improvement is that the process conditions of the JFET ion implantation are as follows: the implanted impurity is phosphorus, and the implantation dosage is 1E12cm-2～4E12cm-2The implantation energy is 30Kev to 100 Kev.
Or, the JFET ion implantation is divided into two times with different implantation energies, and the implantation energy distribution corresponding to the two times of implantation is as follows: 30 Kev-60 Kev and 500 Kev-1.5 MeKev, the implantation impurities are all phosphorus, and the implantation dosage is all 1E12cm-2～4E12cm-2。
The further improvement is that the process conditions of the ion implantation of the P-type well are as follows: the implantation impurity is boron, and the implantation dosage is 3E13cm-2～1E14cm-2The implantation energy is 30Kev to 100 Kev.
The forming process of the P-type ring and the forming process of the P-type well are the same and are formed simultaneously; or, the P-type ring is formed by one time of photoetching definition and P-type ion implantation.
The further improvement is that the process conditions of the ion implantation of the source region are as follows: the implantation impurity is phosphorus or arsenic, and the implantation dosage is 3E15cm-2～8E15cm-2The injection energy is 30 Kev-100 Kev; and performing rapid thermal annealing activation after the ion implantation of the source region is completed, wherein the rapid thermal annealing process conditions corresponding to the source region are as follows: the annealing temperature is 1000-1100 ℃, and the annealing time is 15-30 s;
the forming process of the cut-off region and the source region is the same and formed simultaneously.
In order to solve the technical problem, in the manufacturing method of the super junction device provided by the invention, the middle area of the super junction device is a current flowing area, the terminal area surrounds the periphery of the current flowing area, and the transition area is positioned between the current flowing area and the terminal area; the method is characterized by comprising the following steps:
forming an N-type epitaxial layer on an N-type semiconductor substrate, forming a plurality of grooves in the N-type epitaxial layer by adopting a photoetching definition and dry etching process, filling P-type epitaxial layers in the grooves to form P-type columns, forming N-type columns by the N-type epitaxial layers among the P-type columns, and forming a super junction structure by the N-type columns and the P-type columns which are alternately arranged; the super junction structure is formed in the current flow region, the transition region, and the termination region.
Step two, forming a P-type trap on the top of each P-type column in the current flowing region, wherein each P-type trap extends to the surface of the N-type column on two sides of the corresponding P-type column; a P-type ring is formed in the transition region.
Forming a first oxide film on the surface of the semiconductor substrate, and etching the first oxide film by adopting a photoetching definition and oxide film etching process to form a protective ring oxide film; the protective epoxy film opens the current flow region and covers the transition region and the termination region within a subsequently formed cut-off region.
Taking the protective epoxy film as a self-aligned mask, performing JFET ion implantation to form a JFET region in the current flowing region in a self-aligned mode, and forming an electric field barrier layer on the outermost side of the terminal region; the doping concentration of the JFET area is smaller than that of the P-type trap, the surface of the P-type trap with the superposed impurities of JFET ion implantation still keeps P-type doping, and the JFET area is located between the P-type traps in a self-aligning mode.
Forming a gate oxide film by adopting a thermal oxidation process, and then forming a polysilicon gate; annealing and propelling the impurities of the JFET region and the electric field barrier layer by the thermal oxidation process of the gate oxide film by utilizing the characteristic that the JFET ion implantation is placed before the thermal oxidation process of the gate oxide film, so that the diffusion regions of the JFET region and the electric field barrier layer are increased; the drift region resistance can be reduced by increasing the diffusion region of the JFET region; the diffusion area of the JFET area is increased, and meanwhile, the area of a channel formed by the P-type trap is reduced, so that the channel resistance can be reduced; the increase of the diffusion area of the JFET area also increases the PN junction slow-changing effect formed by the JFET area and the P-type trap, and improves the reliability of the device.
And step six, etching the polysilicon gate and the gate oxide film in sequence by adopting a photoetching definition and etching process to form the split gate planar gate structure formed by overlapping the etched gate oxide film and the polysilicon gate.
The split-gate planar gate structure is positioned in the current flowing area, and a super junction unit is formed by one N-type column and one adjacent P-type column; in the current flowing region, two separated split-gate planar gate structures are arranged above the N-type column of the same super junction unit; the polysilicon gate corresponding to each split gate planar gate structure covers the corresponding P-type well and extends to the surface of the JFET area adjacent to the P-type well, and the surface of the P-type well covered by the polysilicon gate is used for forming a channel; the split-gate planar gate structure reduces the transverse overlapping area between the JFET area and the polysilicon gate, thereby reducing the gate-drain capacitance of the device.
Seventhly, photoetching and N + ion implantation are adopted, a source region formed by an N + region is formed on the surface of the P-type trap in the current flowing region, a cut-off region is formed on the outermost side of the terminal region, and the source region and the side face, located on the P-type trap, of the polysilicon gate are self-aligned.
The doping concentration of the electric field barrier layer is lower than that of the cut-off region by more than 2 orders of magnitude, the cut-off region is fully surrounded by the electric field barrier layer in the longitudinal direction and the transverse direction, so that a depletion layer is prevented from contacting the cut-off region when the device is reversely biased, an electric field is stopped in the electric field barrier layer, and the soft breakdown characteristic of the device is improved.
In a further improvement, in the third step, the thickness of the first oxide film is
Figure BDA0001871924730000061
The process temperature of the first oxide film is above 800 ℃.
In a further improvement, the thickness of the gate oxide film formed in the fifth step is
Figure BDA0001871924730000062
The thickness of the polysilicon gate is
Figure BDA0001871924730000063
The further improvement is that the conditions of the thermal oxidation process of the gate oxide film are as follows: the process temperature is 1050 ℃, the time of the oxide film deposition process is 60 minutes, the temperature rising rate from 800 ℃ to 1050 ℃ is 5 ℃/minute, and the temperature reduction rate from 1050 ℃ to 800 ℃ is 2 ℃/minute.
The further improvement is that, in the fourth step, the process conditions of the JFET ion implantation are as follows: the implanted impurity is phosphorus, and the implantation dosage is 1E12cm-2～4E12cm-2The implantation energy is 30Kev to 100 Kev.
Or, the JFET ion implantation is divided into two times with different implantation energies, and the implantation energy distribution corresponding to the two times of implantation is as follows: 30 Kev-60 Kev and 500 Kev-1.5 MeKev, the implantation impurities are all phosphorus, and the implantation dosage is all 1E12cm-2～4E12cm-2。
In a further improvement, in the second step, the ion implantation of the P-type well is performedThe process conditions are as follows: the implantation impurity is boron, and the implantation dosage is 3E13cm-2～1E14cm-2The implantation energy is 30Kev to 100 Kev.
The P-type ring is formed simultaneously by the same process as the P-type well; or, the P-type ring is formed by one time of photoetching definition and P-type ion implantation.
In a further improvement, in the seventh step, the process conditions of the ion implantation of the source region are as follows: the implantation impurity is phosphorus or arsenic, and the implantation dosage is 3E15cm-2～8E15cm-2The injection energy is 30 Kev-100 Kev; and performing rapid thermal annealing activation after the ion implantation of the source region is completed, wherein the rapid thermal annealing process conditions corresponding to the source region are as follows: the annealing temperature is 1000-1100 ℃, and the annealing time is 15-30 s.
The invention can obtain the following beneficial technical effects:
in a current flowing area, the super junction device combines a split-gate planar gate structure and a process structure of a JFET area, and the split-gate planar gate structure can realize smaller coverage on the JFET area, so that the gate-drain capacitance of the device can be reduced, and the switching loss of the device can be reduced.
The process structure of the JFET area has the structure that annealing diffusion is carried out by adopting the thermal process of the gate oxide film, the process of JFET ion injection only needs to be placed before the formation process of the gate oxide film in the process, and the thermal process of the gate oxide film has higher temperature and longer time and also comprises a longer temperature rise and fall process, so that the thermal process of the gate oxide film can well diffuse the JFET area, the diffusion effect of the JFET area is improved, and the improvement of the diffusion effect of the JFET area can obtain the following beneficial technical effects:
1. the JFET area is diffused more, so that the range of the JFET area is enlarged, or the range of the surface high-concentration area is enlarged, the on-resistance of the device can be reduced, the JFET area belongs to the drift area of the super junction device on the whole, and the reduced on-resistance of the JFET area corresponds to the resistance of the drift area.
2. Because more diffusion of the JFET area is achieved, the channel length of the super junction device is shortened, and therefore the on-resistance of the device can be reduced; the decrease in on-resistance due to the decrease in channel length mainly corresponds to the decrease in channel resistance.
3. As the JFET area is diffused more, the P-type trap near the interface of the gate oxide film and the silicon and the PN junction formed by the JFET area become more gradual, the electric field intensity under the reverse bias condition of the device at the position can be reduced, the electric leakage of the device is reduced, and the reliability of the device is improved.
In addition, the injection area of JFET ion injection directly adopts the self-alignment definition of the guard ring oxide film, and the self-alignment definition has lower process cost; meanwhile, the guard ring oxide film is also commonly called a G-field oxide film, the thickness of the guard ring oxide film is thicker, and is usually 8000-15000 angstroms, and the guard ring oxide film is used as a mask for JFET ion implantation, so that higher ion implantation energy can be borne, and the design of the device is more convenient. In the prior art, JFET ion implantation is performed after a grid structure comprises a superposed layer structure of a grid oxide film and a polysilicon grid is formed, and the thickness of the superposed layer of the grid oxide film and the polysilicon grid is generally 5000-6000 angstroms and is obviously lower than that of a protection ring oxide film, so that the adjustment of the implantation energy of the JFET ion implantation is easier, and the design of a device is more convenient.
In addition, the convenience improvement of the process conditions of the ion implantation of the JFET region and the improvement of the diffusion effect of the JFET region are realized only by elaborately designing the forming process of the JFET region without adding other additional process cost, so the method also has the characteristic of low process cost.
In the terminal area, an electric field barrier layer which is formed by adopting the same process as the JFET area and is formed at the same time is formed on the outermost side of the terminal area, and the doping concentration of the electric field barrier layer is lower than that of the cut-off area by more than 2 orders of magnitude, so that the depletion layer is prevented from contacting the cut-off area when the device is reversely biased, the soft breakdown characteristic of the device can be improved, the leakage current under reverse bias can be reduced, and the reliability of the device can be improved;
meanwhile, the electric field barrier layer is fully diffused under the action of the thermal process of the gate oxide film and fully surrounds the cut-off region in the longitudinal direction and the transverse direction, so that an electric field can be stopped in the electric field barrier layer, and the electric field barrier layer is helpful for improving the breakdown voltage, the current impact resistance and the like of a device.
In the current flowing area, the threshold voltage corresponding to the channel formed by the super junction device is determined by the surface net doping concentration of the P-type trap, and the N-type JFET area is superposed in the surface of the P-type trap, so that in order to keep the threshold voltage the same as that of a device without the JFET area, the depth and the impurity concentration of the P-type trap can be integrally increased, and the current impact resistance of the device can be improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a top view of a superjunction device of an embodiment of the present invention;
fig. 2 is a schematic cross-sectional view of a superjunction device of an embodiment of the present invention;
fig. 3A-3H are schematic cross-sectional views of a superjunction device at various steps of a method of manufacturing the superjunction device according to an embodiment of the present invention;
fig. 4A is a structural simulation diagram of a device cell of a current flow region of a conventional superjunction device;
fig. 4B is a structural simulation diagram of the device cells of the current flow region of the superjunction device of an embodiment of the present invention;
fig. 5 is an impurity concentration profile of a JFET region and a P-well of a superjunction device of an embodiment of the present invention and a conventional superjunction device.
Detailed Description
As shown in fig. 1, is a top view of a super junction device according to an embodiment of the present invention; the general super junction device structure comprises a current flowing region, a terminal region which is transversely subjected to reverse bias voltage and a transition region which is arranged between the current flowing region and the terminal region, wherein the terminal region surrounds the periphery of the current flowing region, and in the figure 1, a region 1 represents the current flowing region, a region 2 represents the transition region, and a region 3 represents the terminal region.
Region 1 includes a super junction structure composed of alternately arranged P-type columns 22 and N-type columns 23, and both P-type columns 22 and N-type columns 23 in fig. 1 have a stripe structure. N-type column 23 provides a conduction path when the superjunction device is turned on, and P-type column 22 and N-type column 23 are mutually depleted when the superjunction device is reversely biased to commonly bear a reverse bias.
And the area 2 and the area 3 are positioned at the terminal of the super junction device and are used as a terminal protection structure for representing the super junction device together. The regions 2 and 3 provide no current when the device is turned on, and in a reverse bias state are used to bear a voltage from the surface of the region 1 peripheral cell to the substrate at the outermost end surface of the device, which is a lateral voltage, and a voltage from the surface of the region 1 peripheral cell to the substrate, which is a vertical voltage.
There is at least one P-type ring 25 in region 2, fig. 1 is a P-type ring 25, and the P-type ring 25 is typically connected to the back gate P-type well in region 1; in the prior art, a field plate dielectric film with a certain inclination angle is generally arranged in the region 2, a field plate 24 for slowing down the abrupt change of a surface electric field is also arranged in the region 2, and the field plate 24 is a polycrystalline field plate or a metal field plate and a P-type column 22; the metal field plate may not be provided in region 2.
Region 3 includes a super junction structure composed of alternately arranged P-type columns 22 and N-type columns 23, and in fig. 1, P-type columns 22 and N-type columns 23 in region 3 are respectively formed by extending and expanding P-type columns 22 and N-type columns 23 in region 1, and the alternately arranged directions are the same. In other configurations, the 3-zone P-type pillars 22 and N-type pillars 23 can also be in an end-to-end ring-type configuration.
A metal field plate is arranged in the region 3, and the metal field plate is not arranged in the region 3; there may or may not be a P-type ring 25 in the 3 region, where the P-type ring is not connected (floating) to the P-type back gate connection of the current flow region in the presence of the P-type ring 25; and a terminal stop ring 21 is arranged at the outermost end of the 3 region, and the terminal stop ring 21 is composed of an N + injection region or an N + injection region and a medium formed on the N + injection region or the medium and a metal.
Fig. 2 is a schematic cross-sectional view of a superjunction device according to an embodiment of the present invention; the middle area of the super junction device is a current flowing area, namely an area 1, a terminal area, namely an area 3, surrounds the periphery of the current flowing area, and a transition area, namely an area 2, is positioned between the current flowing area and the terminal area; the protective epoxy film 7 formed by photolithographic etching of the first oxide film 7 opens the current flow region and covers the transition region and the termination region within the cut-off region 110b composed of the N + region.
The current flowing region includes the following structure:
the N-type epitaxial layer 2 is subjected to dry etching to form a plurality of trenches 41, and the marks of the trenches 41 refer to fig. 3A; the trench 41 is filled with a P-type epitaxial layer and constitutes P-type columns 51, N-type columns 2 are constituted by the N-type epitaxial layer 2 between the P-type columns 51, and a super junction structure is constituted by a plurality of alternately arranged N-type columns 2 and P-type columns 51. In fig. 2, the N-type columns are also denoted by reference numeral 2 corresponding to the N-type epitaxial layer.
One P-type well 6 is formed at the top of each P-type pillar 51 and each P-type well 6 extends to the surface of the N-type pillar 2 on both sides of the corresponding P-type pillar 51.
A JFET region 10a, the JFET region 10a being formed by JFET ion implantation and an area of the JFET ion implantation being defined by the protective epoxy film 7 in self-alignment; the doping concentration of the JFET region 10a is smaller than that of the P-type trap 6, the surface of the P-type trap 6 with the superposed impurities of JFET ion implantation still keeps P-type doping, and the JFET region 10a is located between the P-type traps 6 in a self-aligning mode.
The split gate planar gate structure is formed by superposing a gate oxide film 8 and a polysilicon gate 9; a super junction unit is composed of one N-type column 2 and an adjacent P-type column 51, and two separated split gate planar gate structures are included above the N-type column 2 of the same super junction unit.
Each polysilicon gate 9 covers the corresponding P-type well 6 and extends to the surface of the JFET region 10a adjacent to the P-type well 6, and the surface of the P-type well 6 covered by the polysilicon gate 9 is used for forming a channel; the split-gate planar gate structure reduces the lateral overlapping area between the JFET region 10a and the polysilicon gate 9, thereby reducing the gate-drain capacitance of the device.
A source region 110a composed of an N + region is formed on the surface of the P-well 6 and the source region 110a and the side of the polysilicon gate 9 on the P-well 6 are self-aligned.
The JFET ion implantation is carried out before the formation process of the gate oxide film 8, the gate oxide film 8 is a thermal oxide film, the JFET region 10a is made to have a structure which is subjected to annealing promotion through the thermal oxide process of the gate oxide film 8, and the thermal oxide process of the gate oxide film 8 enables the diffusion area of the JFET region 10a to be increased, so that the drift region resistance can be reduced; the diffusion area of the JFET area 10a is increased, and the area of the P-type well 6 for forming the channel is reduced, so that the channel resistance can be reduced; the diffusion area of the JFET area 10a is increased, so that the PN junction slow-changing effect formed by the JFET area 10a and the P-type well 6 is increased, and the reliability of the device is improved; the threshold voltage required for forming the channel is determined by the P-type net doping concentration of the superposed JFET area 10a and the P-type well 6, so that the doping concentration of the P-type well 6 can be increased, and the current breakdown resistance of the device can be improved.
The super junction structure is also formed in the transition region and the termination region. As shown in fig. 1, the P-type column and the N-type column of the super junction structure in the transition region and the termination region are both extended from the corresponding P-type column and N-type column in the current flowing region. As shown in fig. 2, it can be seen that a plurality of trenches 41,42,43 are formed in the N-type epitaxial layer 2, and the marks of the trenches are shown in fig. 3A; the trenches 41,42,43 are filled with a P-type epitaxial layer and form P- type columns 51,52,53, an N-type column is formed by the N-type epitaxial layer 2 between the P- type columns 51,52,53, and a super junction structure is formed by a plurality of alternately arranged N-type columns and P- type columns 51,52, 53. The super junction structure is located in the current flow region, the transition region, and the termination region.
In the super junction device of the embodiment of the present invention, in order to clearly distinguish the trenches and the P-type columns in the region 1, the region 2, and the region 3, the trenches in each region are separately marked, specifically: trench 41 is a trench formed in region 1, trench 42 is a trench formed in region 2, and trench 43 is a trench formed in region 3; p-type column 51 is a P-type column formed in region 1, P-type column 52 is a P-type column formed in region 1, and P-type column 53 is a P-type column formed in region 1. The width may be set to be different between different trenches, where Wp1 in fig. 3A indicates the width of trench 41, which is also the width of subsequent P-type pillar 51; wp2 indicates the width of trench 42, which is also the width of subsequent P-type pillar 52, Wp3 indicates the width of trench 43, which is also the width of subsequent P-type pillar 53; wn1 denotes the width of the N-type pillars in the region 1, Wn2 denotes the width of the N-type pillars in the region 2, and Wn3 denotes the width of the N-type pillars in the region 3.
A P-type ring 6a is formed in the transition region.
An electric field barrier layer 10b which is formed in the terminal region by the same process as the JFET region 10a and is formed at the same time is formed, the doping concentration of the electric field barrier layer 10b is lower than that of the cut-off region 110b by more than 2 orders of magnitude, the electric field barrier layer 10b is fully diffused under the action of the thermal process of the gate oxide film 8 and fully surrounds the cut-off region 110b in the longitudinal direction and the transverse direction, so that the depletion layer is prevented from contacting the cut-off region 110b and the electric field is stopped in the electric field barrier layer 10b when the device is reversely biased, and the soft breakdown characteristic of the device is improved.
In the embodiment of the present invention, the thickness of the first oxide film 7 is
Figure BDA0001871924730000111
The process temperature of the first oxide film 7 is 800 ℃ or higher.
The thickness of the gate oxide film 8 is
Figure BDA0001871924730000112
The thickness of the polysilicon gate 9 is
Figure BDA0001871924730000113
Figure BDA0001871924730000114
The conditions of the thermal oxidation process of the gate oxide film 8 are as follows: the process temperature is 1050 ℃, the time of the oxide film deposition process is 60 minutes, the temperature rising rate from 800 ℃ to 1050 ℃ is 5 ℃/minute, and the temperature reduction rate from 1050 ℃ to 800 ℃ is 2 ℃/minute.
The process conditions of the JFET ion implantation are as follows: the implanted impurity is phosphorus, and the implantation dosage is 1E12cm-2～4E12cm-2The implantation energy is 30 Kev-100 Kev. Or, the JFET ion implantation is divided into two times with different implantation energies, and the implantation energy distribution corresponding to the two times of implantation is as follows: 30 Kev-60 Kev and 500 Kev-1.5 MeKev, the implantation impurities are all phosphorus, and the implantation dosage is all 1E12cm-2～4E12cm-2. In the embodiment of the invention, the JFET ion implantation adopts the protective epoxy film as a self-aligned defined mask, and the protective epoxy film is thicker, so that the JFET ion implantation can adopt higher implantation energy, and the process adjustment of the JFET ion implantation is facilitated.
The process conditions of the ion implantation of the P-type well 6 are as follows: the implantation impurity is boron, and the implantation dosage is 3E13cm-2～1E14cm-2The implantation energy is 30Kev to 100 Kev. The P-type ring 6a is formed simultaneously with the P-type well 6 by the same process. In other embodiments can also be: the P-type ring 6a is formed by one-time photoetching definition and P-type ion implantation.
The process conditions of the ion implantation of the source region 110a are as follows: the implantation impurity is phosphorus or arsenic, and the implantation dosage is 3E15cm-2～8E15cm-2The injection energy is 30 Kev-100 Kev; after the ion implantation of the source region 110a is completed, rapid thermal annealing activation is performed, and the process conditions of the rapid thermal annealing corresponding to the source region 110a are as follows: the annealing temperature is 1000-1100 ℃, and the annealing time is 15-30 s. The formation processes of the cut-off region 110b and the source region 110a are the same and are formed at the same time.
As shown in fig. 2, in the current flowing region, the superjunction device further includes the following front structure:
the interlayer film 11, the contact hole 121a, the source electrode 14a composed of the front metal layer, and the gate electrode (not shown).
The contact hole 121a passes through the interlayer film 11. The source region 110a is connected to the source electrode 14a through the top corresponding contact hole 121a, and the polysilicon gate 17 is connected to the gate electrode through the top corresponding contact hole 121 a.
The thickness of the interlayer film 11 is 8000 a to 10000 a,
the contact hole 121a corresponding to the top of the source region 110a also passes through the source region 110a to contact the P-type well 14 at the bottom, and a P + doped well contact region 13 is formed at the bottom of the contact hole 121a corresponding to the source region 110 a.
The super junction device further comprises a back structure:
the N-type epitaxial layer 2 is formed on the surface of the semiconductor substrate 1, the silicon substrate 1 adopts an N-type heavily doped structure and directly forms a drain region of the super junction device, and a drain electrode consisting of a back metal layer 15 is formed on the back of the drain region 1.
In the transition region, the P-type ring 6a is connected to the source 14a through a contact hole 121 b.
In the termination region, a polysilicon field plate 9a is also formed on the surface of the protective epoxy film 7, the polysilicon field plate 9a being connected to an electrode 14b composed of a front-side metal layer through a contact hole, the electrode 14b being able to be a gate electrode.
A contact hole 121c is formed at the top of the cut-off region 110b and connected to the electrode 14c composed of the front metal layer through the contact hole 121c, and a well contact region 13 is formed at the bottom of the contact hole 121 c.
The N-type epitaxial layer 2 can be a single layer, and the N-type impurity concentration is consistent. The N-type epitaxial layer 2 may also be a double layer or a multilayer, and is composed of different impurity concentrations, or the impurity concentrations are continuously changed, or are changed in a stepwise manner, so as to meet the requirements on the performance in the device design.
In the super junction device of the embodiment of the invention, a 600V N-type super junction MOSFET is taken as an example for detailed description of parameters:
the resistivity of the semiconductor substrate 1 is 0.001-0.003 ohm cm; the resistance of the N-type epitaxial layer 2 is 1-2 ohm cm, and the thickness is 45-60 micrometers. In the embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate, and the N-type epitaxial layer 2 is a silicon epitaxial layer.
The depth of the grooves corresponding to the P-type columns is usually 40-45 micrometers, the width of the grooves is 4 micrometers, and the distance between the grooves is 5 micrometers. A buffer layer is formed between the bottom of the trench and the semiconductor substrate 1, and generally, the buffer layer is directly composed of the N-type epitaxial layer 2, the thickness of the buffer layer, i.e., T1 in fig. 3A, can be 5 micrometers, and the super junction device has better current impact resistance by arranging the buffer layer.
The embodiment of the invention can obtain the following beneficial technical effects:
firstly, in a current flowing area, the super junction device disclosed by the embodiment of the invention combines a split-gate planar gate structure and a process structure of the JFET area 10a, and the split-gate planar gate structure can realize smaller coverage on the JFET area 10a, so that the gate-drain capacitance of the device can be reduced, and the switching loss of the device can be reduced.
The process structure of the JFET area 10a in the embodiment of the invention has a structure for annealing and diffusing by adopting the thermal process of the gate oxide film 8, and can be realized only by placing the JFET ion injection process before the formation process of the gate oxide film 8, and because the thermal process of the gate oxide film 8 has higher temperature and longer time and also comprises a longer temperature rise and fall process, the thermal process of the gate oxide film 8 can well diffuse the JFET area 10a, the diffusion effect of the JFET area 10a is improved, and the improvement of the diffusion effect of the JFET area 10a can obtain the following beneficial technical effects:
1. since the JFET region 10a is more diffused, the range of the JFET region 10a is enlarged, or the range of the surface high concentration region is enlarged, so that the on-resistance of the device can be reduced, the JFET region 10a as a whole belongs to the drift region of the superjunction device, and the reduced on-resistance of the JFET region 10a corresponds to the drift region resistance.
2. Because more diffusion of the JFET area 10a is achieved, the channel length of the super junction device is shortened, and therefore the on-resistance of the device can be reduced; the decrease in on-resistance due to the decrease in channel length mainly corresponds to the decrease in channel resistance.
3. Since the JFET region 10a is more diffused, the PN junction formed by the P-well 6 and the JFET region 10a near the interface between the gate oxide film 8 and the silicon becomes more gradual, which reduces the electric field strength at this location under reverse bias conditions of the device, reduces the leakage of the device, and improves the reliability of the device.
In addition, the injection area of JFET ion injection in the embodiment of the invention is directly defined by self-alignment of the guard ring oxide film 7, and the self-alignment definition has lower process cost; meanwhile, the protective epoxidation film 7 is also commonly called a G-field oxide film, the protective epoxidation film 7 is thicker, generally 8000-15000 a, and the protective epoxidation film 7 is used as a mask for JFET ion implantation to bear higher ion implantation energy, so that the design of the device is more convenient. In the prior art, JFET ion implantation is performed after a grid structure comprising a superposed layer structure of a grid oxide film 8 and a polysilicon grid 9 is formed, and the thickness of the superposed layer of the grid oxide film 8 and the polysilicon grid 9 is generally 5000-6000 angstroms and is obviously lower than that of a protection ring oxide film 7, so that the adjustment of the implantation energy of the JFET ion implantation is easier and the design of a device is more convenient.
In addition, the convenience improvement of the process conditions of the ion implantation of the JFET region 10a and the improvement of the diffusion effect of the JFET region 10a according to the embodiment of the present invention are realized only by elaborately designing the formation process of the JFET region 10a, and other additional process costs are not required to be added, so the present invention also has the characteristic of low process costs.
In the terminal region, an electric field barrier layer 10b which is formed by adopting the same process as the JFET region 10a and is formed at the same time is formed on the outermost side of the terminal region, and the doping concentration of the electric field barrier layer 10b is lower than that of the cut-off region 110b by more than 2 orders of magnitude, so that the depletion layer is prevented from contacting the cut-off region 110b when the device is reversely biased, the soft breakdown characteristic of the device can be improved, the leakage current under reverse bias can be reduced, and the reliability of the device can be improved;
meanwhile, the electric field barrier layer 10b is fully diffused under the action of the thermal process of the gate oxide film 8 and fully surrounds the cut-off region 110b in the longitudinal direction and the transverse direction, so that an electric field can be stopped in the electric field barrier layer 10b, and the electric field barrier layer is helpful for improving the breakdown voltage, the current impact resistance and the like of a device.
In the current flowing region, the threshold voltage corresponding to the channel formed by the super junction device is determined by the net doping concentration of the surface of the P-type well 6, and the N-type JFET region 10a is superposed on the surface of the P-type well 6, so that in order to keep the threshold voltage the same as that of a device without the JFET region 10a, the depth and the impurity concentration of the P-type well 6 are integrally increased, and the current impact resistance of the device can be improved.
The differences between the devices of the embodiments of the present invention and existing superjunction devices will now be described with reference to the accompanying drawings:
as shown in fig. 4A, which is a simulation diagram of the structure of the device unit of the current flowing region of the existing superjunction device, the forming process of the JFET region 10a of the existing superjunction device is formed by self-aligned definition of the polysilicon gate 9, so that the forming process of the JFET region 10a of the existing superjunction device is placed after the forming process of the gate oxide film 8, and the JFET10a is activated and diffused by using the same annealing condition as the source region 110 a.
As shown in fig. 4B, is a structural simulation diagram of a device unit in a current flowing region of the superjunction device according to the embodiment of the present invention; in FIG. 4A, the abscissa is the X coordinate in microns; the ordinate is the Y-coordinate, in microns. The same reference numerals as in fig. 2 are used for the respective regions in fig. 4A. Different depths of color are also used in fig. 4A to indicate different doping concentrations, and the colors of different depths after printing in black and white in fig. 4A correspond to colors of different grayscales. DopingConcentration means doping concentration and NetActive means net doping in cm-3。
It can be seen that the diffusion area of the JFET region 10a of the superjunction device of the embodiment of the present invention becomes large, as shown in:
the depth Da of the JFET region 10a of the device is larger than the depth Db of the JFET region 10a of the conventional device, and the width La of the JFET region 10a of the device of the embodiment of the invention, which is diffused to the bottom of the polysilicon gate 17, is larger than the width Lb corresponding to the JFET region 10a of the conventional device. Therefore, the embodiment of the invention enables the JFET area 10a of the device to be more fully diffused without adding processes.
As shown in fig. 5, the curves of the impurity concentration distribution of the JFET region and the P-well of the superjunction device according to the embodiment of the present invention and the conventional superjunction device are shown, where the curve 101 corresponds to the curve of the device according to the embodiment of the present invention, and the curve 102 is the curve of the conventional device. It can be seen that:
the area corresponding to width d2 is JFET region 10a of the device of the present embodiment; the area corresponding to the width d1 is the P-type well 6 of the device of the embodiment of the invention.
The area corresponding to the width d102 is the JFET area 10a of the existing device; the region corresponding to the width d101 is the P-well 6 of the conventional device.
The width d1 is about 1.2 microns, and the width d101 is about 1.7 microns, so that the surface of the P-type well 6 covered by the polysilicon gate 17 is used for forming a channel, the channel length of the device of the embodiment of the invention is reduced, and the on-resistance of the channel part is reduced.
Meanwhile, the JFET area 10a of the device in the embodiment of the invention is diffused more; the width d2 of the JFET region 10a for half of the original package is about 1.1 microns greater than the width d102 for the prior device, and the width d102 is about 0.35 microns, which further reduces the on-resistance of the JFET region.
As can be seen from the comparison of fig. 4A, 4B and 5, in the device according to the embodiment of the present invention, the PN junction formed by the P-well and the JFET region becomes more gradual, the electric field strength near the junction under the reverse bias condition of the device is reduced, the leakage characteristic of the device is reduced, and the reliability of the device is improved.
In fig. 2, the N jfet region, i.e., the electric field blocking layer 10b, in the off region 110b has a diffusion width and a diffusion depth larger than those of the N + region, i.e., the off region 110b, and the N jfet region surrounds the N + region, and it can be seen that 60Kev is used in the N jfet region, 2E12cm-2In the case of (1), the concentration of the diffused NJFET region is 1cm-3～3e16cm-3Impurity concentration 5E15cm significantly higher than that of N epitaxial layer 2-3But much lower than the impurity concentration of the N + region by 1cm-3～2E20cm-3. The NJFET region 10b forms an electric field blocking layer 10b or a buffer layer between the N-type epitaxial layer 2 with low concentration and the N + region 110b with extremely high concentration, when reverse bias is carried out between the drain electrode and the source electrode of the device, and P-N columns in the terminal region are mutually depleted, the depletion layer can be prevented from contacting the N + region 110b under many conditions, so that the soft breakdown characteristic of the device is improved, and the electric leakage of the device is reduced.
The JFET ion implantation of the embodiment of the invention is arranged after photoetching and etching of the protective ring field oxide film 7, and the current flowing area is comprehensively implanted, so that impurities after implantation and diffusion of the P-type well 6 are arranged at the Si interface of the gate oxide film 8The quantity of JFET ion implantation needs to be removed to be the net impurity quantity of surface P-type impurities, and in order to obtain the same threshold voltage of a product, the implantation dosage of the P-type well needs to be improved, so that the depth and the impurity concentration of the P-type well are integrally increased, and the current impact resistance of the device is improved. For example, in a process flow, if there is no JFET ion implantation into the channel region, the implantation conditions for the P-well 6 can be 60Kev for a threshold voltage of 3.5V, and 5E13cm for a dose of 5E13-3(ii) a JFET ion implantation is carried out after Gfield, the implantation conditions are that the implanted impurity is phosphorus, the implantation energy is 60KEV, and the implantation dosage is 2E12cm-2In order to obtain a threshold voltage of 3.5V, the implantation conditions of the P-type well are 60Kev and 8E13cm-3(ii) a The implantation dosage of the P-type well is obviously increased, and the current resistance of the device is improved. The super junction device with the current of 600V4 amperes has the current impact resistance capability of 3A, which is obviously higher than that of 2A of the existing super junction device.
As shown in fig. 3A to fig. 3H, the cross-sectional views of the devices in the steps of the method for manufacturing the super junction device according to the embodiment of the present invention are schematic diagrams, the middle region of the super junction device in the method for manufacturing the super junction device according to the embodiment of the present invention is a current flowing region, a terminal region surrounds the periphery of the current flowing region, and a transition region is located between the current flowing region and the terminal region; the method comprises the following steps:
step one, as shown in fig. 3A, an N-type epitaxial layer 2 is formed on an N-type semiconductor substrate 1, and a plurality of trenches 41 are formed in the N-type epitaxial layer 2 by using a photolithography definition and dry etching process.
As shown in fig. 3B, P-type epitaxial layers are filled in the trenches 41 to form P-type columns 51, N-type columns 2 are formed by the N-type epitaxial layers 2 between the P-type columns 51, and a super junction structure is formed by a plurality of alternately arranged N-type columns 2 and P-type columns 51; the super junction structure is formed in the current flow region, the transition region, and the termination region. The trenches in the transition region are indicated by reference 42 and the P-type pillars are indicated by reference 52; the trench in the termination region is denoted by reference numeral 43 and the P-type column is denoted by reference numeral 53.
The N-type epitaxial layer 2 can be a single layer, and the N-type impurity concentration is consistent. The N-type epitaxial layer 2 may also be a double layer or a multilayer, and is composed of different impurity concentrations, or the impurity concentrations are continuously changed, or are changed in a stepwise manner, so as to meet the requirements on the performance in the device design.
In the method of the embodiment of the invention, the manufactured super junction device is an N-type super junction MOSFET with 600V as an example for detailed description: the N-type epitaxial layer 2 is formed on the surface of the semiconductor substrate 1, and the semiconductor substrate 1 adopts an N-type heavily doped structure; preferably, the N-type epitaxial layer 2 is a silicon epitaxial layer, and the semiconductor substrate 1 is a silicon substrate, which is also known as a silicon wafer or a silicon wafer. The drain region of the super junction MOSFET is usually formed on the back surface of the semiconductor substrate 1, so the heavily doped semiconductor substrate 1 is directly adopted, and in the method of the embodiment of the invention, the resistivity of the semiconductor substrate 1 is 0.001-0.003 ohm cm; the resistance of the N-type epitaxial layer 2 is 1-2 ohm cm, and the thickness is 45-60 micrometers. In the embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate, and the N-type epitaxial layer 2 is a silicon epitaxial layer.
In the method of the embodiment of the invention, the step of forming the super junction structure comprises the following steps:
a dielectric film 201 is deposited on the N-type epitaxial layer 2, a region needing a groove is defined through groove photoetching, and then the groove is formed through drying etching. After the trenches are formed, a P-type epitaxial layer such as a P-type silicon epitaxial layer is deposited in the trenches, and then the P-type epitaxial layer on the surface of the semiconductor substrate 1 is removed by Chemical Mechanical Polishing (CMP), so that the P-type columns are formed in the trenches. And then removing the dielectric film 201 on the surface or remaining the dielectric film.
The depth of the grooves corresponding to the P-type columns is usually 40-45 micrometers, the width of the grooves is 4 micrometers, and the distance between the grooves is 5 micrometers. A buffer layer is formed between the bottom of the trench and the semiconductor substrate 1, and generally, the buffer layer is directly composed of the N-type epitaxial layer 2, the thickness of the buffer layer can be 5 micrometers, for example, and the super junction device has better current impact resistance by arranging the buffer layer.
The dielectric film 201 can be a single oxide film, for example, an oxide film with a thickness exceeding 1 micron, the oxide film can be used as a hard mask during trench etching, after the trench is formed, an oxide film with a certain thickness is left, for example, an oxide film with a thickness of 0.1 micron to 0.2 micron, during the P-type epitaxial filling and the CMP, the oxide film is used as a protective layer of the N-type epitaxial layer 2 during the CMP, so that the N-type epitaxial layer 2 at the position is not affected by the CMP process to cause defects, and thus, leakage or quality problems are caused.
The dielectric film 201 can also be formed by overlapping a layer of oxide film with the thickness of 0.1-0.15 micron, a layer of SiN film with the thickness of 0.1-0.2 micron and a layer of oxide film with the thickness of more than 1 micron; this allows for better control of uniformity during the fabrication process: for example, after the trench etching is completed, at least a part of the SiN film remains on the oxide film thereunder, and before the P-type epitaxial growth, the SiN film is removed, so that the uniformity of the oxide film before the P-type epitaxial growth is good, and the uniformity of the subsequent epitaxial CMP can be improved.
In a further improvement of the dielectric film 201 formed by stacking the above-described multilayer films, the first oxide film is formed by thermal oxidation, which further improves uniformity.
Step two, as shown in fig. 3B, a P-type well 6 is formed at the top of each P-type pillar 51 in the current flowing region, and each P-type well 6 extends to the surface of the N-type pillar 2 on both sides of the corresponding P-type pillar 51. A P-type ring 6a is formed in the transition region.
In the method of the embodiment of the invention, the sub-steps of forming the P-type well 6 comprise:
a region of the P-well 6 is formed in the current flow region of the device by P-well lithography, followed by ion implantation to form the P-well 6. After the P-type well 6 is formed, a high temperature thermal process is performed to complete the drive-in, the temperature of the drive-in is generally higher than 1000 ℃, the time is generally longer than 30min, for example, an annealing process of 1100 ℃ for 120 min to 180 min is used to perform the drive-in.
The process condition of the P-type well 6 needs to meet the requirement of the threshold voltage of the device, and the requirement of the threshold voltage is2V-4V device, the process conditions of the ion implantation of the P-type trap 6 are as follows: the implantation impurity is B, the implantation energy is 30 Kev-100 Kev, and the implantation dosage is 3E13cm-2～1E14cm-2. Meanwhile, when the breakdown voltage of the device occurs, the channel does not have Punch-through (Punch-through), otherwise, the device has large leakage and low breakdown voltage.
The P-type ring 6a is formed simultaneously by the same process as the P-type well 6; alternatively, the P-type ring 6a is formed by one photolithography definition and P-type ion implantation.
Step three, as shown in fig. 3C, forming a first oxide film 7 on the surface of the semiconductor substrate 1, and then etching the first oxide film 7 by using a process of defining lithography and etching the oxide film to form a protective epoxy film 7; the protective epoxy film 7 opens the current flow region and covers the transition region and the termination region within the subsequently formed cut-off region 110 b.
In the method of the embodiment of the invention, the protective epoxy film 7 is formed by adopting a thermal oxidation process with the temperature higher than 800 ℃, so that dangling bonds and unstable interface states can be reduced at the Si-SiO2 interface, the voltage bearing capacity of a terminal region is further improved, and the consistency of the breakdown voltage of a device is improved. The thickness of protective epoxy film 7 is set according to the breakdown voltage (BVds) of the device, and generally, the larger the BVds is, the thicker protective epoxy film 7 is, and generally, the oxide film thickness of 600V or more devices is more than 8000A, for example, it is set
Figure BDA0001871924730000181
Step four, as shown in fig. 3C, taking the protective epoxy film 7 as a self-aligned mask, performing JFET ion implantation to form a JFET region 10a1 in the current flowing region in a self-aligned manner and form an electric field blocking layer 10b1 on the outermost side of the termination region; the doping concentration of the JFET region 10a1 is smaller than that of the P-type trap 6, the surface of the P-type trap 6 with the superposed impurities of JFET ion implantation still keeps P-type doping, and the JFET region 101a is located between the P-type traps 6 in a self-aligning mode. The JFET region designated 10a1 and the doped region before annealing diffusion after ion implantation of the electric field blocking layer designated 10b 1.
Because the transition region and the terminal region are protected by the protective epoxy film 7, the JFET ion implantation can be performed without photolithography, so that the cost of the photolithography process is saved, because if the terminal region is also subjected to the JFET ion implantation, the BVds of the device is obviously reduced, and if the JFET ion implantation is performed in the transition region, the current impact resistance of the device is reduced.
The process conditions of the JFET ion implantation are as follows: the implanted impurity is phosphorus, and the implantation dosage is 1E12cm-2～4E12cm-2The implantation energy is 30Kev to 100 Kev. Or, the JFET ion implantation is divided into two times with different implantation energies, and the implantation energy distribution corresponding to the two times of implantation is as follows: 30 Kev-60 Kev and 500 Kev-1.5 MeKev, the implantation impurities are all phosphorus, and the implantation dosage is all 1E12cm-2～4E12cm-2. The high energy implant further reduces the specific on-resistance of the device and increases the Bvds of the device by improving the charge balance around the P-well 6 (experimental results are that for a 600V device, it can be increased by 10V to 20V).
Step five, as shown in fig. 3D, a gate oxide film 8 is formed by a thermal oxidation process, and then a polysilicon gate 9 is formed; by utilizing the characteristic that the JFET ion implantation is placed before the thermal oxidation process of the gate oxide film 8, annealing promotion of impurities of the JFET region 10a and the electric field barrier layer 10b is realized by adopting the thermal oxidation process of the gate oxide film 8, so that the diffusion area of the JFET region 10a and the electric field barrier layer 10b is increased; the diffusion area of the JFET region 10a is increased, so that the drift region resistance can be reduced; the diffusion area of the JFET area 10a is increased, and the area of a channel formed by the P-type well 6 is reduced, so that the channel resistance can be reduced; the increase of the diffusion area of the JFET area 10a also increases the PN junction slow-changing effect formed by the JFET area 10a and the P-type well 6, and improves the reliability of the device.
In the method of the embodiment of the invention, for the super junction MOSFET of 500V-700V, the thickness of the gate oxide film 8 is
Figure BDA0001871924730000191
The thickness of the polysilicon gate 9 is
Figure BDA0001871924730000192
In the method of the embodiment of the invention, in order to obtain the high-quality gate oxide film 8, the high-temperature oxidation temperature is set around 1050 ℃, the time is adjusted according to the thickness of the gate oxide film 8, for a common high-voltage super-junction MOSFET, the thickness of the gate oxide film 8 is generally about 1000 angstroms, the required high-temperature deposition time is about 60 minutes, and the time of temperature rise and temperature reduction in a high-temperature stage is well controlled, for example, the temperature rise speed is 5 ℃/minute from 800 ℃ to 1050 ℃, the temperature reduction speed is set to be less than 2 ℃/minute from 1050 ℃, and the quality and the consistency of the gate oxide film 8 are further ensured.
Sixthly, as shown in fig. 3D, the polysilicon gate 9 and the gate oxide film 8 are etched in sequence by adopting a photoetching definition and etching process to form the split-gate planar gate structure formed by overlapping the etched gate oxide film 8 and the etched polysilicon gate 9. A polysilicon field plate 9a is formed on the surface of the protective epoxy film 7 at the same time as the polysilicon gate 9 is formed.
The split-gate planar gate structure is positioned in the current flowing region, and a super junction unit is formed by one N-type column 2 and one adjacent P-type column 51; in the current flowing region, two separated split-gate planar gate structures are arranged above the N-type column 2 of the same super junction unit; the polysilicon gate 9 corresponding to each split gate planar gate structure covers the corresponding P-type well 6 and extends to the surface of the JFET region 10a adjacent to the P-type well 6, and the surface of the P-type well 6 covered by the polysilicon gate 9 is used for forming a channel; the split-gate planar gate structure reduces the lateral overlapping area between the JFET region 10a and the polysilicon gate 9, thereby reducing the gate-drain capacitance of the device.
Seventhly, as shown in fig. 3E, photolithography and N + ion implantation are adopted to form a source region 110a, which is formed by an N + region, on the surface of the P-type well 6 in the current flowing region, and a cut-off region 110b is formed on the outermost side of the terminal region, and the source region 110a and the side surface of the polysilicon gate 9, which is located on the P-type well 6, are self-aligned.
The doping concentration of the electric field barrier layer 10b is lower than that of the cut-off region 110b by more than 2 orders of magnitude, and the electric field barrier layer 10b fully surrounds the cut-off region 110b in the longitudinal direction and the transverse direction, so that a depletion layer is prevented from contacting the cut-off region 110b and an electric field is stopped in the electric field barrier layer 10b when the device is reversely biased, and the soft breakdown characteristic of the device is improved.
The process conditions of the ion implantation of the source region 110a are as follows: the implantation impurity is phosphorus or arsenic, and the implantation dosage is 3E15cm-2～8E15cm-2The injection energy is 30 Kev-100 Kev; after the ion implantation of the source region 110a is completed, rapid thermal annealing activation is performed, and the process conditions of the rapid thermal annealing corresponding to the source region 110a are as follows: the annealing temperature is 1000-1100 ℃, and the annealing time is 15-30 s.
In other example methods, the source region can also be activated using thermal annealing, for example, annealing at 950 ℃ for 30 minutes; the activation temperature can also be set between 800 ℃ and 950 ℃ and the time between 30 minutes and-60 minutes.
The method also comprises the following steps:
step eight, as shown in fig. 3F, depositing an interlayer film 11, and forming contact holes penetrating through the interlayer film 11 by using a photolithography and etching process, where the contact holes are distributed and marked with marks 121a, 121b, and 121c in fig. 3F.
The interlayer film 11 is a combination of an undoped oxide film and a BPSG film. The thickness of the interlayer film 11 is
Figure BDA0001871924730000201
Figure BDA0001871924730000202
In the etching of the contact hole 121a in the current flowing region, N + at the bottom thereof, i.e., the source region 18, needs to be etched, i.e., over-etching of silicon is needed, the over-etching amount of silicon can be 2000 angstroms to 4000 angstroms, and the over-etching amount of silicon specifically needs to be determined according to the implantation conditions of ion implantation, i.e., the implantation dose and the implantation energy, corresponding to the source region 18. Since the contact hole 121a penetrates the N +, i.e. the range of the source region 18, the contact problem between the P-type well 6 and the metal due to the overall implantation of the source region 18 in the region outside the polysilicon gate 9 is avoided, and the normal electrical characteristics are ensured.
As shown in fig. 3G, the method further includes a step of performing P + ion implantation at the bottom of the contact holes 121a, 121b, and 121c to form a well contact region 13 after the opening of the contact hole is formed and before the metal filling. Preferably, the P-type impurity of the well contact region 13 is B, BF2, or a combination of B and BF2, and the implantation energy is generally 30Kev to 80Kev, and the implantation dose is 1E15cm-2～3E15cm-2The current surge resistance of the device can be improved by optimizing the injection conditions. In order to better improve the softness of the reverse recovery process of the body diode, the energy and dose of the P-type implantation of the well contact region 13 can also be reduced, for example, the energy can be BF2, 5Kev 40KEV, 5E14cm-2～2E15cm-2The dose is selected so that the energy is selected primarily to take into account the capabilities of the ion implantation equipment in order to ensure the minimum dose to form the ohmic contacts.
As shown in fig. 3G, after the contact hole etching and the P + ion implantation at the bottom are completed, a blocking layer formed by stacking Ti and TiN is deposited, then metal tungsten (W) is deposited to fill the opening of the contact hole, the thickness of W for the opening with the width of 0.6 micrometer can be set to 4000 angstroms, and then plasma dry etching is performed to completely remove the metal on the surface.
Ninthly, as shown in fig. 3G, performing front metal deposition to form a front metal layer, forming the gate and the source 14a and electrodes 14b and 14c composed of the front metal layer by using a photolithography and metal etching process, and connecting each source region 18 and the corresponding P-type well 6 to the source 14a through the same contact hole 22 at the top; the polysilicon gate 9 is connected to the gate through the corresponding contact hole 22 at the top. The polysilicon field plate 9a is connected to an electrode 14b through a contact hole, the electrode 14b can be a gate. The cut-off region 110b is connected to the electrode 14c through the contact hole 121 c.
The front metal layer can be made of ALSi or AlSiCu and can be provided with a barrier layer, and the barrier layer can be Ti/TiN, namely a superposed layer of Ti and TiN, or TiN. The total thickness of the front metal layer is generally 4 μm to 6 μm.
And then thinning the back surface of the semiconductor substrate 1, and forming a drain region by using the N + region formed in the thinned semiconductor substrate 1, wherein the drain region can be directly formed by the heavily doped semiconductor substrate 1 or formed by injecting the heavily doped semiconductor substrate 1 and N-type heavily doped ions. And depositing a back metal layer 15 on the back of the semiconductor substrate 1, namely the drain region 11 to form a drain electrode.
In the manufacturing method of the embodiment of the invention, the process flow is the same as the cost of the prior art by using seven times of photoetching, including groove photoetching, P-type well photoetching, guard ring oxide film photoetching, polysilicon photoetching, N + source region photoetching, contact hole photoetching and front metal photoetching.
In order to ensure the production stability in production, 0 layer of photoetching and/or mark layer photoetching can be added before the groove photoetching, so that an alignment mark and an alignment precision test mark are formed by photoetching and etching; the process for layer 0 may be deposition
Figure BDA0001871924730000211
Then photolithography, etching the oxide film, and then etching silicon
Figure BDA0001871924730000212
A step is formed.
In order to better protect the front side of the device and improve the reliability of the device, a passivation layer can be deposited after the front side metal layer pattern is formed, and then the passivation layer of the metal area to be opened is etched through the passivation layer photoetching and etching. While in other areas the passivation layer is left to protect the device. The passivation layer can be SIN, SION, SIO2, typically 0.8 microns to 2 microns thick.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A super junction device is characterized in that the middle area of the super junction device is a current flowing area, a terminal area surrounds the periphery of the current flowing area, and a transition area is located between the current flowing area and the terminal area; the method is characterized in that: a protective epoxy film formed by photolithographic etching of the first oxide film opens the current flow region and covers the transition region and the termination region within a cut-off region composed of an N + region;
the current flowing region includes the following structure:
the N-type epitaxial layer is subjected to dry etching to form a plurality of grooves; filling a P-type epitaxial layer in the groove to form a P-type column, forming an N-type column by the N-type epitaxial layer between the P-type columns, and forming a super junction structure by a plurality of alternately arranged N-type columns and P-type columns;
a P-type well is formed at the top of each P-type column and extends to the surface of the N-type column on two sides of the corresponding P-type column;
a JFET region formed by JFET ion implantation and the JFET ion implantation region is defined by the guard ring oxide film in a self-aligned mode; the doping concentration of the JFET area is smaller than that of the P-type trap, the surface of the P-type trap with the superposed impurities of JFET ion implantation still keeps P-type doping, and the JFET area is positioned between the P-type traps in a self-aligned mode;
the split gate planar gate structure is formed by superposing a gate oxide film and a polysilicon gate; a super junction unit is formed by one N-type column and one adjacent P-type column, and two separated split gate planar gate structures are arranged above the N-type column of the same super junction unit;
each polysilicon gate covers the corresponding P-type well and extends to the surface of the JFET area adjacent to the P-type well, and the surface of the P-type well covered by the polysilicon gate is used for forming a channel; the split-gate planar gate structure reduces the transverse overlapping area between the JFET area and the polysilicon gate, thereby reducing the gate-drain capacitance of the device;
a source region consisting of an N + region is formed on the surface of the P-type well, and the source region and the side face of the polysilicon gate, which is positioned on the P-type well, are self-aligned;
the JFET ion implantation is carried out before the formation process of the gate oxide film, the gate oxide film is a thermal oxide film, the JFET region is provided with a structure which is subjected to annealing promotion through the thermal oxide process of the gate oxide film, and the thermal oxide process of the gate oxide film increases the diffusion region of the JFET region and can reduce the resistance of a drift region; the diffusion area of the JFET area is increased, and meanwhile, the area of the P-type trap forming the channel is reduced, so that the channel resistance can be reduced; the diffusion area of the JFET area is increased, so that the PN junction slow-changing effect formed by the JFET area and the P-type trap is increased, and the reliability of the device is improved; the threshold voltage required by the channel is determined by the superposed P-type net doping concentration of the JFET area and the P-type well, so that the doping concentration of the P-type well can be improved, and the current breakdown resistance of the device can be improved;
the super junction structure is also formed in the transition region and the terminal region;
a P-type ring is formed in the transition region;
an electric field barrier layer which is formed in the terminal area and has the same process as the JFET area and is formed at the same time is formed in the terminal area, the doping concentration of the electric field barrier layer is lower than that of the cut-off area by more than 2 orders of magnitude, the electric field barrier layer is fully diffused under the action of the thermal process of the gate oxide film and fully surrounds the cut-off area in the longitudinal direction and the transverse direction, so that the depletion layer is prevented from contacting the cut-off area and stopping an electric field in the electric field barrier layer when the device is reversely biased, and the soft breakdown characteristic of the device is improved.
2. The superjunction device of claim 1, wherein: the thickness of the first oxide film is
Figure FDA0001871924720000021
Figure FDA0001871924720000022
3. The superjunction device of claim 2, wherein: the process temperature of the first oxide film is above 800 ℃.
4. The superjunction device of claim 1, wherein: the thickness of the gate oxide film is
Figure FDA0001871924720000023
Figure FDA0001871924720000024
The thickness of the polysilicon gate is
Figure FDA0001871924720000025
5. The superjunction device of claim 4, wherein: the conditions of the thermal oxidation process of the gate oxide film are as follows: the process temperature is 1050 ℃, the time of the oxide film deposition process is 60 minutes, the temperature rising rate from 800 ℃ to 1050 ℃ is 5 ℃/minute, and the temperature reduction rate from 1050 ℃ to 800 ℃ is 2 ℃/minute.
6. The superjunction device of claim 1, wherein: the process conditions of the JFET ion implantation are as follows: the implanted impurity is phosphorus, and the implantation dosage is 1E12cm-2～4E12cm-2The injection energy is 30 Kev-100 Kev;
or, the JFET ion implantation is divided into two times with different implantation energies, and the implantation energy distribution corresponding to the two times of implantation is as follows: 30 Kev-60 Kev and 500 Kev-1.5 MeKev, the implantation impurities are all phosphorus, and the implantation dosage is all 1E12cm-2～4E12cm-2。
7. The super set of claim 1A junction device, characterized by: the process conditions of the ion implantation of the P-type well are as follows: the implantation impurity is boron, and the implantation dosage is 3E13cm-2～1E14cm-2The injection energy is 30 Kev-100 Kev;
the forming process of the P-type ring and the forming process of the P-type well are the same and are formed simultaneously; or, the P-type ring is formed by one time of photoetching definition and P-type ion implantation.
8. The superjunction device of claim 1, wherein: the process conditions of the ion implantation of the source region are as follows: the implantation impurity is phosphorus or arsenic, and the implantation dosage is 3E15cm-2～8E15cm-2The injection energy is 30 Kev-100 Kev; and performing rapid thermal annealing activation after the ion implantation of the source region is completed, wherein the rapid thermal annealing process conditions corresponding to the source region are as follows: the annealing temperature is 1000-1100 ℃, and the annealing time is 15-30 s;
the forming process of the cut-off region and the source region is the same and formed simultaneously.
9. A manufacturing method of a super junction device is provided, wherein the middle area of the super junction device is a current flowing area, a terminal area surrounds the periphery of the current flowing area, and a transition area is positioned between the current flowing area and the terminal area; the method is characterized by comprising the following steps:
forming an N-type epitaxial layer on an N-type semiconductor substrate, forming a plurality of grooves in the N-type epitaxial layer by adopting a photoetching definition and dry etching process, filling P-type epitaxial layers in the grooves to form P-type columns, forming N-type columns by the N-type epitaxial layers among the P-type columns, and forming a super junction structure by the N-type columns and the P-type columns which are alternately arranged; the super junction structure is formed in the current flow region, the transition region and the termination region;
step two, forming a P-type trap on the top of each P-type column in the current flowing region, wherein each P-type trap extends to the surface of the N-type column on two sides of the corresponding P-type column; forming a P-type ring in the transition region;
forming a first oxide film on the surface of the semiconductor substrate, and etching the first oxide film by adopting a photoetching definition and oxide film etching process to form a protective ring oxide film; the protective epoxy film opens the current flow region and covers the transition region and the termination region within a subsequently formed cut-off region;
taking the protective epoxy film as a self-aligned mask, performing JFET ion implantation to form a JFET region in the current flowing region in a self-aligned mode, and forming an electric field barrier layer on the outermost side of the terminal region; the doping concentration of the JFET area is smaller than that of the P-type trap, the surface of the P-type trap with the superposed impurities of JFET ion implantation still keeps P-type doping, and the JFET area is positioned between the P-type traps in a self-aligned mode;
forming a gate oxide film by adopting a thermal oxidation process, and then forming a polysilicon gate; annealing and propelling the impurities of the JFET region and the electric field barrier layer by the thermal oxidation process of the gate oxide film by utilizing the characteristic that the JFET ion implantation is placed before the thermal oxidation process of the gate oxide film, so that the diffusion regions of the JFET region and the electric field barrier layer are increased; the drift region resistance can be reduced by increasing the diffusion region of the JFET region; the diffusion area of the JFET area is increased, and meanwhile, the area of a channel formed by the P-type trap is reduced, so that the channel resistance can be reduced; the diffusion area of the JFET area is increased, so that the PN junction slow-changing effect formed by the JFET area and the P-type trap is increased, and the reliability of the device is improved;
step six, etching the polysilicon gate and the gate oxide film in sequence by adopting a photoetching definition and etching process to form the split gate planar gate structure formed by overlapping the etched gate oxide film and the polysilicon gate;
the split-gate planar gate structure is positioned in the current flowing area, and a super junction unit is formed by one N-type column and one adjacent P-type column; in the current flowing region, two separated split-gate planar gate structures are arranged above the N-type column of the same super junction unit; the polysilicon gate corresponding to each split gate planar gate structure covers the corresponding P-type well and extends to the surface of the JFET area adjacent to the P-type well, and the surface of the P-type well covered by the polysilicon gate is used for forming a channel; the split-gate planar gate structure reduces the transverse overlapping area between the JFET area and the polysilicon gate, thereby reducing the gate-drain capacitance of the device;
seventhly, photoetching and N + ion implantation are adopted, a source region consisting of an N + region is formed on the surface of the P-type well in the current flowing region, a cut-off region is formed on the outermost side of the terminal region, and the source region and the side face, located on the P-type well, of the polysilicon gate are self-aligned;
the doping concentration of the electric field barrier layer is lower than that of the cut-off region by more than 2 orders of magnitude, the cut-off region is fully surrounded by the electric field barrier layer in the longitudinal direction and the transverse direction, so that a depletion layer is prevented from contacting the cut-off region when the device is reversely biased, an electric field is stopped in the electric field barrier layer, and the soft breakdown characteristic of the device is improved.
10. The method of manufacturing a superjunction device of claim 9, wherein: in the third step, the thickness of the first oxide film is
Figure FDA0001871924720000041
The process temperature of the first oxide film is above 800 ℃.
11. The method of manufacturing a superjunction device of claim 9, wherein: the thickness of the gate oxide film formed in the fifth step is
Figure FDA0001871924720000043
The thickness of the polysilicon gate is
Figure FDA0001871924720000042
12. The method of manufacturing a superjunction device of claim 11, wherein: the conditions of the thermal oxidation process of the gate oxide film are as follows: the process temperature is 1050 ℃, the time of the oxide film deposition process is 60 minutes, the temperature rising rate from 800 ℃ to 1050 ℃ is 5 ℃/minute, and the temperature reduction rate from 1050 ℃ to 800 ℃ is 2 ℃/minute.
13. The method of manufacturing a superjunction device of claim 9, wherein: in the fourth step, the process conditions of the JFET ion implantation are as follows: the implanted impurity is phosphorus, and the implantation dosage is 1E12cm-2～4E12cm-2The injection energy is 30 Kev-100 Kev;
or, the JFET ion implantation is divided into two times with different implantation energies, and the implantation energy distribution corresponding to the two times of implantation is as follows: 30 Kev-60 Kev and 500 Kev-1.5 MeKev, the implantation impurities are all phosphorus, and the implantation dosage is all 1E12cm-2～4E12cm-2。
14. The method of manufacturing a superjunction device of claim 9, wherein: in the second step, the process conditions of the ion implantation of the P-type well are as follows: the implantation impurity is boron, and the implantation dosage is 3E13cm-2～1E14cm-2The injection energy is 30 Kev-100 Kev;
the P-type ring is formed simultaneously by the same process as the P-type well; or, the P-type ring is formed by one time of photoetching definition and P-type ion implantation.
15. The method of manufacturing a superjunction device of claim 9, wherein: in the seventh step, the process conditions of the ion implantation of the source region are as follows: the implantation impurity is phosphorus or arsenic, and the implantation dosage is 3E15cm-2～8E15cm-2The injection energy is 30 Kev-100 Kev; and performing rapid thermal annealing activation after the ion implantation of the source region is completed, wherein the rapid thermal annealing process conditions corresponding to the source region are as follows: the annealing temperature is 1000-1100 ℃, and the annealing time is 15-30 s.
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