CN111200025A

CN111200025A - Superjunction device and method of making the same

Info

Publication number: CN111200025A
Application number: CN201811381199.1A
Authority: CN
Inventors: 肖胜安
Original assignee: Shenzhen Sanrise Tech Co ltd
Current assignee: Shenzhen Sanrise Tech Co ltd
Priority date: 2018-11-20
Filing date: 2018-11-20
Publication date: 2020-05-26

Abstract

The invention discloses a super junction device.A current flowing area is opened by a protection ring oxide film, the current flowing area comprises a super junction structure formed in an N-type epitaxial layer, and a P-type trap is formed at the top of each P-type column; the ion implantation of the JFET area is defined by self-alignment of a guard ring oxide film; the super junction unit comprises two separated split-gate planar gate structures above an N-type column of the same super junction unit; the source region is formed on the surface of the P-type well; and the JFET ion implantation is carried out before the formation process of the gate oxide film of the split gate plane gate, so that the JFET region has a structure which is subjected to annealing promotion through the thermal oxidation process of the gate oxide film. The invention also discloses a manufacturing method of the super junction device. The invention can realize the split-gate planar gate structure to reduce the gate-drain capacitance of the device, and can realize better diffusion to the JFET area of the super junction device with the split-gate planar gate structure, thereby reducing the on-resistance of the device and improving the reliability of the device without increasing the process cost.

Description

Super junction device and manufacturing method thereof

Technical Field

The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a super junction (junction) device.

Background

The existing super junction device comprises a current flowing area, which is also commonly called a charge flowing area, wherein P-type columns and N-type columns, namely P-N columns, which are alternately arranged, are arranged in the current flowing area, the P-N columns form a super junction structure, the P-type columns are generally composed of P-type epitaxial layers filled in trenches, namely super junction trenches, and the N-type columns are composed of N-type epitaxial layers between the P-type columns. Taking the structure of a strip-shaped P-N column as an example, a gate structure is arranged above each N column, and the gate structure comprises a planar gate structure and a trench gate structure. For a planar gate structure, the gate structure can partially cover the peripheral P-type columns or not, a P-type well is arranged above each P-type column, and a source region consisting of an N + region is arranged in each P-type well; a contact hole is formed at the top of the source region, and the source region is connected to a source electrode consisting of a front metal layer, namely a metal source electrode through the contact hole at the top; meanwhile, the bottom of the contact hole of the source region is also connected with the P-type well through a high-concentration P + contact region; an N-type region is arranged between the adjacent P-type wells, when the device is conducted, the surfaces of the P-type wells covered by the grid structures are inverted and form channels, electrons in the source region flow to the N-type region outside the P-type wells through the inversion layers, namely the channels, on the surfaces of the P-type wells, then flow to the high-concentration drain region on the back side through the N-type epitaxy, namely the N-type columns, and the N-type epitaxy at the bottoms of the N-type columns and flow to the drain electrode formed by the metal layer on the back side, and therefore conducting current is formed.

In the prior art, in order to reduce the on-resistance, a certain amount of N-type ions, such as phosphorus ions, are generally implanted into the N-type region between two adjacent P-type wells to form a region with a higher concentration than the N-type epitaxial layer, thereby reducing the on-resistance (Rdson) of the device.

In order to reduce the switching loss of the device, it is effective to reduce the reverse conducting capacitance (Crss), which is equal to the gate-drain capacitance (Cgd). In order to reduce Cgd, one of the most straightforward ways to reduce the footprint of the gate and JFET regions, a device is designed with a planar gate designed as a split-gate structure, i.e., a split-gate planar gate is used.

In the prior art, after a split-gate planar gate is adopted, JFET ion implantation is carried out once in order to reduce the on-resistance of a device, in the prior art, the JFET ion implantation is placed after polysilicon gate etching is finished, N + ion implantation of a source region is carried out after the JFET ion implantation is finished, then an activation process is carried out, activation of the source region and the JFET region is simultaneously realized through the activation process, the activation temperature is generally 900-950 ℃, in the prior art, the JFET region and the N + source region are subjected to basically the same thermal process, the diffusion effect of the process on the JFET region is limited, the Rdson of the device can be influenced, and meanwhile, the electric field intensity of the JFET region is improved due to the high concentration of the JFET region, and the reliability of the device can be influenced.

Disclosure of Invention

The invention aims to solve the technical problem of providing a super junction device, which can realize a split-gate planar gate structure to reduce the gate-drain capacitance of the device and can realize better diffusion of a JFET (junction field effect transistor) area of the super junction device with the split-gate planar gate structure, thereby reducing the on-resistance of the device and improving the reliability of the device without increasing the process cost. Therefore, the invention also provides a manufacturing method of the super junction device.

In order to solve the technical problem, the middle area of the super junction device provided by the invention is a current flowing area, a terminal area surrounds the periphery of the current flowing area, and a transition area is positioned between the current flowing area and the terminal area; a protective epoxy film (G-field oxide) formed by photolithographic etching of the first oxide film opens the current flow region.

The current flowing region includes the following structure:

the N-type epitaxial layer is subjected to dry etching to form a plurality of grooves; and filling a P-type epitaxial layer in the groove to form a P-type column, forming an N-type column by the N-type epitaxial layer among the P-type columns, and forming a super junction structure by a plurality of alternately arranged N-type columns and P-type columns.

A P-type well is formed at the top of each P-type column and each P-type well extends to the surface of the N-type column on both sides of the corresponding P-type column.

A JFET region formed by JFET ion implantation and the JFET ion implantation region is defined by the guard ring oxide film in a self-aligned mode; the doping concentration of the JFET area is smaller than that of the P-type trap, the surface of the P-type trap with the superposed impurities of JFET ion implantation still keeps P-type doping, and the JFET area is located between the P-type traps in a self-aligning mode.

The split gate planar gate structure is formed by superposing a gate oxide film and a polysilicon gate; a super junction unit is formed by one N-type column and one adjacent P-type column, and two separated split gate plane gate structures are arranged above the N-type column of the same super junction unit.

Each polysilicon gate covers the corresponding P-type well and extends to the surface of the JFET area adjacent to the P-type well, and the surface of the P-type well covered by the polysilicon gate is used for forming a channel; the split-gate planar gate structure reduces the transverse overlapping area between the JFET area and the polysilicon gate, thereby reducing the gate-drain capacitance of the device.

And a source region consisting of an N + region is formed on the surface of the P-type well, and the source region and the side face of the polysilicon gate, which is positioned on the P-type well, are self-aligned.

The JFET ion implantation is carried out before the formation process of the gate oxide film, the gate oxide film is a thermal oxide film, the JFET region is provided with a structure which is subjected to annealing promotion through the thermal oxide process of the gate oxide film, and the thermal oxide process of the gate oxide film increases the diffusion region of the JFET region and can reduce the resistance of a drift region; the diffusion area of the JFET area is increased, and meanwhile, the area of the P-type trap forming the channel is reduced, so that the channel resistance can be reduced; the increase of the diffusion area of the JFET area also increases the PN junction slow-changing effect formed by the JFET area and the P-type trap, and improves the reliability of the device.

In a further improvement, the first oxide film has a thickness of

In a further improvement, the process temperature of the first oxide film is above 800 ℃.

In a further improvement, the thickness of the gate oxide film is

The thickness of the polysilicon gate is

The further improvement is that the conditions of the thermal oxidation process of the gate oxide film are as follows: the process temperature is 1050 ℃, the time of the oxide film deposition process is 60 minutes, the temperature rising rate from 800 ℃ to 1050 ℃ is 5 ℃/minute, and the temperature reduction rate from 1050 ℃ to 800 ℃ is 2 ℃/minute.

In a further improvement, the process conditions of the JFET ion implantation of the JFET region are as follows: the implanted impurity is phosphorus, and the implantation dosage is 1E12cm^-2～4E12cm^-2The implantation energy is 30Kev to 100 Kev.

Or the JFET ion implantation of the JFET area is divided into two times with different implantation energies, and the implantation energy distribution corresponding to the two times of implantation is as follows: 30 Kev-60 Kev and 500 Kev-1.5 MeKev, the implantation impurities are all phosphorus, and the implantation dosage is all 1E12cm^-2～4E12cm^-2。

The further improvement is that the process conditions of the ion implantation of the P-type well are as follows: the implantation impurity is boron, and the implantation dosage is 3E13cm^-2～1E14cm^-2The implantation energy is 30Kev to 100 Kev.

The further improvement is that the process conditions of the ion implantation of the source region are as follows: the implantation impurity is phosphorus or arsenic, and the implantation dosage is 3E15cm^-2～8E15cm^-2The injection energy is 30 Kev-100 Kev; and performing rapid thermal annealing activation after the ion implantation of the source region is completed, wherein the rapid thermal annealing process conditions corresponding to the source region are as follows: the annealing temperature is 1000-1100 ℃, and the annealing time is 15-30 s.

In order to solve the technical problem, in the manufacturing method of the super junction device provided by the invention, the middle area of the super junction device is a current flowing area, the terminal area surrounds the periphery of the current flowing area, and the transition area is positioned between the current flowing area and the terminal area; the method comprises the following steps:

step one, forming an N-type epitaxial layer on an N-type semiconductor substrate, forming a plurality of grooves in the N-type epitaxial layer by adopting a photoetching definition and dry etching process, filling P-type epitaxial layers in the grooves to form P-type columns, forming N-type columns by the N-type epitaxial layer among the P-type columns, and forming a super junction structure by the N-type columns and the P-type columns which are alternately arranged.

And secondly, forming a P-type trap at the top of each P-type column in the current flowing region, wherein each P-type trap extends to the surfaces of the N-type columns on two sides of the corresponding P-type column.

And thirdly, forming a first oxide film on the surface of the semiconductor substrate, and then removing the first oxide film in the current flowing area by adopting a photoetching definition and oxide film etching process to form a protective ring oxide film, wherein the protective ring oxide film opens the current flowing area.

And fourthly, taking the protective epoxidation film as a self-alignment mask, carrying out JFET ion implantation to form a JFET area in the current flowing area in a self-alignment manner, wherein the doping concentration of the JFET area is smaller than that of the P-type trap, the surface of the P-type trap on which impurities injected by the JFET ions are superposed is still kept in a P-type doping manner, and the JFET area is positioned between the P-type traps in a self-alignment manner.

Forming a gate oxide film by adopting a thermal oxidation process, and then forming a polysilicon gate; annealing and propelling the impurities in the JFET region by the thermal oxidation process of the gate oxide film by utilizing the characteristic that the JFET ion implantation is placed before the thermal oxidation process of the gate oxide film, so that the diffusion area of the JFET region is increased, and the resistance of a drift region can be reduced; the diffusion area of the JFET area is increased, and meanwhile, the area of a channel formed by the P-type trap is reduced, so that the channel resistance can be reduced; the increase of the diffusion area of the JFET area also increases the PN junction slow-changing effect formed by the JFET area and the P-type trap, and improves the reliability of the device.

And step six, etching the polysilicon gate and the gate oxide film in sequence by adopting a photoetching definition and etching process to form the split gate planar gate structure formed by overlapping the etched gate oxide film and the polysilicon gate.

The split-gate planar gate structure is positioned in the current flowing area, and a super junction unit is formed by one N-type column and one adjacent P-type column; in the current flowing region, two separated split-gate planar gate structures are arranged above the N-type column of the same super junction unit; the polysilicon gate corresponding to each split gate planar gate structure covers the corresponding P-type well and extends to the surface of the JFET area adjacent to the P-type well, and the surface of the P-type well covered by the polysilicon gate is used for forming a channel; the split-gate planar gate structure reduces the transverse overlapping area between the JFET area and the polysilicon gate, thereby reducing the gate-drain capacitance of the device.

Seventhly, photoetching and N + ion implantation are adopted, a source region is formed by an N + region on the surface of the P-type trap in the current flowing region, and the source region and the side face, located on the P-type trap, of the polysilicon gate are self-aligned.

In a further improvement, in the third step, the thickness of the first oxide film is

The process temperature of the first oxide film is above 800 ℃.

In a further improvement, the thickness of the gate oxide film formed in the fifth step is

The thickness of the polysilicon gate is

Further, the method comprisesThe improvement is that in the fourth step, the process conditions of the JFET ion implantation in the JFET area are as follows: the implanted impurity is phosphorus, and the implantation dosage is 1E12cm^-2～4E12cm^-2The implantation energy is 30Kev to 100 Kev.

In a further improvement, in the second step, the process conditions of the ion implantation of the P-type well are as follows: the implantation impurity is boron, and the implantation dosage is 3E13cm^-2～1E14cm^-2The implantation energy is 30Kev to 100 Kev.

In a further improvement, in the seventh step, the process conditions of the ion implantation of the source region are as follows: the implantation impurity is phosphorus or arsenic, and the implantation dosage is 3E15cm^-2～8E15cm^-2The injection energy is 30 Kev-100 Kev; and performing rapid thermal annealing activation after the ion implantation of the source region is completed, wherein the rapid thermal annealing process conditions corresponding to the source region are as follows: the annealing temperature is 1000-1100 ℃, and the annealing time is 15-30 s.

The super junction device combines the split-gate planar gate structure and the process structure of the JFET area, and the split-gate planar gate structure can realize smaller coverage on the JFET area, so that the gate-drain capacitance of the device can be reduced, and the switching loss of the device can be reduced.

The process structure of the JFET area has the structure that annealing diffusion is carried out by adopting the thermal process of the gate oxide film, the process of JFET ion injection only needs to be placed before the formation process of the gate oxide film in the process, and the thermal process of the gate oxide film has higher temperature and longer time and also comprises a longer temperature rise and fall process, so that the thermal process of the gate oxide film can well diffuse the JFET area, the diffusion effect of the JFET area is improved, and the improvement of the diffusion effect of the JFET area can obtain the following beneficial technical effects:

1. the JFET area is diffused more, so that the range of the JFET area is enlarged, or the range of the surface high-concentration area is enlarged, the on-resistance of the device can be reduced, the JFET area belongs to the drift area of the super junction device on the whole, and the reduced on-resistance of the JFET area corresponds to the resistance of the drift area.

2. Because more diffusion of the JFET area is achieved, the channel length of the super junction device is shortened, and therefore the on-resistance of the device can be reduced; the decrease in on-resistance due to the decrease in channel length mainly corresponds to the decrease in channel resistance.

3. As the JFET area is diffused more, the P-type trap near the interface of the gate oxide film and the silicon and the PN junction formed by the JFET area become more gradual, the electric field intensity under the reverse bias condition of the device at the position can be reduced, the electric leakage of the device is reduced, and the reliability of the device is improved.

In addition, the injection area of JFET ion injection directly adopts the self-alignment definition of the guard ring oxide film, and the self-alignment definition has lower process cost; meanwhile, the guard ring oxide film is also commonly called a G-field oxide film, the thickness of the guard ring oxide film is thicker, and is usually 8000-15000 angstroms, and the guard ring oxide film is used as a mask for JFET ion implantation, so that higher ion implantation energy can be borne, and the design of the device is more convenient. In the prior art, JFET ion implantation is performed after a grid structure comprises a superposed layer structure of a grid oxide film and a polysilicon grid is formed, and the thickness of the superposed layer of the grid oxide film and the polysilicon grid is generally 5000-6000 angstroms and is obviously lower than that of a protection ring oxide film, so that the adjustment of the implantation energy of the JFET ion implantation is easier, and the design of a device is more convenient.

In addition, the convenience improvement of the process conditions of the ion implantation of the JFET region and the improvement of the diffusion effect of the JFET region are realized only by elaborately designing the forming process of the JFET region without adding other additional process cost, so the method also has the characteristic of low process cost.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

fig. 1 is a schematic structural diagram of a prior art first super junction device;

fig. 2 is a schematic structural diagram of a second prior art superjunction device;

fig. 3A is a structural simulation diagram of a second superjunction device in the prior art;

fig. 3B is a structural simulation diagram of a superjunction device according to an embodiment of the present invention;

fig. 4 is an impurity concentration profile of a JFET region and a P-well of a superjunction device of an embodiment of the present invention and a second prior art superjunction device.

Detailed Description

Before the superjunction device according to the embodiment of the present invention is described, the structures of two superjunction devices in the prior art are described.

As shown in fig. 1, a schematic structure of a prior art super junction device; the middle region of the prior first super junction device is a current flowing region, a terminal region surrounds the periphery of the current flowing region, a transition region is located between the current flowing region and the terminal region, and fig. 1 shows the transition region and the terminal region; a protective epoxy film (not shown) formed by photolithographic etching of the first oxide film opens the current flow region.

The current flowing region includes the following structure:

the N-type epitaxial layer 12 is subjected to dry etching to form a plurality of grooves; the trenches are filled with a P-type epitaxial layer and form P-type columns 13, N-type columns 12 are formed by the N-type epitaxial layer 12 between the P-type columns 13, and a super junction structure is formed by a plurality of alternately arranged N-type columns 12 and P-type columns 13. In fig. 1, since the N-type columns are composed of an N-type epitaxial layer, they are denoted by reference numeral 12.

One P-type well 14 is formed at the top of each P-type pillar 13 and each P-type well 14 extends to the surface of the N-type pillar 12 on both sides of the corresponding P-type pillar 13.

And the JFET region 15 is formed by JFET ion implantation in the prior art, and the JFET ion implantation area is defined by self-alignment of the guard ring oxide film or by adopting a photoetching process.

The planar gate structure is formed by superposing a gate oxide film 16a and a polysilicon gate 17 a; a super junction unit is composed of one N-type column 12 and one adjacent P-type column 13, and a planar gate structure above the N-type column 12 of the same super junction unit is of an integral structure.

Each polysilicon gate 17a covers the corresponding P-type well 14 and extends to the surface of the JFET region 15 area adjacent to the P-type well 14, and the surface of the P-type well 14 covered by the polysilicon gate 17a is used for forming a channel. As shown in fig. 1, the gate polysilicon 17a covers the JFET region 15 completely.

A source region 8 comprised of an N + region is formed on the surface of the P-well 14 and the source region 8 and the sides of the polysilicon gate 17a on the P-well 14 are self-aligned.

As shown in fig. 1, the superjunction device further includes the following front structure:

an interlayer film 19, a contact hole 20, a source electrode and a gate electrode composed of a front metal layer 22.

The contact hole 20 passes through the interlayer film 19. The source region 8 is connected to the source through a top corresponding contact hole 20, and the polysilicon gate 17a is connected to the gate through a top corresponding contact hole 20.

The contact hole 20 corresponding to the top of the source region 8 also passes through the source region 8 to contact with the P-type well 14 at the bottom, and a P + doped well contact region 21 is formed at the bottom of the contact hole 20 corresponding to the source region 8.

The super junction device further comprises a back structure:

the N-type epitaxial layer 12 is formed on the surface of the semiconductor substrate 11, the silicon substrate 11 adopts an N-type heavily doped structure and directly forms a drain region of the super junction device, and a drain 23 composed of a back metal layer is formed on the back of the drain region 11.

As can be seen from fig. 1, the polysilicon gate 17a of the planar gate structure may fully cover the JFET region 15, which may generate a large overlap capacitance, i.e., gate-drain capacitance, which is not favorable for reducing the switching loss of the device.

Fig. 2 is a schematic structural diagram of a second conventional superjunction device; the existing second super junction device is obtained by improving the existing first super junction device shown in fig. 1, and the improvement is mainly that a plane gate structure is separated to form a split-gate plane gate structure, and the split-gate plane gate structure is formed by overlapping a gate oxide film 16 and a polysilicon gate 17; a super junction unit is composed of one N-type column 12 and an adjacent P-type column 13, and two separated split gate planar gate structures are included above the N-type column 12 of the same super junction unit. It can be seen that after the split-gate planar gate structure is adopted, the lateral overlapping area between the JFET region 15 and the polysilicon gate 17a is reduced, so that the gate-drain capacitance of the device is reduced, and the switching loss of the device can be reduced.

However, the JFET regions 15 of the second conventional superjunction device are usually formed by JFET ion implantation using the polysilicon gate 7a as a self-aligned condition after the etching process of the polysilicon gate 7a is completed. And after the formation of the source region 8, an annealing drive of the source region 8 is carried out to simultaneously effect activation of the JFET region 15. This makes the JFET region 15 of the second prior art structure less effective in spreading and ultimately affects the on-resistance of the device.

The super junction device of the embodiment of the invention comprises:

referring to fig. 2, a schematic structural diagram of a super junction device according to an embodiment of the present invention is also shown, where a middle region of the super junction device according to the embodiment of the present invention is a current flowing region, a terminal region surrounds a periphery of the current flowing region, a transition region is located between the current flowing region and the terminal region, and fig. 2 shows the transition region and the terminal region; a protective epoxy film (not shown) formed by photolithographic etching of the first oxide film opens the current flow region. In the embodiment of the invention, the thickness of the first oxide film is

The process temperature of the first oxide film is above 800 ℃.

The current flowing region includes the following structure:

the N-type epitaxial layer 12 is subjected to dry etching to form a plurality of grooves; the trenches are filled with a P-type epitaxial layer and form P-type columns 13, N-type columns 12 are formed by the N-type epitaxial layer 12 between the P-type columns 13, and a super junction structure is formed by a plurality of alternately arranged N-type columns 12 and P-type columns 13. In fig. 2, since the N-type columns are composed of an N-type epitaxial layer, they are all denoted by reference numeral 12.

In the embodiment of the present invention, the process conditions of the ion implantation of the P-type well 14 are as follows: the implantation impurity is boron, and the implantation dosage is 3E13cm^-2～1E14cm^-2The implantation energy is 30Kev to 100 Kev.

A JFET region 15, wherein the JFET region 15 is formed through JFET ion implantation, and the JFET ion implantation region is defined by the guard ring oxide film in a self-aligned mode; the doping concentration of the JFET region 15 is smaller than that of the P-type trap 14, the surface of the P-type trap 14 with the superposed impurities of JFET ion implantation still keeps P-type doping, and the JFET region 15 is located between the P-type traps 14 in a self-aligning mode.

In the embodiment of the present invention, the process conditions of the JFET ion implantation in the JFET region 15 are as follows: the implanted impurity is phosphorus, and the implantation dosage is 1E12cm^-2～4E12cm^-2The implantation energy is 30Kev to 100 Kev. Or, the JFET ion implantation of the JFET region 15 is divided into two times with different implantation energies, and the implantation energy distribution corresponding to the two times of implantation is: 30 Kev-60 Kev and 500 Kev-1.5 MeKev, the implantation impurities are all phosphorus, and the implantation dosage is all 1E12cm^-2～4E12cm^-2. In the embodiment of the invention, the JFET ion implantation adopts the protective epoxy film as a self-aligned defined mask, and the protective epoxy film is thicker, so that the JFET ion implantation can adopt higher implantation energy, and the process adjustment of the JFET ion implantation is facilitated.

The split gate planar gate structure is formed by superposing a gate oxide film 16 and a polysilicon gate 17; a super junction unit is composed of one N-type column 12 and an adjacent P-type column 13, and two separated split gate planar gate structures are included above the N-type column 12 of the same super junction unit.

In the embodiment of the invention, the thickness of the gate oxide film 16 is

The polysilicon gate 17 has a thickness of

The conditions of the thermal oxidation process of the gate oxide film 16 are as follows: the process temperature is 1050 ℃, the time of the oxide film deposition process is 60 minutes, the temperature rising rate from 800 ℃ to 1050 ℃ is 5 ℃/minute, and the temperature reduction rate from 1050 ℃ to 800 ℃ is 2 ℃/minute.

Each polysilicon gate 17 covers the corresponding P-type well 14 and extends to the surface of the JFET region 15 area adjacent to the P-type well 14, and the surface of the P-type well 14 covered by the polysilicon gate 17 is used for forming a channel; the split gate planar gate structure reduces the lateral overlapping area between the JFET region 15 and the polysilicon gate 17, thereby reducing the gate-drain capacitance of the device.

Source region 8, which is comprised of an N + region, is formed on the surface of P-well 14 and the sides of source region 8 and polysilicon gate 17 on P-well 14 are self-aligned.

In the embodiment of the present invention, the process conditions of the ion implantation of the source region 8 are as follows: the implantation impurity is phosphorus or arsenic, and the implantation dosage is 3E15cm^-2～8E15cm^-2The injection energy is 30 Kev-100 Kev; and performing rapid thermal annealing activation after the ion implantation of the source region 8 is completed, wherein the process conditions of the rapid thermal annealing corresponding to the source region 8 are as follows: the annealing temperature is 1000-1100 ℃, and the annealing time is 15-30 s.

As shown in fig. 2, the superjunction device further includes the following front structure:

The contact hole 20 passes through the interlayer film 19. The source region 8 is connected to the source through a top corresponding contact hole 20, and the polysilicon gate 17 is connected to the gate through a top corresponding contact hole 20.

The thickness of the interlayer film 19 is 8000 to 10000 angstroms,

The super junction device further comprises a back structure:

In the super junction device according to the first embodiment of the present invention, a 600V N-type super junction MOSFET is taken as an example to describe the parameters in detail:

the resistivity of the semiconductor substrate 11 is 0.001-0.003 ohm cm; the resistance of the N-type epitaxial layer 12 is 1-2 ohm cm, and the thickness is 45-60 microns. In the embodiment of the present invention, the semiconductor substrate 11 is a silicon substrate, and the N-type epitaxial layer 12 is a silicon epitaxial layer.

The depth of the grooves corresponding to the P-type columns 13 is usually 40 micrometers to 45 micrometers, the width of the grooves is 4 micrometers, and the distance between the grooves is 5 micrometers. A buffer layer is formed between the bottom of the trench and the semiconductor substrate 11, and generally, the buffer layer is directly composed of the N-type epitaxial layer 12, the thickness of the buffer layer can be 5 micrometers, for example, and the super junction device has better current impact resistance by arranging the buffer layer.

The JFET ion implantation is carried out before the formation process of the gate oxide film 16, the gate oxide film 16 is a thermal oxide film, the JFET region 15 has a structure which is subjected to annealing promotion through the thermal oxide process of the gate oxide film 16, and the thermal oxide process of the gate oxide film 16 increases the diffusion area of the JFET region 15, so that the drift region resistance can be reduced; the diffusion area of the JFET area 15 is increased, and the area of the P-type well 14 forming the channel is reduced, so that the channel resistance can be reduced; the increase of the diffusion area of the JFET area 15 also increases the PN junction slow-changing effect formed by the JFET area 15 and the P-type well 14, and improves the reliability of the device.

According to the super junction device, the split-gate planar gate structure and the process structure of the JFET area 15 are combined, the split-gate planar gate structure can achieve small coverage on the JFET area 15, and therefore the gate-drain capacitance of the device can be reduced, and the switching loss of the device can be reduced.

The process structure of the JFET area 15 in the embodiment of the invention has a structure for annealing and diffusing by adopting the thermal process of the gate oxide film 16, and can be realized only by placing the JFET ion injection process before the formation process of the gate oxide film 16 in the process, and because the thermal process of the gate oxide film 16 has higher temperature and longer time and also comprises a longer temperature rise and fall process, the thermal process of the gate oxide film 16 can well diffuse the JFET area 15, the diffusion effect of the JFET area 15 is improved, and the improvement of the diffusion effect of the JFET area 15 can obtain the following beneficial technical effects:

1. the JFET region 15 is more diffused, so that the range of the JFET region 15 is enlarged, or the range of the surface high concentration region is enlarged, so that the on-resistance of the device can be reduced, the JFET region 15 belongs to the drift region of the superjunction device as a whole, and the reduced on-resistance of the JFET region 15 corresponds to the drift region resistance.

2. Because the JFET area 15 is more spread, the channel length of the super junction device is shortened, and the on-resistance of the device can be reduced; the decrease in on-resistance due to the decrease in channel length mainly corresponds to the decrease in channel resistance.

3. As the JFET region 15 is more diffused, the PN junction formed by the P-well 14 and the JFET region 15 near the interface of the gate oxide film 16 and the silicon becomes more gradual, reducing the electric field strength at this point under reverse bias conditions of the device, reducing the leakage of the device, and improving the reliability of the device.

In addition, the injection area of JFET ion injection in the embodiment of the invention is directly defined by self-alignment of a guard ring oxide film, and the self-alignment definition has lower process cost; meanwhile, the protective epoxy film is thicker, usually 8000-15000 angstroms, and can bear higher ion implantation energy by using the protective ring oxide film as a mask for JFET ion implantation, so that the design of the device is more convenient. In the prior art, JFET ion implantation is performed after a grid structure comprising a superposed layer structure of a grid oxide film 16 and a polysilicon grid 17 is formed, and the thickness of the superposed layer of the grid oxide film 16 and the polysilicon grid 17 is generally 5000-6000 angstroms and is obviously lower than that of a protection ring oxide film, so that the adjustment of the implantation energy of the JFET ion implantation is easier and the design of a device is more convenient.

In addition, the convenience improvement of the process conditions of the ion implantation of the JFET region 15 and the improvement of the diffusion effect of the JFET region 15 in the embodiment of the present invention are realized only by elaborately designing the formation process of the JFET region 15, and other additional process costs are not required to be added, so the embodiment of the present invention also has the characteristic of low process costs.

The differences between the device of the embodiment of the present invention and the second superjunction device of the prior art will now be described with reference to the accompanying drawings:

as shown in fig. 3A, it is a structural simulation diagram of a second superjunction device in the prior art; as shown in fig. 3B, is a structural simulation diagram of a super junction device according to an embodiment of the present invention; in FIG. 3A, the abscissa is the X coordinate in microns; the ordinate is the Y-coordinate, in microns. The same reference numerals as in fig. 2 are used for the respective regions in fig. 3A. Different depths of color are also used in fig. 3A to indicate different doping concentrations, and the colors of different depths after printing in black and white in fig. 3A correspond to colors of different grayscales. DopingConcentration means doping concentration and NetActive means net doping in cm^-3。

It can be seen that the diffusion area of the JFET region 15 of the superjunction device of the embodiment of the present invention becomes large, as shown in:

the depth Da of the JFET region 15 of the device is larger than the depth Db of the JFET region 15 of the conventional second device, and the width La of the JFET region 15 of the device of the embodiment of the invention, which is diffused to the bottom of the polysilicon gate 17, is larger than the width Lb corresponding to the JFET region 15 of the conventional second device. Therefore, the embodiment of the invention enables the JFET area 15 of the device to be more fully diffused without adding processes.

As shown in fig. 4, the curves of the impurity concentration distribution of the JFET region and the P-type well of the superjunction device according to the embodiment of the present invention and the second superjunction device of the related art are shown, where the curve 101 corresponds to the curve of the device according to the embodiment of the present invention, and the curve 102 is shown in the curve of the second device of the related art. It can be seen that:

the area corresponding to width d2 is the JFET region 15 of the device of the embodiment of the invention; the area corresponding to width d1 is P-type well 14 of the device of the embodiment of the present invention.

The area corresponding to the width d102 is the JFET area 15 of the existing device; the region corresponding to the width d101 is the P-type well 14 of the conventional device.

Width d1 is about 1.2 microns, and width d101 is about 1.7 microns, so the surface of P-type well 14 covered by polysilicon gate 17 is used to form the channel, and the channel length of the device of the embodiment of the invention is reduced, and the on-resistance of the channel part is reduced.

Meanwhile, the JFET area 15 of the device of the embodiment of the invention obtains more diffusion; the width d2 of the JFET region 15 for half of the original package is about 1.1 microns greater than the width d102 of the second prior art device, and the width d102 is about 0.35 microns, which further reduces the on-resistance of the JFET region.

As can be seen from the comparison of fig. 3A, fig. 3B and fig. 4, in the device according to the embodiment of the present invention, the PN junction formed by the P-well and the JFET region becomes more gradual, the electric field strength near the junction under the reverse bias condition of the device is reduced, the leakage characteristic of the device is reduced, and the reliability of the device is improved.

The manufacturing method of the super junction device comprises the following steps:

in the method for manufacturing the super junction device, the middle area of the super junction device is a current flowing area, a terminal area surrounds the periphery of the current flowing area, and a transition area is positioned between the current flowing area and the terminal area; the method comprises the following steps:

step one, forming an N-type epitaxial layer 12 on an N-type semiconductor substrate 11, forming a plurality of grooves in the N-type epitaxial layer 12 by adopting a photoetching definition and dry etching process, filling P-type epitaxial layers in the grooves to form P-type columns 13, forming the N-type columns 12 by the N-type epitaxial layers 12 among the P-type columns 13, and forming a super junction structure by the N-type columns 12 and the P-type columns 13 which are alternately arranged.

In the method of the embodiment of the invention, the manufactured super junction device is an N-type super junction MOSFET with 600V as an example for detailed description: the N-type epitaxial layer 12 is formed on the surface of the semiconductor substrate 11, and the semiconductor substrate 11 adopts an N-type heavily doped structure; preferably, the N-type epitaxial layer 12 is a silicon epitaxial layer, and the semiconductor substrate 11 is a silicon substrate, which is also known as a silicon wafer or a silicon wafer. The drain region of the super junction MOSFET is usually formed on the back surface of the semiconductor substrate 11, so the heavily doped semiconductor substrate 11 is directly adopted, and in the method of the embodiment of the invention, the resistivity of the semiconductor substrate 11 is 0.001-0.003 ohm cm; the resistance of the N-type epitaxial layer 12 is 1-2 ohm cm, and the thickness is 45-60 microns. In the embodiment of the present invention, the semiconductor substrate 11 is a silicon substrate, and the N-type epitaxial layer 12 is a silicon epitaxial layer.

In the method of the embodiment of the invention, the step of forming the super junction structure comprises the following steps:

a dielectric film is deposited on the N-type epitaxial layer 12, the region requiring the trench is defined by trench lithography, and then the trench is formed by dry etching. After the trenches are formed, a P-type epitaxial layer such as a P-type silicon epitaxial layer is deposited in the trenches, and then the P-type epitaxial layer on the surface of the semiconductor substrate 11 is removed by Chemical Mechanical Polishing (CMP), so that the P-type pillars 13 are formed in the trenches. And then removing the dielectric film on the surface or remaining the dielectric film.

The dielectric film can be a single oxide film, for example, an oxide film with a thickness of more than 1 micron, the oxide film can be used as a hard mask during trench etching, an oxide film with a certain thickness is left after trench formation, for example, an oxide film with a thickness of 0.1 micron to 0.2 micron, and during the process of P-type epitaxial filling and CMP, the oxide film is used as a protective layer of the N-type epitaxial layer 12 during CMP, so that the N-type epitaxial layer 12 at the position is not affected by the CMP process to cause defects, and leakage or quality problems are caused.

The dielectric film can also be formed by overlapping a layer of oxide film with the thickness of 0.1-0.15 micron, a layer of SiN film with the thickness of 0.1-0.2 micron and a layer of oxide film with the thickness of more than 1 micron; this allows for better control of uniformity during the fabrication process: for example, after the trench etching is completed, at least a part of the SiN film remains on the oxide film thereunder, and before the P-type epitaxial growth, the SiN film is removed, so that the uniformity of the oxide film before the P-type epitaxial growth is good, and the uniformity of the subsequent epitaxial CMP can be improved.

In a further improvement of the dielectric film formed by stacking the above-described multilayer films, the first oxide film is formed by thermal oxidation, which further improves uniformity.

Step two, forming a P-type well 14 on the top of each P-type column 13 in the current flowing region, wherein each P-type well 14 extends to the surface of the N-type column 12 on both sides of the corresponding P-type column 13.

In the method of the embodiment of the present invention, the sub-steps of forming the P-type well 14 include:

a region of P-type well 14 is formed in the current flow region of the device by P-type well lithography, followed by ion implantation to form P-type well 14. After the P-type well 14 is formed, a high temperature thermal process is performed to complete the drive-in, the temperature of the drive-in is generally higher than 1000 ℃, the time is generally longer than 30min, for example, an annealing process of 1100 ℃ for 120 min to 180 min is used to perform the drive-in.

The process conditions of the P-type well 14 need to meet the requirement of the threshold voltage of the device, and for the device with the threshold voltage of 2-4V, the process conditions of the ion implantation of the P-type well 14 are as follows: the implantation impurity is B, the implantation energy is 30 Kev-100 Kev, and the implantation dosage is 3E13cm^-2～1E14cm^-2. Meanwhile, it is to ensure that when the breakdown voltage of the device occurs, Punch-through (Punch-through) does not occur at the channel, otherwise, Punch-through may occurThe device has large leakage and low breakdown voltage.

And step three, forming a first oxide film on the surface of the semiconductor substrate 11, and then removing the first oxide film in the current flowing area by adopting a photoetching definition and oxide film etching process to form a guard ring oxide film, wherein the current flowing area is opened by the guard ring oxide film.

In the method of the embodiment of the present invention, the etched protective epoxy film covers the transition region and most or all of the termination region.

One improvement is that the first oxide film is a silicon oxide film and is formed by adopting a thermal oxidation process at the temperature higher than 800 ℃, and the dangling bonds and unstable interface states can be reduced at the Si-SiO2 interface at the high temperature of more than 800 ℃, so that the voltage bearing capacity of the terminal region is further improved, and the consistency of the breakdown voltage of the device is improved. The thickness of the guard ring oxide film is required to be set according to the breakdown voltage (BVds) of the device, the thickness of the protective epoxy film is required to be thicker as the BVds is larger, and the thickness of the protective epoxy film required for the super junction device of 600V or more is more than 8000 angstroms and can be set to be larger than 8000 angstroms

And fourthly, taking the protective epoxy film as a self-aligned mask, carrying out JFET ion implantation to form a JFET region 15 in the current flowing region in a self-aligned mode, wherein the doping concentration of the JFET region 15 is smaller than that of the P-type well 14, the surface of the P-type well 14 with the superposed impurities of the JFET ion implantation still keeps P-type doping, and the JFET region 15 is located between the P-type wells 14 in a self-aligned mode.

In the method of the embodiment of the present invention, the process conditions of the JFET ion implantation in the JFET region 15 are as follows: the implanted impurity is phosphorus, and the implantation dosage is 1E12cm^-2～4E12cm^-2The implantation energy is 30Kev to 100 Kev.

Or, the JFET ion implantation of the JFET region 15 is divided into two times with different implantation energies, and the implantation energy distribution corresponding to the two times of implantation is: 30 Kev-60 Kev and 500 Kev-1.5 MeKev, implanting impuritiesAre all phosphorus, and the implantation dose is all 1E12cm^-2～4E12cm^-2. Since the guard ring oxide film is thick, a large implantation energy can be used, which can facilitate the conditions of implantation energy for the JFET ion implantation and also facilitate the adjustment of the structure of the JFET region 15.

Fifthly, forming a gate oxide film 16 by adopting a thermal oxidation process, and then forming a polysilicon gate 17; annealing and propelling the impurities in the JFET region 15 by the thermal oxidation process of the gate oxide film 16 are realized by utilizing the characteristic that the JFET ion implantation is placed before the thermal oxidation process of the gate oxide film 16, so that the diffusion area of the JFET region 15 is increased, and the resistance of a drift region can be reduced; the diffusion area of the JFET area 15 is increased, and the area of a channel formed by the P-type well 14 is reduced, so that the channel resistance can be reduced; the increase of the diffusion area of the JFET area 15 also increases the PN junction slow-changing effect formed by the JFET area 15 and the P-type well 14, and improves the reliability of the device.

In the method of the embodiment of the invention, for the super junction MOSFET of 500V-700V, the thickness of the gate oxide film 16 is

The polysilicon gate 17 has a thickness of

In the method of the embodiment of the invention, in order to obtain a high-quality gate oxide film 16, the high-temperature oxidation temperature is set around 1050 ℃, the time is adjusted according to the thickness of the gate oxide film 16, for a common high-voltage super-junction MOSFET, the thickness of the gate oxide film 16 is generally about 1000 angstroms, the required high-temperature deposition time is about 60 minutes, and the time of temperature rise and temperature reduction in a high-temperature stage is well controlled, for example, the temperature rise speed is 5 ℃/minute from 800 ℃ to 1050 ℃, the temperature reduction speed is set to be less than 2 ℃/minute from 1050 ℃, so that the quality and the consistency of the gate oxide film 16 are further ensured.

And sixthly, etching the polysilicon gate 17 and the gate oxide film 16 in sequence by adopting a photoetching definition and etching process to form the split-gate planar gate structure formed by overlapping the etched gate oxide film 16 and the polysilicon gate 17.

The split-gate planar gate structure is positioned in the current flowing region, and a super junction unit is formed by one N-type column 12 and one adjacent P-type column 13; in the current flowing region, two separated split-gate planar gate structures are included above the N-type column 12 of the same super junction unit; the polysilicon gate 17 corresponding to each split gate planar gate structure covers the corresponding P-type well 14 and extends to the surface of the JFET region 15 area adjacent to the P-type well 14, and the surface of the P-type well 14 covered by the polysilicon gate 17 is used for forming a channel; the split gate planar gate structure reduces the lateral overlapping area between the JFET region 15 and the polysilicon gate 17, thereby reducing the gate-drain capacitance of the device.

Seventhly, photoetching and N + ion implantation are adopted to implant a source region 8 consisting of an N + region on the surface of the P-type well 14 in the current flowing region, and the source region 8 and the side face, located on the P-type well 14, of the polysilicon gate 17 are self-aligned.

The process conditions of the ion implantation of the source region 8 are as follows: the implantation impurity is phosphorus or arsenic, and the implantation dosage is 3E15cm^-2～8E15cm^-2The injection energy is 30 Kev-100 Kev; and performing rapid thermal annealing activation after the ion implantation of the source region 8 is completed, wherein the process conditions of the rapid thermal annealing corresponding to the source region 8 are as follows: the annealing temperature is 1000-1100 ℃, and the annealing time is 15-30 s.

In other example methods, the source region can also be activated using thermal annealing, for example, annealing at 950 ℃ for 30 minutes; the activation temperature can also be set between 800 ℃ and 950 ℃ and the time between 30 minutes and-60 minutes.

The method also comprises the following steps:

and step eight, depositing an interlayer film 19, and forming a contact hole 20 penetrating through the interlayer film 19 by adopting a photoetching and etching process.

The interlayer film 19 is a combination of an undoped oxide film and a BPSG film. The thickness of the interlayer film 19 is

In the etching of the contact hole 20, N + at the bottom of the contact hole, i.e., the source region 18, needs to be etched, i.e., over-etching of silicon is needed, the over-etching amount of silicon can be 2000 angstroms to 4000 angstroms, and the over-etching amount of silicon specifically needs to be determined according to the implantation conditions of ion implantation, i.e., implantation dose and implantation energy, corresponding to the source region 18. Since the contact hole 20 penetrates the N +, i.e. the range of the source region 18, the contact problem between the P-type well 14 and the metal due to the overall implantation of the source region 18 in the region outside the polysilicon gate 17 is avoided, and the normal electrical characteristics are ensured.

The method also comprises the step of performing P + ion implantation at the bottom of the contact hole 20 to form a well contact region 21 after the opening of the contact hole 20 is formed and before metal filling. Preferably, the P-type impurity of the well contact region 21 is B, BF2, or a combination of B and BF2, and the implantation energy is generally 30Kev to 80Kev, and the implantation dose is 1E15cm^-2～3E15cm^-2The current surge resistance of the device can be improved by optimizing the injection conditions. In order to better improve the softness of the reverse recovery process of the body diode, the energy and dose of the P-type implantation of the well contact region 21 can also be reduced, for example, the energy can be BF2, 5Kev 40KEV, 5E14cm^-2～2E15cm^-2The dose is selected so that the energy is selected primarily to take into account the capabilities of the ion implantation equipment in order to ensure the minimum dose to form the ohmic contacts.

After the etching of the contact hole 20 and the injection of P + ions at the bottom are finished, a blocking layer formed by overlapping Ti and TiN is deposited, then metal tungsten (W) is deposited to fill the opening of the contact hole 20, the thickness of W can be set to 4000 angstroms for the opening with the width of 0.6 micron, and then plasma dry etching is carried out to completely remove the metal on the surface.

Ninthly, performing front metal deposition to form a front metal layer 22, forming the gate and the source composed of the front metal layer 22 by adopting a photoetching and metal etching process, and connecting each source region 18 and the corresponding P-type well 14 to the source through the contact hole 22 with the same top; the polysilicon gate 17 is connected to the gate through the corresponding contact hole 22 at the top.

The front metal layer 22 can be ALSi, AlSiCu, or can have a barrier layer, which can be Ti/TiN, i.e., a stack of Ti and TiN, or TiN. The total thickness of the front metal layer 22 is generally 4 μm to 6 μm.

And then thinning the back surface of the semiconductor substrate 11, and forming a drain region by using the N + region formed in the thinned semiconductor substrate 11, wherein the drain region can be directly formed by the heavily doped semiconductor substrate 11, or formed by the semiconductor substrate 11 and N-type heavily doped ion implantation. And then depositing a back metal layer 23 on the back of the semiconductor substrate 11, namely the drain region 11 to form a drain electrode.

The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims

1. a super junction device, the middle region of the super junction device is a current flow region, a terminal region surrounds the periphery of the current flow region, and a transition region is located between the current flow region and the terminal region; it is characterized in that : the protective epoxy film formed by the photolithographic etching of the first oxide film opens the current flow area;

The following structures are included in the current flow region:

N-type epitaxial layer, the N-type epitaxial layer is dry-etched to form a plurality of trenches; the trenches are filled with P-type epitaxial layers and form P-type pillars, and the P-type pillars are formed by the gaps between the P-type pillars. The N-type epitaxial layer constitutes an N-type pillar, and a superjunction structure consisting of a plurality of alternately arranged N-type pillars and P-type pillars;

A P-type well is formed on the top of each of the P-type pillars, and each of the P-type wells extends to the surfaces of the N-type pillars on both sides of the corresponding P-type pillar;

JFET region, the JFET region is formed by JFET ion implantation and the region of the JFET ion implantation is defined by the self-alignment of the guard epoxy film; the doping concentration of the JFET region is less than that of the P-type well concentration, the surface of the P-type well superimposed with the impurities implanted by the JFET ion is still kept as P-type doping, so that the JFET region is self-aligned between the P-type wells;

The split gate planar gate structure is formed by stacking a gate oxide film and a polysilicon gate; a super junction unit is formed by one of the N-type pillars and an adjacent one of the P-type pillars. Above the type pillar includes two separate split gate planar gate structures;

Each of the polysilicon gates covers the corresponding P-type well and extends to the surface of the JFET region adjacent to the P-type well, and the surface of the P-type well covered by the polysilicon gate is used to form a channel ; The split-gate planar gate structure reduces the lateral overlap region between the JFET region and the polysilicon gate, thereby reducing the gate-to-drain capacitance of the device;

A source region consisting of an N+ region is formed on the surface of the P-type well, and the source region and the side surface of the polysilicon gate located on the P-type well are self-aligned;

The JFET ion implantation is performed before the formation process of the gate oxide film, and the gate oxide film is a thermal oxide film, so that the JFET region has a structure that is annealed and advanced through the thermal oxidation process of the gate oxide film, so The thermal oxidation process of the gate oxide film increases the diffusion region of the JFET region, which can reduce the resistance of the drift region; the increase of the diffusion region of the JFET region also reduces the region where the P-type well forms the channel, which can reduce the Channel resistance; the increase of the diffusion area of the JFET region also increases the gradual change effect of the PN junction formed by the JFET region and the P-type well, improving the reliability of the device.

2. The superjunction device according to claim 1, wherein the thickness of the first oxide film is

3 . The superjunction device of claim 2 , wherein the process temperature of the first oxide film is 800° C. or higher. 4 .

4. The superjunction device of claim 1, wherein the gate oxide film has a thickness of

The thickness of the polysilicon gate is

5. The superjunction device according to claim 4, wherein the thermal oxidation process conditions of the gate oxide film are as follows: the process temperature is 1050°C, and the oxide film deposition process time is 60 minutes, ranging from 800°C to 1000°C. The rate of temperature increase at 1050°C was 5°C/min, and the rate of temperature drop from 1050°C to 800°C was 2°C/min.

6 . The superjunction device according to claim 1 , wherein the process conditions for the JFET ion implantation in the JFET region are: the implantation impurity is phosphorus, the implantation dose is 1E12cm ^-2 -4E12cm ^-2 , and the implantation energy 30Kev～100Kev;

Alternatively, the JFET ion implantation in the JFET region is divided into two times with different implantation energies, and the corresponding implantation energy distributions of the two implantations are: 30Kev～60Kev and 500Kev～1.5MeKev, the implanted impurities are all phosphorus, and the implantation dose is both 1E12cm ^-2 to 4E12cm ^-2 .

7 . The superjunction device according to claim 1 , wherein the process conditions for the ion implantation of the P-type well are as follows: the implanted impurity is boron, the implantation dose is 3E13cm ^-2 -1E14cm ^-2 , and the implantation energy is 30Kev. 8 . ~100Kev.

8 . The superjunction device according to claim 1 , wherein the process conditions for the ion implantation in the source region are: the implantation impurities are phosphorus or arsenic, the implantation dose is 3E15cm ⁻² to 8E15cm ⁻² , and the implantation energy is 8E15cm −2 . 30Kev～100Kev; after the ion implantation in the source region is completed, rapid thermal annealing is performed to activate, and the process conditions of the rapid thermal annealing corresponding to the source region are: annealing temperature is 1000℃～1100℃, and annealing time is 15s～30s.

9. A method for manufacturing a superjunction device, wherein a middle region of the superjunction device is a current flow region, a termination region surrounds the periphery of the current flow region, and a transition region is located between the current flow region and the termination region; It is characterized in that, comprises the following steps:

Step 1. An N-type epitaxial layer is formed on an N-type semiconductor substrate, a plurality of trenches are formed in the N-type epitaxial layer by a photolithography definition and a dry etching process, and a P-type epitaxial layer is filled in the trenches The layers form a P-type column, an N-type column is formed by the N-type epitaxial layer between each of the P-type columns, and a superjunction structure formed by a plurality of alternately arranged N-type columns and P-type columns;

Step 2: A P-type well is formed on the top of each of the P-type pillars in the current flow region, and each of the P-type wells extends to the corresponding N-type pillars on both sides of the P-type pillar. surface;

Step 3: A first oxide film is formed on the surface of the semiconductor substrate, and then a process of photolithography definition and oxide film etching is used to remove the first oxide film in the current flow area to form a protective epoxy film, so The protective epoxy film opens the current flow area;

Step 4. Using the protective epoxy film as a self-aligned mask, perform JFET ion implantation to form a JFET region in the current flow region by self-alignment, and the doping concentration of the JFET region is lower than that of the P-type well doping concentration, the surface of the P-type well superimposed with the impurities implanted by the JFET ion is still kept as P-type doping, so that the JFET region is self-aligned between the P-type wells;

Step 5: Use a thermal oxidation process to form a gate oxide film, and then form a polysilicon gate; utilize the feature that the JFET ion implantation is placed before the thermal oxidation process of the gate oxide film to realize the thermal oxidation process of the gate oxide film. The impurities in the JFET region are annealed and advanced, so that the diffusion region of the JFET region is increased, and the resistance of the drift region can be reduced; the diffusion region of the JFET region is increased and the region of the channel formed by the P-type well is reduced at the same time, The channel resistance can be reduced; the increase of the diffusion area of the JFET region also increases the gradual change effect of the PN junction formed by the JFET region and the P-type well, improving the reliability of the device;

Step 6: Etching the polysilicon gate and the gate oxide film sequentially by using a photolithography definition and etching process to form the split gate formed by superimposing the etched gate oxide film and the polysilicon gate Planar grid structure;

The split gate planar gate structure is located in the current flow region, and a super junction unit is formed by one of the N-type pillars and an adjacent one of the P-type pillars; in the current flow region, in the same super junction The unit above the N-type pillar includes two separate split-gate planar gate structures; the polysilicon gate corresponding to each split-gate planar gate structure covers the corresponding P-type well and extends to the P-type well The surface of the JFET region adjacent to the type well, and the surface of the P-type well covered by the polysilicon gate is used to form a channel; the split-gate planar gate structure makes the JFET region and the polysilicon gate separate. The lateral overlap area between them is reduced, thereby reducing the gate-to-drain capacitance of the device;

Step 7. Use photolithography and N+ ions to implant the surface of the P-type well in the current flow region into a source region composed of N+ regions, and the source region and the polysilicon gate are located in the P-type well. self-aligning on the sides.

10 . The method for manufacturing a superjunction device according to claim 9 , wherein in step 3, the thickness of the first oxide film is 10 .

The process temperature of the first oxide film is 800°C or higher.

11. The method for manufacturing a superjunction device according to claim 9, wherein the gate oxide film formed in step 5 has a thickness of

The thickness of the polysilicon gate is

12 . The method for manufacturing a superjunction device according to claim 11 , wherein the thermal oxidation process conditions of the gate oxide film are as follows: the process temperature is 1050° C., the oxide film deposition process time is 60 minutes, and 12 . The temperature increase rate from 800°C to 1050°C was 5°C/min, and the temperature drop rate from 1050°C to 800°C was 2°C/min.

13. The method for manufacturing a superjunction device according to claim 9, wherein in step 4, the process conditions for the JFET ion implantation in the JFET region are: the implantation impurity is phosphorus, and the implantation dose is 1E12cm ^-2 ～4E12cm ^-2 , the injection energy is 30Kev～100Kev;

14. The method for manufacturing a superjunction device according to claim 9, wherein in step 2, the process conditions for the ion implantation of the P-type well are as follows: the implanted impurity is boron, and the implantation dose is 3E13cm ^-2 -1E14cm ^-2 , the injection energy is 30Kev～100Kev.

15 . The method for manufacturing a superjunction device according to claim 9 , wherein in step 7, the process conditions for the ion implantation in the source region are: the implantation impurities are phosphorus or arsenic, and the implantation dose is 3E15cm ⁻² ~ 15 . 8E15cm ^-2 , the implantation energy is 30Kev～100Kev; after the ion implantation in the source region is completed, rapid thermal annealing is performed for activation, and the process conditions of the rapid thermal annealing corresponding to the source region are: the annealing temperature is 1000 ℃～1100 ℃, annealing The time is 15s to 30s.