CN118823911B

CN118823911B - Access control system, receiving device, receiving method and transmission system

Info

Publication number: CN118823911B
Application number: CN202411296695.2A
Authority: CN
Inventors: 詹敏; 赵士龙; 金吕新
Original assignee: Hangzhou Hikvision Digital Technology Co Ltd
Current assignee: Hangzhou Hikvision Digital Technology Co Ltd
Priority date: 2024-09-14
Filing date: 2024-09-14
Publication date: 2024-12-03
Anticipated expiration: 2044-09-14
Also published as: CN118823911A

Abstract

The embodiment of the application provides an access control system, receiving equipment, a receiving method and a transmission system, which are used for receiving wiegand data through a serial interface with two pins, realizing high-speed sampling, remarkably improving data processing efficiency, and realizing data storage by utilizing a direct memory access technology, thereby greatly reducing the burden of a processor. More importantly, the method can realize the receiving and processing of the wiegand data without modifying or adding an external circuit to hardware equipment, and reduces the cost and complexity of the receiving and processing of the wiegand data. In addition, the receiving device has excellent compatibility, can receive and analyze wiegand data in various formats, accurately extracts information according to a wiegand protocol, and greatly improves flexibility and expansibility of wiegand data reception.

Description

Access control system, receiving equipment, receiving method and transmission system

Technical Field

The application relates to the technical field of security systems, in particular to an access control system, receiving equipment, a receiving method and a transmission system.

Background

In the existing access control system, the access control system comprises a card reader, a processor and access control equipment, the access control system receives wiegand signals from the card reader through DATA0 and DATA1 signal lines, hardware equipment of the access control system is required to be modified in order to enable the processor to receive and process the wiegand signals, and an external differential amplifying circuit and an external signal modulating circuit are added, so that the implementation cost and complexity of the access control system are increased, and meanwhile the implementation difficulty of a scheme is improved. And the processor of the access control system not only needs to directly participate in the whole process of receiving and processing the wiegand data, but also needs to consider other system tasks, so that the burden of the processor is increased, and the data processing efficiency is reduced. Secondly, because the technology needs to preset the wiegand format before implementation, the technology cannot be compatible with a plurality of different wiegand formats, and the flexibility and expansibility of the system are limited.

Disclosure of Invention

The embodiment of the application aims to provide an access control system, receiving equipment, a receiving method and a transmission system, so as to reduce the cost and complexity of receiving and processing wiegand data, reduce the burden of a processor and improve the flexibility and expansibility of wiegand data reception. The specific technical scheme is as follows:

in a first aspect, the embodiment of the application provides an access control system, which comprises card reading equipment, control equipment and access control equipment;

The card reading device comprises a processor and two pins;

the control device comprises a processor, a serial interface with two pins, the two pins and a memory;

the processor of the card reading device is used for responding to card reading operation, acquiring access control card information of an access control card triggering the card reading operation, and packaging the access control card information into wiegand data;

The serial interface with two pins is used for periodically sampling the two pins of the control device and storing sampled data in the memory through direct memory access;

The processor of the control device is used for responding to the completion of the receiving of wiegand data, reading data stored in the memory through direct memory access as first data, taking the first combined data as a separator, separating the first data into a plurality of sub-data composed of second combined data and/or third combined data, respectively determining first wiegand data corresponding to each sub-data, combining each first wiegand data to obtain second data, analyzing the second data according to a preset wiegand protocol to obtain entrance guard card information, authenticating the entrance guard card information, and sending a passing instruction to the entrance guard device if the authentication is passed;

the access control equipment is used for responding to the passing instruction and entering a passing permission state.

The first combined data is a combination formed by first unit data and second unit data, wherein the first unit data is data obtained by sampling a first pin when the two pins receive a wiegand idle signal, and the second unit data is data obtained by sampling a second pin when the two pins receive the wiegand idle signal;

The second combination data is a combination formed by third unit data and fourth unit data, the third unit data is data obtained by sampling a first pin when the two pins receive wiegand data 0, and the fourth unit data is data obtained by sampling a second pin when the two pins receive wiegand data 0;

The third combination data is a combination formed by fifth unit data and sixth unit data, the fifth unit data is data obtained by sampling a first pin when the two pins receive wiegand data 1, and the sixth unit data is data obtained by sampling a second pin when the two pins receive wiegand data 1.

In one possible implementation, the card reading device is a microcontroller, the microcontroller including a processor and two pins;

the control device includes a system-on-chip including a processor, a serial interface having two pins, the two pins, and a memory.

In one possible implementation, the access control system includes a plurality of control devices,

The processor of the control device is also used for responding to card reading operation, acquiring access control card information of an access control card triggering the card reading operation, packaging the access control card information into wiegand data, and sending the wiegand data to other control devices through the two pins of the control device.

In a second aspect, an embodiment of the present application provides a receiving device, where the receiving device includes a processor, a serial interface having two pins, the two pins, and a memory;

the serial interface with two pins is used for periodically sampling the two pins and storing the sampled data in the memory through direct memory access;

The processor is used for responding to the completion of the receiving of the wiegand data, reading the data stored in the memory through direct memory access as first data, taking the first combined data as a separator, separating the first data into a plurality of sub-data composed of second combined data and/or third combined data, respectively determining first wiegand data corresponding to each sub-data, combining each first wiegand data to obtain second data, and analyzing the second data according to a preset wiegand protocol to obtain first information;

In a possible implementation manner, the processor is further configured to periodically sample the two pins, and parse the sampled data through a preset serial protocol to obtain second information until a first level signal is sampled from any one of the pins;

The processor is further configured to enable the direct memory access and send an acquisition instruction to the serial interface having two pins in response to sampling the first level signal from any of the pins;

The serial interface with two pins is specifically configured to respond to the acquisition instruction, periodically sample the two pins, and store the sampled data in the memory through the direct memory access;

The first level signal is a level signal other than a second level signal, the second level signal is a level signal on the two pins when the wiegand idle signal is received, and the total transmission length of the direct memory access is configured to be greater than a preset length threshold.

In one possible implementation, the serial interface with two pins includes a chip select pin;

the processor is further configured to maintain a level of the chip select pin at a first level;

the processor sends an acquisition instruction to the serial interface with two pins, comprising:

The processor adjusts the level of the chip select pin to a second level;

wherein the first level is one of a high level and a low level, and the second level is the other of the high level and the low level.

In a possible implementation manner, the processor is further configured to record, in the memory, a pin sampled to the first level signal as a target pin in response to sampling the first level signal from any one of the pins;

The processor is further configured to read a recorded target pin if the first data starts with the first combined data, and determine second wiegand data corresponding to the target pin;

the processor combines the first wiegand data to obtain second data, including:

If the first data starts with the first combined data, sequentially arranging the first wiegand data corresponding to each piece of sub-data in the second wiegand data according to the sequence in the first data to obtain second data;

if the first data do not start with the first combined data, sequentially arranging the first wiegand data corresponding to each piece of sub data according to the sequence in the first data to obtain second data;

The first pin corresponds to wiegand data 0, the second pin corresponds to wiegand data 1, the first pin is a pin which is positioned in the first level signal when receiving wiegand data 0, and the second pin is a pin which is positioned in the first level signal when receiving wiegand data 1.

In a possible implementation manner, the processor is further configured to periodically read, as third data, data recorded by the memory in a last cycle; if the third data comprises the first combined data which continuously appears, determining that the reception of the wiegand data is finished;

wherein the processor reads the data recorded in the memory in the last cycle for a period greater than the Wiegand data maximum bit interval time.

In a third aspect, an embodiment of the present application provides a receiving method, where the method includes:

Periodically sampling the two pins through a serial interface with the two pins, and storing the sampled data in a memory through direct memory access;

Reading data stored in the memory through direct memory access as first data in response to completion of reception of wiegand data;

dividing the first data into a plurality of sub-data composed of second combined data and/or third combined data by taking the first combined data as a separator;

respectively determining first wiegand data corresponding to each piece of sub data, and combining the first wiegand data to obtain second data;

Analyzing the second data according to a preset Wiegand protocol to obtain first information, wherein the ordering of each first Wiegand data in the second data is the same as the ordering of corresponding sub-data in the first data, the first combined data is a combination formed by the first unit data and the second unit data, the first unit data is data obtained by sampling a first pin when the two pins receive Wiegand idle signals, the second unit data is data obtained by sampling a second pin when the two pins receive Wiegand idle signals, the second combined data is a combination formed by a third unit data and a fourth unit data, the third unit data is data obtained by sampling a first pin when the two pins receive Wiegand data 0, the fourth unit data is data obtained by sampling a second pin when the two pins receive Wiegand data 0, the third combined data is data obtained by sampling a fifth unit data and a sixth unit data, and the fifth unit data is data obtained by sampling a second pin when the two pins receive Wiegand data 1.

In one possible embodiment, the method further comprises:

periodically sampling the two pins, analyzing the sampled data through a preset serial protocol to obtain second information until any pin is sampled to a first level signal;

Enabling the direct memory access in response to sampling a first level signal from any of the pins and sending an acquisition instruction to the serial interface having two pins;

Responding to the acquisition instruction, periodically sampling the two pins through the serial interface with the two pins, and storing sampled data in the memory through the direct memory access;

In one possible embodiment, the method further comprises:

Maintaining the level of a chip select pin at a first level, wherein the chip select pin is arranged on the serial interface with two pins;

The sending the acquisition instruction to the serial interface with two pins comprises:

adjusting the level of the chip select pin to a second level;

In one possible embodiment, the method further comprises:

Recording a pin sampled to the first level signal in the memory as a target pin in response to sampling the first level signal from any one of the pins;

if the first data starts with the first combined data, reading a recorded target pin, and determining second wiegand data corresponding to the target pin;

The step of combining the first wiegand data to obtain second data comprises the following steps:

In one possible embodiment, the method further comprises:

Periodically reading the data recorded by the memory in the last period as third data, and if the third data comprises continuously-occurring first combined data, determining that the reception of the wiegand data is completed;

And reading the data recorded in the memory in the last period, wherein the period of reading the data recorded in the memory in the last period is longer than the maximum bit interval time of the Wiegand data.

In a fourth aspect, an embodiment of the present application provides a receiving apparatus, including:

the sampling module is used for periodically sampling the two pins through the serial interface with the two pins and storing the sampled data in the memory through direct memory access;

the reading module is used for responding to the completion of the reception of the wiegand data, and the processor is used for reading the data stored in the memory through direct memory access as first data;

the separation module is used for taking the first combined data as a separator, and separating the first data into a plurality of sub-data composed of second combined data and/or third combined data through the processor;

The combination module is used for respectively determining first wiegand data corresponding to each piece of sub-data through the processor and combining the first wiegand data to obtain second data;

The device comprises a processor, an analyzing module, a third unit data and a fourth unit data, wherein the processor analyzes the second data according to a preset Wiegand protocol to obtain first information, the ordering of each first Wiegand data in the second data is the same as the ordering of corresponding sub-data in the first data, the first combined data is formed by the first unit data and the second unit data, the first unit data is data obtained by sampling a first pin when the two pins receive Wiegand idle signals, the second unit data is data obtained by sampling a second pin when the two pins receive Wiegand idle signals, the second combined data is a combination formed by third unit data and fourth unit data, the third unit data is data obtained by sampling a first pin when the two pins receive Wiegand data 0, the fourth unit data is data obtained by sampling a second pin when the two pins receive Wiegand data 0, the third combined data is data obtained by sampling a fifth unit data and a sixth unit data obtained by sampling a fifth pin, and the fourth unit data is data obtained by sampling a sixth pin when the two pins receive Wiegand data 1.

In a fifth aspect, an embodiment of the present application provides a transmission system, including a transmitting apparatus and a receiving apparatus;

The transmitting device comprises a processor and two pins;

The receiving device comprises a processor, a serial interface with two pins, the two pins and a memory;

the processor of the sending device is configured to obtain a first message, and encapsulate the first message into wiegand data; transmitting the wiegand data to the receiving device through the two pins of the transmitting device;

The serial interface with two pins is used for periodically sampling the two pins of the receiving device and storing sampled data in the memory through direct memory access;

The processor of the receiving device is used for responding to the completion of the receiving of wiegand data, reading the data stored in the memory through direct memory access as first data, taking the first combined data as a separator, separating the first data into a plurality of sub-data composed of second combined data and/or third combined data, respectively determining first wiegand data corresponding to each sub-data, combining each first wiegand data to obtain second data, analyzing the second data according to a preset wiegand protocol, and obtaining first information;

The method comprises the steps of obtaining first data, second data, third data and fourth data, wherein the ordering of the first wiegand data in the second data is the same as the ordering of corresponding sub-data in the first data, the first combined data is a combination formed by the first unit data and the second unit data, the first unit data is a combination formed by the first pin and the second pin when the two pins receive wiegand idle signals, the second unit data is a combination formed by the third unit data and the fourth unit data when the two pins receive wiegand data 0, the third combined data is a combination formed by the first pin and the fourth unit data when the two pins receive wiegand data 0, the second pin is a combination formed by the fifth unit data and the sixth unit data, the fifth unit data is a combination formed by the first pin and the sixth unit data when the two pins receive wiegand data 1, and the sixth unit data is obtained by sampling the second pin 1.

In one possible embodiment, the transmitting device comprises a microcontroller comprising a processor and two pins;

The receiving device includes a system-on-chip including a processor, a serial interface having two pins, the two pins, and a memory.

The embodiment of the application has the beneficial effects that:

the receiving device provided by the embodiment of the application receives the wiegand data through the serial interface with two pins, realizes high-speed sampling, remarkably improves the data processing efficiency, and realizes data storage by utilizing a direct memory access technology, thereby greatly reducing the burden of a processor. More importantly, the method can realize the receiving and processing of the wiegand data without modifying or adding an external circuit to hardware equipment, and reduces the cost and complexity of the receiving and processing of the wiegand data. In addition, the receiving device has excellent compatibility, can receive and analyze wiegand data in various formats, accurately extracts information according to a wiegand protocol, and greatly improves flexibility and expansibility of wiegand data reception.

Of course, it is not necessary for any one product or method of practicing the application to achieve all of the advantages set forth above at the same time.

Drawings

In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the application, and other embodiments may be obtained according to these drawings to those skilled in the art.

FIG. 1 is a schematic diagram of a wiegand data representation method;

FIG. 2 is a schematic diagram of the significance of bits in the Wiegand 26 format;

FIG. 3 is a schematic diagram showing the active time of the data bits of the root of the Chinese herb;

FIG. 4 is a diagram of the maximum bit interval of Wiegand data;

FIG. 5 is a schematic diagram of a Wiegand data sample;

FIG. 6 is a schematic diagram of a two-wire serial peripheral interface data transfer;

Fig. 7a is a first schematic diagram of a wiegand data transmission flat state according to an embodiment of the present application;

fig. 7b is a second schematic diagram of a wiegand data transmission flat state according to an embodiment of the present application;

Fig. 7c is a third schematic diagram of a wiegand data transmission flat state according to an embodiment of the present application;

fig. 7d is a fourth schematic diagram of a wiegand data transmission flat state according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a receiving device according to an embodiment of the present application;

Fig. 9 is a flowchart of a wiegand data receiving process according to an embodiment of the present application;

Fig. 10 is a schematic diagram of a first configuration of a transmission system according to an embodiment of the present application;

Fig. 11 is a schematic diagram of a second structure of a transmission system according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of an access control system according to an embodiment of the present application;

FIG. 13 is a flowchart of authentication of an access control system according to an embodiment of the present application;

Fig. 14 is a flowchart of a receiving method according to an embodiment of the present application;

Fig. 15 is a schematic structural diagram of a receiving device according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by the person skilled in the art based on the present application are included in the scope of protection of the present application.

For a more clear description of the receiving device provided by the present application, the following will explain the relevant terms referred to herein:

Wiegand protocol Wiegand is an internationally unified standard, a communication protocol established by motorola corporation. Is commonly used to transfer data between a reader (readhead) and an access controller. And after the card reader identifies the effective card, the access control card information is sent to the controller in a wiegand protocol mode, and the controller verifies that the access control card information is effective and then opens the door. The wiegand protocol does not define the baud rate of the communication nor the data length. The wiegand protocol is mainly defined as a DATA transmission mode in which two DATA lines, namely DATA0 (i.e., DATA 0) and DATA1 (i.e., DATA 1), respectively transmit 0 and 1. The wiegand interface is typically composed of 3 wires, which are DATA0, DATA1, and GND (Ground), none of which are shown in the structural schematic provided by the present application. Only two DATA lines are needed in the transmission of the wiegand DATA, one is DATA0, and the other is DATA1. Exemplary wiegand data representation referring to fig. 1, fig. 1 is a schematic diagram of a wiegand data representation.

Wiegand format Wiegand protocol has various formats, commonly used are 26 bits (Binary digit, abbreviated as "bit"), 34 bits, 58 bits, and so on. A typical wiegand 26 format is shown in fig. 2, and fig. 2 is a schematic diagram of the meaning of each bit of the wiegand 26 format. Wherein the 0 th bit is the even parity bit of the 1 st to 12 th bits, the 25 th bit is the odd parity bit of the 13 th to 24 th bits, namely E represents even parity bit, D represents data bit and O represents odd parity bit in figure 2. Other formats are similar, with differences in data length and check bit length.

Wiegand data bit valid time Wiegand data is represented by a low level, and bit valid time period 1 refers to a low level duration corresponding to one bit data, as shown in FIG. 3.

The wiegand data maximum bit interval time, bit interval time period 2, refers to the interval time between two bit data in the same wiegand transmission, as shown in fig. 4.

SPI (SERIAL PERIPHERAL INTERFACE ), mainly used as interface protocol for main control chip to configure peripheral chip. Is commonly used in EEPROM (read-write memory), FLASH (FLASH memory), real-time clock, AD converter (Analog-to-Digital Converter ), and between digital signal processor and digital signal decoder. The serial peripheral interface is a high-speed, full duplex, synchronous, serial, master-slave architecture communication bus.

Dual SPI (Dual SERIAL PERIPHERAL INTERFACE ), serial peripheral interface has four wires including CS (CHIP SELECT, chip select signal), CLK (Clock signal), MOSI (Master Output Slave Input ), MISO (Master Input Slave Output, master input Slave output), serial peripheral interface works in full duplex mode, MOSI and MISO are input and output respectively at the same time, i.e. input and output are accomplished by one wire only, MOSI and MISO wires are independently operated in any Clock cycle, and are used for transmission and reception respectively. Whereas the dual-wire serial peripheral interface changes the full duplex serial peripheral interface into half duplex, the dual-wire serial peripheral interface also uses four wires, but MOSI becomes DATA0, MISO becomes DATA1, and DATA transmission is performed by using two wires of DATA0 and DATA1 simultaneously at the time of input and output, so that unidirectional DATA transmission speed is double that of the serial peripheral interface, for half duplex communication, where DATA0 and DATA1 refer to two DATA wires in the dual-wire serial peripheral interface, unlike DATA0 and DATA1 in the wiegand interface, and hereinafter, the two DATA wires DATA0 and DATA1 in the dual-wire serial peripheral interface will be simply referred to as D0 and D1 for ease of understanding.

DMA-DMA (Direct Memory Access ), a direct memory access transfer copies data from one address space to another address space, providing high speed data transfer between a two-wire serial peripheral interface and memory or between memory and memory. When the processor initiates this transfer action, the transfer action itself is implemented and completed by the direct memory access controller. The direct memory access transmission mode does not need a processor to directly control transmission, does not need to interrupt the processing mode to reserve the site and recover the site process, and opens up a direct data transmission channel for RAM (Random Access Memory ) and IO (Input/Output) equipment through hardware, so that the efficiency of the processor is greatly improved.

DMA buffer (direct memory access buffer) is a section of memory space allocated for direct memory access before starting the direct memory access, and is used for buffering data transmitted by the direct memory access.

SOC (System On Chip), also known as System On a Chip, means that it is a product, which is an integrated circuit with a dedicated target, containing the complete System and the entire contents of embedded software.

CPU (Central Processing Unit, CPU) is used as the operation and control core of computer system and is the final execution unit for information processing and program running.

MCU (Microcontroller Unit, microcontroller or micro control unit) is an integrated circuit chip, it adopts very large scale integrated circuit technology, integrate the Central Processing Unit (CPU) frequency of the computer and basic IO (input/output) interface circuit on the same chip. The microcontroller is generally used as a core control component of an embedded system and is widely applied to modern intelligent electronic equipment such as intelligent instruments, real-time industrial control, communication equipment, navigation systems, household appliances and the like.

Signal in the present application means a high-low level signal.

Data in the present application, the high and low level signals are converted into the form represented by digital signals 0 and 1, which are referred to as data.

Information in the present application, the information is a specific meaning represented by a binary code composed of the index signals 0 and 1, for example, related information such as an access card (e.g., card number, user information of the access card, etc.) can be converted into binary code data by a coding technique. The content carried by these binary coded data is information.

Sampling, namely, a process of collecting signals and converting the collected signals into DATA, referring to fig. 5, two lines shown in fig. 5 are a signal collected by a DATA0 signal line and a DATA1 signal line, sampling is carried out at a time 3, a low level on the DATA0 is represented as 1, a low level on the DATA A1 is represented as 0, sampling is carried out at a time 4, a low level on the DATA0 is represented as 0, a low level on the DATA A1 is represented as 1, and sampling is carried out to obtain DATA 0.

In the existing access control system, the access control system receives initial wiegand signals from a card reader through DATA0 and DATA1 signal lines and transmits the initial wiegand signals to an external differential amplification circuit for differential processing. And then, the signals subjected to differential processing enter an external signal modulation circuit for modulation so as to adapt to transmission requirements. Finally, the system receives and analyzes the modulated wiegand signal through a serial peripheral interface or other communication protocols, restores the original data, and verifies whether the original data meets the requirement of access control authority.

However, this processing technique has some problems. Firstly, the differential amplifying circuit and the signal modulation circuit are used as external parts, so that the implementation cost and complexity of the access control system are increased, and meanwhile, the implementation difficulty of the scheme is increased. And the processor of the access control system not only needs to directly participate in the whole process of receiving and processing the wiegand data, but also needs to consider other system tasks, so that the burden of the processor is increased, and the data processing efficiency is reduced. Secondly, because the technology needs to preset the wiegand format before implementation, the technology cannot be compatible with a plurality of different wiegand formats, and the flexibility and expansibility of the system are limited.

Based on this, the present application provides a receiving apparatus that solves the above-mentioned technical problems by the characteristics of a serial interface having two pins, and for more clear explanation of the present application, the principle of a serial interface having two pins will be explained first:

The serial interface with two pins may be a two-wire serial peripheral interface, or may be other interfaces that are characteristic of other serial interfaces with two pins. Since a serial interface having two pins typically uses 8 bits or more to represent one byte of data, pins herein are IO pins, i.e., input/output pins, and thus, for convenience of description herein, a wiegand data transmission manner is described by way of example in fig. 1, in which a serial interface having two pins is a two-wire serial peripheral interface, pins are input/output pins, and each of the two-wire serial peripheral interfaces uses 8 bits to represent one byte of data.

As mentioned above, the dual-line serial peripheral interface samples wiegand data through two input/output pins, that is, data 0 and 1 are respectively transmitted through two data lines D0 and D1, a buffer space is provided in the dual-line serial peripheral interface, the transmitted wiegand data is 8-bit data, 8 spaces are provided in the corresponding buffer space, the numbers of the 0 th to 7 th spaces are 0-7 in sequence, and each space can store one bit of data. Data of consecutive 8 bits is dispersed on two data lines of D0 and D1 in the order shown in fig. 6. After receiving wiegand data, the two-wire serial peripheral device interface stores data input by the way of D0 in the positions numbered 0,2,4 and 6 in the buffer space, and stores data input by the way of D1 in the positions numbered 1,3,5 and 7. After the data in the cache space of the two-wire serial peripheral device interface is accessed and carried to the memory by the direct memory, the storage mode in the memory is the same as the storage mode in the cache space of the two-wire serial peripheral device interface, and the data are read from the memory by the processor according to the sequence of 0-7, so that the two paths of input are finally read once, and the combined data are obtained.

When the dual-wire serial peripheral interface performs wiegand data transmission, the two input/output pins include a first input/output pin D0 and a second input/output pin D1, and the two input/output pins coexist in three possible situations, namely, the wiegand data 1 is transmitted, the wiegand data 0 is transmitted and no valid data is transmitted, see fig. 7a, and fig. 7a is a schematic diagram of a wiegand data transmission flat state provided by an embodiment of the present application.

Specifically, when the wiegand data is a wiegand idle signal, that is, no valid data is transmitted, referring to fig. 7b, the D0 level is high, the D1 level is high, the data 1 obtained by sampling the first pin, that is, the data 1 obtained by sampling the D0 pin is recorded as first unit data, the data 1 obtained by sampling the second pin, that is, the data 1 obtained by sampling the D1 pin is recorded as second unit data, the data obtained by combining the first unit data and the second unit data is recorded as 11, and the data transmission lasts for a period of time, so that the data obtained by continuously collecting the data is recorded as repeated 0xFF (the binary data is 1111 1111), and the data in the form is recorded as first combined data.

When wiegand data 0 is transmitted, referring to fig. 7c, D0 level is low level, D1 level is high level, data 1 obtained by sampling the first pin, that is, data 1 obtained by sampling the D0 pin is denoted as third unit data, data 0 obtained by sampling the second pin, that is, data 0 obtained by sampling the D1 pin is denoted as fourth unit data, data obtained by combining the third unit data and the fourth unit data is denoted as 10, and based on the same principle as that of the transmission without effective data, the data obtained by continuously collecting the data is denoted as repeated 0xAA (the binary data is 1010 1010), and the data in the form is denoted as second combined data.

When wiegand data 1 is transmitted, referring to fig. 7D, D0 level is high level, D1 level is low level, data 0 obtained by sampling the first pin, that is, data 0 obtained by sampling the D0 pin is denoted as fifth unit data, data 1 obtained by sampling the second pin, that is, data 1 obtained by sampling the D1 pin is denoted as sixth unit data, data obtained by combining the fifth unit data and the sixth unit data is denoted as 01, and based on the same principle as that of the transmission without effective data, the data obtained by continuously collecting "01" is obtained, and thus the data obtained by combining them is denoted as repeated 0x55 (the binary data is 0101 0101), and the data in this form is denoted as third combined data.

It will be appreciated that the unit data transmitted over the two data lines of D0 and D1 should be combined in the same order, and that exemplary, when no valid data is transmitted, the first combined data 1111 1111 is combined in the order of D0-D1-D0-D1-D0-D1, the second combined data 1010 1010 is combined in the order of D0-D1-D0-D1-D0-D1 is transmitted when Wiegand data 0 is transmitted, and the third combined data 0101 0101 is combined in the order of D0-D1-D0-D1-D0-D1-D0-D1 when Wiegand data 1 is transmitted.

Referring to fig. 8, fig. 8 is a schematic diagram of a receiving device according to an embodiment of the present application, including a processor 801, a two-wire serial peripheral interface 802, two input/output pins 803 and 804, a memory 805, and a common ground pin 806;

A two-wire serial peripheral interface 802 for periodically sampling the two input/output pins 803 and 804 and storing the sampled data in a memory 805 by direct memory access;

The processor 801 is configured to read data stored in the memory 805 through direct memory access as first data in response to completion of reception of wiegand data, divide the first data into a plurality of sub-data by using first combined data as a separator, respectively determine first wiegand data corresponding to each sub-data, and combine each first wiegand data to obtain second data, analyze the second data according to a preset wiegand protocol, and obtain first information;

The ordering of each first wiegand data in the second data is the same as the ordering of the corresponding sub data in the first data, the sub data of the repeated occurrence second combined data corresponds to wiegand data 0, and the sub data of the repeated occurrence third combined data corresponds to wiegand data 1; the first combined data, the second combined data and the third combined data are data obtained by sampling two input and output pins under different conditions, and when the first combined data are that the two input and output pins receive a wiegand idle signal, the second combined data are that the two input and output pins 803 and 804 receive wiegand data 0, and the third combined data are that the two input and output pins 803 and 804 receive wiegand data 1.

For example, assuming that the first data is 0xAA 0xFF 0x55 0xFF 0x55 0xFF 0x55 0xFF 0xAA 0xFF 0x55 0xFF 0xAA 0xFF 0x55 0xFF, the first data starts with the second combined data 0xAA, then the first bit is collected and the combined second data is 0xAA 0x55 0x55 0x55 0xAA 0x55 0xAA 0x55, i.e., 01110101.

Assuming that the first data is 0xFF 0xAA 0xFF 0x55 0xFF 0x55 0xFF 0xAA 0xFF 0x55 0xFF 0xAA 0xFF 0xAA 0xFF, the first data starts with the second combined data 0xFF, then the first bit is not collected, assuming that the second wiegand data is 0xAA, and the combined second data is 0xAA 0xAA 0x55 0x55 0x55 0xAA 0x55 0xAA 0x55, i.e., 00110100.

By applying the embodiment, the receiving device receives the wiegand data through the two-wire serial peripheral device interface, high-speed sampling is realized, data processing efficiency is remarkably improved, and data storage is realized by utilizing a direct memory access technology, so that the burden of a processor is greatly reduced. More importantly, the method can realize the receiving and processing of the wiegand data without modifying or adding an external circuit to hardware equipment, and reduces the cost and complexity of the receiving and processing of the wiegand data. In addition, the receiving device has excellent compatibility, can receive and analyze wiegand data in various formats, accurately extracts information according to a wiegand protocol, and greatly improves flexibility and expansibility of wiegand data reception.

The receiving device provided by the application will be exemplarily described in the whole flow of wiegand data receiving processing:

referring to fig. 9, fig. 9 is a flowchart of a wiegand data receiving process according to an embodiment of the present application, including:

S901, setting a receiving trigger interrupt;

s9021, other threads execute normally;

s9022, receiving a trigger interrupt trigger;

S903, recording a trigger signal;

s904, starting a two-wire serial peripheral interface;

S905, starting direct memory access;

S9061, direct memory access acquisition;

S9062, triggering the completion of the interrupt of the direct memory access;

S9063, other threads execute normally;

s9064, judging whether the receiving is completed, if yes, executing S907, and if not, executing S9063;

S907, judging whether the first bit (i.e. the first bit) is collected, if so, executing S909, if not, executing S908;

s908, reading the recorded trigger signal to identify the first bit data;

s909, determining whether the data length is 26, if so, executing S9010, and if not, executing S9011;

S9010, analyzing wiegand 26 data;

S9011, judging whether the data length is 34, if so, executing S9012, and if not, executing S9013;

s9012, analyzing wiegand 34 data;

s9013, judging whether the data length is other length, if so, executing S9014;

s9014, analyzing other length data of the wiegand.

The above steps S901 to S9014 will be described below in conjunction with the receiving apparatus:

In S901, since the sender of wiegand data can initiate data transmission at any time, if the receiving device is in a receiving state continuously, the occupancy rate of the processor will be increased, so as to affect the performance of the receiving device, based on which the occupancy rate of the processor can be reduced by triggering an interrupt by the device receiving, so as to improve the efficiency and reliability of wiegand data transmission.

Before the interrupt is triggered, the processor is used for periodically sampling the two input and output pins, analyzing the sampled data through a preset serial protocol, and obtaining second information. The second information is usually information that is not transmitted in the form of wiegand data, and is used to monitor the status of two input/output pins.

When a first level signal is sampled from either input-output pin, an interrupt is triggered. The first level signal is a level signal other than the second level signal, the second level signal is a level signal on two input and output pins under the condition that the wiegand idle signal is received, namely, the first level signal is a low level signal, and the second level signal is a high level signal.

By applying the embodiment, the processor periodically samples the two input and output pins, so that the real-time performance of non-wiegand data acquisition is ensured, when a specific first level signal is detected, a direct memory access (namely DMA) mechanism can be immediately triggered, and the direct transmission of data from a two-wire serial peripheral interface to a memory is realized through a DMA technology, so that the participation and interruption times of a CPU are reduced, the load of the CPU is reduced, and the overall performance of receiving equipment is improved. In addition, the total length of DMA transmission is configured to be larger than a preset length threshold, so that the integrity and continuity of data transmission are ensured, the stability and reliability of the system are further improved, and further, rapid data transmission and storage are realized, and the response speed and the data processing efficiency of the receiving equipment are improved.

Setting the reception trigger interrupt may be achieved by:

The dual-wire serial peripheral interface comprises a chip select pin, the level of the chip select pin of the dual-wire serial peripheral interface is kept at a first level when the processor receives non-wiegand data, and the level of the chip select pin is adjusted to a second level when the processor receives wiegand data. Wherein the first level is one of a high level and a low level, and the second level is the other of the high level and the low level.

The process of adjusting the level of the chip select pin to the second level is a process of sending an acquisition instruction to the two-wire serial peripheral interface, so that the two-wire serial peripheral interface performs the step of sampling the two input/output pins.

By applying the above embodiment, the processor may be enabled to receive non-wiegand data by the processor maintaining the chip select pin level at the first level. When the data acquisition of the wiegand is needed, the processor sends an acquisition instruction by adjusting the chip selection pin to the second level, so that the flexibility and the response speed of the equipment are improved, and the accuracy and the reliability of the data acquisition are ensured. In addition, the design of the chip select pins also reduces the complexity of the device design, reduces the additional hardware and software overhead, and further reduces the cost.

In S9021, the other threads execute normally, i.e. the processor performs other tasks than receiving and processing wiegand data, e.g. periodically checking whether reception of wiegand data has been completed based on data stored in the memory, as described in detail in S9063 below;

In S9022, the processor executes step S903, step S904, and step S905 in response to the interrupt being triggered.

In response to the interrupt being triggered, the processor records the trigger signal in the memory, i.e., records the input/output pin sampled to the first level signal, and takes it as the target input/output pin, and records the wiegand data corresponding to the target input/output pin as the second wiegand data.

In S904, in response to the interrupt being triggered, the processor turns on the two-wire serial peripheral interface, i.e., the set register turns on the two-wire serial peripheral interface acquisition. The two-wire serial peripheral interface periodically samples the two input-output pins after being turned on.

In S905, in response to the interrupt being triggered, the processor opens the direct memory access, i.e. the processor enables the direct memory access, and after opening the direct memory access, step S9061 is performed.

In S9061, after sampling two input/output pins through the two-wire serial peripheral interface, the sampled data is stored in the memory by direct memory access.

S9062, direct memory access completion interrupt triggering, namely after the completion of the reception of wiegand data, stopping direct memory access by a processor, or stopping direct memory access control by itself, wherein the specific mode of stopping direct memory access control by itself is as follows:

In the wiegand data transmission process, the direct memory access sets the source address, the destination address, the total transmission length, whether to start the completion interrupt and the like of the transmission before starting, and the direct memory access automatically stops when the total transmission length is completed and generates a completion interrupt. The total transmission length may be calculated according to the length of wiegand data received by the receiving device, and, for example, assuming that the wiegand protocol to be received supports wiegand 58 at the longest, i.e., the wiegand data length is 58, the total transmission length is 58× (20 ms) ×1MB/1000 ms=1.16 MB. Where 20ms is the maximum value of the bit interval time of the wiegand data. In practical application, a larger value can be taken on the basis of the above, and the specific limitation is not given here.

In S9063, after the interrupt is triggered and the processor opens the direct memory access, the processor periodically reads the data recorded in the memory in the last cycle as the third data, and then performs step S9064.

In S9064, in order to reduce the burden of the processor, improve the accuracy and reliability of the wiegand data reception, and ensure the integrity of the wiegand data, the processor may determine whether the wiegand data reception is completed by periodically checking the data stored in the memory, and specifically, if the third data read by the processor is the first combined data that repeatedly appears, it is determined that the wiegand data reception is completed. Wherein the period of the data recorded by the processor reading memory in the last period is greater than the Wiegand data maximum bit interval time.

It can be understood that, in the wiegand data transmission process, the interval time between two bits in the same wiegand transmission is fixed, namely, the bit interval time, and if the received data is a wiegand idle signal in a time longer than the bit interval time, the wiegand data is proved to be received.

After the wiegand data is received, step S907 is executed, and if not, step S9063 is executed, in which the wiegand data is continuously collected, and the processor periodically reads the data recorded in the memory in the last period.

In S907, the two-wire serial peripheral interface does not sample both input-output pins until the interrupt is triggered. The two input-output pins will be sampled by the two-wire serial peripheral interface only after the interrupt is triggered, so the wiegand data transmitted through the two input-output pins cannot be collected until the interrupt is triggered. In addition, the dual-wire serial peripheral interface does not have the function of directly writing wiegand data into the memory, and only after direct memory access is enabled can wiegand data be written into the memory. Therefore, even if the dual-wire serial peripheral interface can collect wiegand data before enabling direct memory access, the collected data cannot be written into the memory, so that the condition that the first bit is not collected by the direct memory access exists. And because the wiegand data lengths of different formats are also different, the received accurate data length needs to be known during analysis so as to analyze according to the correct wiegand format. In order to be compatible with different wiegand formats, flexibility and expansibility of wiegand data receiving are improved, accuracy of wiegand data processing is improved, whether a first bit is collected or not can be judged after the wiegand data receiving is completed, and the implementation can be specifically realized by judging whether first data starts with first combined data 0xFF (namely invalid data):

If the first data is not started with the first combined data 0xFF, i.e. the first data is started with the second combined data 0xAA or the third combined data 0x55, the first bit is verified to be collected. In this case, when the processor combines the first wiegand data to obtain the second data, the processor sequentially arranges the first wiegand data in order of the first data to obtain the second data. The ordering of the first wiegand data in the second data is the same as the ordering of the first wiegand data in the first data.

If the first data starts with the first combined data 0xFF, it is proved that the first bit is not collected, and when the processor combines the first wiegand data to obtain the second data, the processor sequentially arranges the first wiegand data in the second wiegand data according to the ordering in the first data to obtain the second data, which is step S908.

By applying the embodiment, the processor can accurately identify and record the input/output pins receiving the first level signal by monitoring the level signal change on the input/output pins in real time, so that the target input/output pins, namely the corresponding wiegand data (0 or 1), are rapidly determined, the design effectively avoids data loss or misjudgment, and the integrity and accuracy of data acquisition are ensured. Further, the processor can intelligently identify the initial combination mode of the first data, and select a correct data processing mode according to the mode, so that not only is the correct combination of the data ensured, but also the speed and the efficiency of data processing are improved, and the flexible data processing mode enables the access control system to adapt to different data formats and transmission requirements, and improves the compatibility and the expandability of the system.

In S909-S9014, the processor selects a corresponding wiegand format to parse the second data according to the length of the second data.

Corresponding to the above-described receiving apparatus, the embodiment of the present application also provides a transmission system, see fig. 10, which includes a transmitting apparatus 100, and the above-described receiving apparatus 101;

The transmitting device 100 includes a processor 1001, two input-output pins 1002,1003, and a common ground pin 1004;

A receiving device 101 comprising a processor 801, a two-wire serial peripheral interface 802, two input-output pins 803,804, a memory 805, and a common ground pin 806;

A processor 1001 of the transmitting device 100 for acquiring the first message and encapsulating the first message into wiegand data, transmitting the wiegand data to the receiving device 101 via two input output pins 1002,1003 of the transmitting device 100;

a two-wire serial peripheral interface 802 for periodically sampling two input/output pins 803,804 of the receiving device 101 and storing the sampled data in a memory 805 by direct memory access;

The processor 801 of the receiving device 101 is configured to read data stored in the memory 805 through direct memory access as first data in response to completion of reception of wiegand data, partition the first data into a plurality of sub-data by using the first combined data as a separator, respectively determine first wiegand data corresponding to each sub-data, and combine each first wiegand data to obtain second data;

The ordering of the first wiegand data in the second data is the same as the ordering of the corresponding sub-data in the first data, the sub-data where the second combined data repeatedly appears corresponds to wiegand data 0, the sub-data where the third combined data repeatedly appears corresponds to wiegand data 1, the first combined data, the second combined data and the third combined data are data obtained by sampling the two input output pins 803,804 of the receiving device 101 under different conditions, and the first combined data are data obtained by sampling the two input output pins 803,804 of the receiving device 101 when the two input output pins 803,804 of the receiving device 101 receive wiegand idle signals, the second combined data are data obtained by sampling the wiegand data 0 when the two input output pins 803,804 of the receiving device 101 receive wiegand data 1.

By applying the embodiment, the transmission system acquires the first message through the sending equipment, encapsulates the first message into the wiegand data and sends the wiegand data to the receiving equipment, and the receiving equipment receives the wiegand data through the two-wire serial peripheral equipment interface, so that high-speed sampling is realized, the data processing efficiency is remarkably improved, and the data storage is realized by utilizing the direct memory access technology, so that the burden of a processor is greatly reduced. More importantly, the wiegand data can be received and processed without modifying hardware equipment or adding an external circuit, so that the cost and complexity of a transmission system are reduced. In addition, the transmission system has excellent compatibility, can receive and analyze wiegand data in various formats, accurately extracts information according to a wiegand protocol, and greatly improves flexibility and expansibility of the transmission system.

For the above-mentioned each processor, the detailed description of the steps performed by the dual-wire serial peripheral device interface may be referred to the above description of the steps performed by the dual-wire serial peripheral device interface for the processor in the receiving device, which is not repeated herein.

In one possible embodiment, the transmitting device may comprise a system on a chip (i.e., SOC) and the receiving device may comprise a microcontroller (i.e., MCU), but in practical applications the receiving device may also need to handle some complex traffic, such as web services, displays, cameras, etc.

Based on this, in order to enable the receiving device to easily cope with complex traffic scenarios, to improve the resource utilization of the overall transmission system, as well as the efficiency and reliability of data transmission, in another possible embodiment, referring to fig. 11, the transmitting device may comprise a microcontroller (i.e., MCU) that may comprise a system-on-chip (i.e., SOC) comprising a processor 1001, two input-output pins 1002,1003, and a common ground pin 1004, the system-on-chip comprising a processor 801, a two-wire serial peripheral interface 802, two input-output pins 803,804, a memory 805, and a common ground pin 806.

The transmission system provided in the embodiment of the application can be applied to a plurality of scenes, such as an access control system, a parking management system, an elevator control system and the like, and the transmission system is only used in the access control system for illustration.

Referring to fig. 12, fig. 12 is a schematic structural diagram of an access control system provided in an embodiment of the present application, including a card reading device 120, a control device 121, and an access control device 122;

Card reader device 120 includes a processor 1201, two input-output pins 1202,1203, and a common ground pin 1204;

the control device 121 includes a processor 1211, a two-wire serial peripheral interface 1212, two input-output pins 1213,1214, a memory 1215, and a common ground pin 1216.

The following will describe the above-mentioned access control system in detail with reference to fig. 13 in combination with the complete flow of authentication in the access control system, and fig. 13 is a flowchart of authentication of the access control system according to an embodiment of the present application, including step S130 executed by the card reader 120, step S131 executed by the control device 121, and step S132 executed by the access control device 122;

wherein, step S130 includes:

S1301, the user swipes a card;

s1302, card reading, namely, the processor 1201 of the card reading equipment 120 responds to card reading operation, acquires access control card information of an access control card triggering the card reading operation, and encapsulates the access control card information into Wiegand data;

S1303, the processor 1201 of the card reader device 120 sends wiegand data to the control device 121 through two input/output pins 1202,1203 of the card reader device.

Step S131 includes:

S1311, receiving wiegand data, that is, periodically sampling two input/output pins 1213,1214 of the control device 121 by the two-wire serial peripheral interface 1212 of the control device 121, and storing the sampled data in the memory 1215 through direct memory access;

S1312, analyzing the wiegand data, namely, the processor 1211 of the control equipment 121 reads the data stored in the memory through direct memory access in response to the completion of the reception of the wiegand data as first data, taking the first combined data as a separator to separate the first data into a plurality of sub-data, respectively determining the first wiegand data corresponding to each sub-data, combining the first wiegand data to obtain second data, analyzing the second data according to a preset wiegand protocol, and obtaining access card information;

S1313, it is verified whether the card information passes, that is, the processor 1211 of the control device 121 authenticates the access card information, and if the authentication passes, a pass instruction is sent to the access device 122. In order to provide timely feedback for the user, long-time waiting and uncertainty are avoided, so that user experience is improved, authentication success can be displayed in a screen of the access control system under the condition that authentication is passed, namely, step S1314, and authentication failure is displayed in the screen of the access control system under the condition that authentication is not passed, namely, step S1315;

Step S132 includes:

S1321, opening the door, namely under the condition that authentication passes, the door access device responds to the pass instruction and enters a state allowing pass, and in the case that the door access device is a gate, the gate opens a gate wing to allow a user to pass after responding to the pass instruction, and in the case that the door access device is a revolving door, the revolving door automatically rotates at a corresponding speed according to the moving direction of the user after responding to the pass instruction, so that the user can pass.

The ordering of each first wiegand data in the second data is the same as the ordering of the corresponding sub data in the first data, the sub data of the repeated occurrence second combined data corresponds to wiegand data 0, and the sub data of the repeated occurrence third combined data corresponds to wiegand data 1; the method comprises the steps that under the condition that first combined data, second combined data and third combined data are data obtained by sampling two input and output pins of control equipment under different conditions, the first combined data are the condition that the two input and output pins of the control equipment receive wiegand idle signals, the second combined data are the condition that the two input and output pins of the control equipment receive wiegand data 0, and the third combined data are the condition that the two input and output pins of the control equipment receive wiegand data 1.

In order to more clearly describe the authentication flow in the access control system provided by the application, the following will take an access control card number as a 32-bit binary number (taking a wiegand 34 format as an example) as an example for description:

Assume that the user has an access card, access card number 10101010 11110000 10101010 11110000 (for example only). After the user swipes the card, the card reader device obtains the access card information, encapsulates the access card information into Wiegand data, 10101010 11110000 10101010 11110000 (in this example, focus on the transmission of Wiegand data, and therefore, for convenience of description, no specific check bit calculation is involved), and represents the Wiegand data by the second combination data and the third combination data, wherein the Wiegand data is ：0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0x55 0x55 0x55 0xAA 0xAA 0xAA 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0x55 0x55 0x55 0xAA 0xAA 0xAA 0xAA;

After the wiegand data is obtained, the card reading device sends the wiegand data to the control device, and the control device stores the wiegand data through the memory after receiving the wiegand data. The control device analyzes the wiegand data, namely, the processor of the control device reads the data stored in the memory, and if the first data is 0x55 0xFF 0xAA 0xFF 0x55 0xFF 0xAA 0xFF 0x55 0xFF 0xAA 0xFF 0x55 0xFF 0xAA 0xFF 0x55 0xFF 0x55 0xFF 0x55 0xFF 0x55 0xFF 0xAA 0xFF 0xAA 0xFF 0xAA 0xFF 0xAA 0xFF 0x55 0xFF 0xAA 0xFF 0x55 0xFF 0xAA 0xFF 0x55 0xFF 0xAA 0xFF 0x55 0xFF 0xAA 0xFF 0x55 0xFF 0x55 0xFF 0x55 0xFF 0x55 0xFF 0xAA 0xFF 0xAA 0xFF 0xAA 0xFF 0xAA 0xFF; and the first data starts with the third combined data 0x55, the first bit is collected, so that the second data obtained by combining is ：0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0x55 0x55 0x55 0xAA 0xAA 0xAA 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0x55 0x55 0x55 0xAA 0xAA 0xAA 0xAA,, the obtained access card number is 10101010 11110000 10101010 11110000, the access card number is verified, and if the authentication is passed, a passing instruction is sent to the access device, and the user is allowed to pass.

By using the access control system, the access control system adopts the wiegand data as the transmission format of the access control card information, encapsulates the access control card information into the wiegand data through the processor of the card reading equipment, and sends the wiegand data to the control equipment through the input/output pins. The data format has high safety and stability, can ensure accurate transmission of the information of the access card, and effectively prevents information leakage and tampering. And secondly, the control equipment periodically samples the input and output pins through a two-wire serial peripheral interface, and stores the sampled data in a memory through direct memory access. The sampling and storing mode not only improves the efficiency and stability of data transmission, but also reduces the workload of a processor, so that the access control system can respond to card reading operation more quickly. The Wiegand data can be received and processed by the access control system without modifying hardware equipment or adding an external circuit, the cost and complexity of the access control system for receiving and processing the Wiegand data are reduced, furthermore, the access control system has excellent compatibility, can receive and analyze Wiegand data in various formats, accurately extracts information according to Wiegand protocols, and greatly improves the flexibility and expansibility of the access control system.

In one possible embodiment, the card reader device 120 may comprise a system on a chip (i.e., SOC), and the control device 121 may comprise a microcontroller (i.e., MCU), but in practical applications, the control device 121 may also need to handle some complex traffic, such as web services, displays, cameras, etc.

Based on this, in order to enable the access control system to easily cope with complex business scenarios, to improve the resource utilization of the entire access control system, and the efficiency and reliability of data transmission in the access control system, in another possible embodiment, the card reading device 120 may include a microcontroller (i.e., MCU), the control device 121 may include a system-in-chip (i.e., SOC) including a processor and two input-output pins, and the system-in-chip includes a processor, a two-wire serial peripheral interface, two input-output pins, and a memory.

In one possible embodiment, since the control device includes a system on a chip (i.e., SOC) that has a powerful processing capability, the control device itself may also be integrated as a card reading device, based on which the processor 1211 of the control device 121 is further configured to obtain access card information of an access card that triggers the card reading operation in response to the card reading operation, package the access card information into wiegand data, and send the wiegand data to other control devices through two input/output pins of the control device.

By applying the embodiment, the card reading function can be integrated into the control equipment based on the performance of the system-in-chip, so that the number of components of the access control system is reduced, the integration level of the access control system is improved, the structure and wiring of the access control system are simplified, and the maintenance cost of the access control system is reduced.

Corresponding to the foregoing receiving device, the embodiment of the present application further provides a receiving method, referring to fig. 14, and fig. 14 is a flowchart of the receiving method provided by the embodiment of the present application, including:

S1401, periodically sampling the two pins through a serial interface with the two pins, and storing the sampled data in a memory through direct memory access;

s1402, in response to completion of the reception of the wiegand data, reading the data stored in the memory through direct memory access as first data;

s1403, dividing the first data into a plurality of sub-data composed of the second combined data and/or the third combined data by taking the first combined data as a separator;

S1404, respectively determining first wiegand data corresponding to each piece of sub data, and combining the first wiegand data to obtain second data;

S1405, analyzing the second data according to a preset Wiegand protocol to obtain first information.

The method comprises the steps that the ordering of first wiegand data in second data is the same as the ordering of corresponding sub-data in the first data, first combined data are combinations formed by first unit data and second unit data, the first unit data are data obtained by sampling a first pin when two pins receive wiegand idle signals, and the second unit data are data obtained by sampling a second pin when the two pins receive wiegand idle signals; the second combined data is a combination formed by third unit data and fourth unit data, wherein the third unit data is data obtained by sampling a first pin when two pins receive Wiegand data 0, the fourth unit data is data obtained by sampling a second pin when two pins receive Wiegand data 0, the third combined data is a combination formed by fifth unit data and sixth unit data, the fifth unit data is data obtained by sampling a first pin when two pins receive Wiegand data 1, and the sixth unit data is data obtained by sampling a second pin when two pins receive Wiegand data 1.

By adopting the embodiment, the wiegand data is received through the serial interface with two pins, so that high-speed sampling is realized, the data processing efficiency is remarkably improved, and the data storage is realized by utilizing the direct memory access technology, thereby greatly reducing the burden of a processor. More importantly, the method can realize the receiving and processing of the wiegand data without modifying or adding an external circuit to hardware equipment, and reduces the cost and complexity of the receiving and processing of the wiegand data. In addition, the receiving device has excellent compatibility, can receive and analyze wiegand data in various formats, accurately extracts information according to a wiegand protocol, and greatly improves flexibility and expansibility of wiegand data reception.

The steps S1401-S1405 are similar to the steps performed by the receiving apparatus, and the description of the steps performed by the receiving apparatus may be referred to herein, and will not be repeated.

Corresponding to the above receiving method, the embodiment of the present application further provides a receiving apparatus, referring to fig. 15, and fig. 15 is a schematic structural diagram of the receiving apparatus provided in the embodiment of the present application, including:

A sampling module 1501, configured to periodically sample the two pins through the serial interface having the two pins, and store the sampled data in the memory through direct memory access;

A reading module 1502, configured to read, by using the processor, data stored in the memory through direct memory access as first data in response to completing reception of wiegand data;

A separation module 1503, configured to separate, by the processor, the first data into a plurality of sub-data composed of the second combined data and/or the third combined data, with the first combined data as a separator;

a combination module 1504, configured to determine first wiegand data corresponding to each piece of sub-data respectively through the processor, and combine each piece of first wiegand data to obtain second data;

the parsing module 1505 is configured to parse the second data according to a preset wiegand protocol by using the processor, so as to obtain first information.

In one possible embodiment, the apparatus further comprises:

the acquisition module is used for periodically sampling the two pins, analyzing the sampled data through a preset serial protocol, and obtaining second information until any pin is sampled to a first level signal;

An enabling module, configured to enable the direct memory access and send an acquisition instruction to the serial interface with two pins in response to sampling the first level signal from any one of the pins;

the storage module is used for responding to the acquisition instruction, periodically sampling the two pins through the serial interface with the two pins, and storing the sampled data in the memory through the direct memory access;

In one possible embodiment, the apparatus further comprises:

a holding module for holding the level of the chip select pin at a first level, wherein, the chip selection pins are arranged on the serial interface with the two pins;

The enabling module comprises:

the enabling first sub-module is used for adjusting the level of the chip select pin to a second level;

In one possible embodiment, the apparatus further comprises:

a recording module for recording, in response to sampling the first level signal from any one of the pins, the pin sampled to the first level signal in the memory as a target pin;

the reading module is used for reading the recorded target pin and determining second wiegand data corresponding to the target pin if the first data starts with the first combined data;

The combination module comprises:

a first sub-module is configured to, if the first data starts with the first combined data, sequentially arrange the first wiegand data corresponding to each sub-data in the second wiegand data according to the ordering in the first data, and then obtain second data;

A second sub-module is configured to, if the first data does not start with the first combined data, sequentially arrange the first wiegand data corresponding to each sub-data according to the ordering in the first data, so as to obtain second data;

In one possible embodiment, the apparatus further comprises:

the system comprises a memory, a confirmation module, a receiving module and a receiving module, wherein the memory is used for storing data recorded in the memory in the last period and used for storing the data in the memory, and the confirmation module is used for periodically reading the data recorded in the last period of the memory as third data;

In the technical scheme of the application, related operations such as acquisition, storage, use, processing, transmission, provision, disclosure and the like of the personal information of the user are performed under the condition that the authorization of the user is obtained.

Claims

1. The access control system is characterized by comprising card reading equipment, control equipment and access control equipment;

The card reading device comprises a processor and two pins;

the access control equipment is used for responding to the passing instruction and entering an allowed passing state;

2. The access control system of claim 1, wherein the card reading device is a microcontroller comprising a processor and two pins;

3. The door access system of claim 1, wherein the door access system comprises a plurality of control devices,

4. A receiving device comprising a processor, a serial interface having two pins, and a memory;

5. The receiving device of claim 4, wherein the receiving device,

The processor is further configured to periodically sample the two pins, and parse the sampled data through a preset serial protocol to obtain second information until a first level signal is sampled from any one of the pins;

6. The receiving device of claim 5, wherein the receiving device,

The serial interface with two pins comprises a chip selection pin;

The processor adjusts the level of the chip select pin to a second level;

7. The receiving device of claim 5, wherein the receiving device,

The processor is further configured to record, in the memory, a pin sampled to the first level signal as a target pin in response to sampling the first level signal from any one of the pins;

the processor combines the first wiegand data to obtain second data, including:

8. The receiving device of claim 4, wherein the receiving device,

The processor is also used for periodically reading the data recorded by the memory in the last period as third data, and if the third data comprises continuously-occurring first combined data, determining that the reception of the wiegand data is finished;

9. A method of reception, the method comprising:

10. The method according to claim 9, wherein the method further comprises:

11. The method according to claim 10, wherein the method further comprises:

adjusting the level of the chip select pin to a second level;

12. The method according to claim 10, wherein the method further comprises:

13. The method according to claim 9, wherein the method further comprises:

14. A receiving device, the device comprising:

The sampling module is used for periodically sampling the two pins through a serial interface with the two pins and storing the sampled data in the memory through direct memory access;

the reading module is used for responding to the completion of the reception of the wiegand data, and utilizing the processor to read the data stored in the memory through direct memory access as first data;

15. A transmission system is characterized by comprising a transmitting device and a receiving device;

The transmitting device comprises a processor and two pins;

16. The system of claim 15, wherein the transmitting device comprises a microcontroller comprising a processor and two pins;