SU1550524A1 - Device for interfacing processor and external unit - Google Patents

Abstract

The invention relates to computing and can be used to build information exchange systems. The aim of the invention is to increase speed. The device contains a control node, a latching node, two multiplexers, two bus drivers, two interrupt signal generators, mode register, feature register, output information register, input information register, current status byte register, encoder, trigger, two OR elements. 2 hp f-ly. 4 il.

Description

The invention relates to computing and can be used to build data exchange systems.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a block diagram of the device; in fig. 2-4 are diagrams of the control unit, the fixation unit, and the mode register.

The device contains the output information bus 1 of the processor, bus 2 Record of the processor, bus 3 Read of the processor, address bus 4 of the processor, input information bus 5 of the processor, input bus 6 Interruption of the processor, register 7 of modes, trigger 8, register 9 of the output information, driver 10 interrupt signal, OR element 11, bus driver 12, bus driver 13, register of 14 signs, consisting of triggers 15, 16 and 17, node 18

control, element OR 19, multiplexer 20, interrupt signal generator 21, encoder 22, multiplexer 23, current status byte register 24, input information register 25, operating mode fixing node 26, external device interrupt bus 27, input information bus 28 external device, bus 29 External device recording, bus 30 Reading external device, address bus 31 external device, bus 32 End of block, bus 33 Direct access permission, bus 34 Direct access request, output information bus 35 external device -keeping, the initial installation bus 36, bus 37 zero potential, the tire 38 of the unit capacity.

FIG. 1 shows the outputs 39-50 of the control unit 18, the input 51 and the outputs 52-55 of the operation-fixing unit 26.

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The control unit 18 comprises FIG. 2) the elements And 56 - 67, the first 68 and the second 69 decoders and the element OR 70,

Node 26 fixing mode of operation contains (Fig. 3) three trigger 71 - 73, six elements OR 74 - 79 and four elements And 80 - 83.

Register 7 modes contains (Fig. 4) three elements And 84 - 86 and three trigger 87-89.

The output information bus 1 of the processor serves to issue control information to the register of 7 modes, as well as to issue a command byte or data to the register 9 of the output information.

Bus 2 Processor Record serves for the processor to issue a write control signal to the mode register 7, output information register 9.

Bus 3 Read processor serves for the processor to issue a read control signal from register 14 of signs, encoder 22, register 24 bytes of the current state, register 25 of input information.

The address bus 4 of the processor serves for issuing by the processor the addresses of the addressable memory elements: register 7 modes, register 9 output information, register 14 signs, encoder 22, register 24 bytes of the current state, register 25 of the input information. The input information bus 5 of the processor is used to transmit to the processor the values of the register of 14 attributes, the encoder 22, the register 24 bytes of the current state, the register 25 of the input information.

The processor interrupt input bus 6 is used to issue microprogram interrupt requests to the processor to initiate the read byte procedures of the initial and final states, as well as read or write data bytes.

Register 7 of modes is used to record and store information from a processor representing instructions such as Receive, Chain of Instructions, End of Data Transfer.

The trigger 8 serves to identify the information recorded in the output register 9 as commands.

Output register 9 is used to record and store instructions and data from the processor.

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Interrupt signal generator 10 serves to generate and output an interrupt signal to the processor. The values of the register of 14 signs, the single value of each of which causes the formation of an interrupt signal, arrive at the input of the shaper, the shaper 10 is made on the OR element.

The bus driver 12 serves to control the output of information to the input information bus 5 of the processor. Made on the elements with the third state.

The bus driver 13 serves to control the output of information to the input information bus 28 of an external device. Made on the elements with the third state.

The feature register 14 serves to store and output to the processor features that identify information in the input information register 25 as data or status bytes. A single value of each of the register of 14 signs causes the formation of an interrupt signal to the processor. The register of 14 signs consists of triggers 15-17.

The trigger 15 serves to record and store a status byte flag to identify information stored in the input information register 25 as a status byte. When writing to the register of 14 characters from the external device, the trigger 15 has a separate address, which also records to the trigger 72 in the operation fixing unit 26. The trigger 16 is used to record and store the attribute. Data byte data from the processor is required. When writing to the trigger 16 by the external device, it has a separate address. The trigger 17 serves to store the characteristic Data to identify the information stored in the input information register 25 as data. The trigger 17 is set when writing input data byte from an external device to register 25.

The control unit 18 serves to receive control signals from the processor and an external device and, based on their analysis, to generate device control signals.

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The multiplexer 20 serves to control the output of information to an external device from the register of 7 modes and the trigger 8, or from the register 9 of the output information.

Interrupt signal generator 21 serves to generate the w and output the interrupt signal to an external device. The bits of the register of 7 modes and the trigger 8 are supplied to the input of the imaging unit 21. The imaging unit 21 is executed, for example, on the OR element.

The encoder 22 serves to store the initial status bytes for issuing them to the processor in an initial sample procedure for all instruction codes. Completed, for example, on a ROM, the instruction inputs of which receive instruction codes, and the output bytes of the initial state are read out.

The multiplexer 23 serves to control the output of information to the processor from the encoder 22, the register of 14 signs, the register 24 bytes of the current state or the register 25 of the input information.

A register of 24 bytes of the current state serves to store the state of the external device: Available, Not Available, Zanto.

Input information register 25 is used to record and store data bytes and status bytes from an external device.

The operation-fixing unit 26 serves to control the modes of data exchange with an external device in the direct access mode to the external memory.

The input bus 27 for interrupting an external device is used to issue requests to the external device for a firmware interrupt to initiate procedures for sending a command, exchange data, and complete the operation.

The input information bus 28 of the external device is used to transfer to the external device the values of the register of 7 modes, the trigger 8, and the values of the register 9 of the output information.

Bus 29 Write external device is used to receive from the external device a write control signal in the register of 14 signs, in the register 24 bytes of the current state, in the register 25 of the input information.

Bus 30 Read external device is used to receive from the external device the read control signal of the register of 7 modes, trigger 8, and also register 9 of the output information. The address bus 31 of the external device serves to receive from the internal device the addresses of the addressable memory elements: register 7 modes, trigger 8, register 14 features, register 7 modes, trigger 8, register 14 features, register 24 bytes of the current state, register 25 of the input information .

Spike 32 The end of the block is used to receive from the external device a signal for completing the data exchange procedure in the direct access mode to the external memory.

Bus 33 Direct Forward Access is used for an external device to issue a feedback signal to a signal. A direct access request from the device is used to control the reception or output of data bytes.

Bus 34 A direct access request is used to initiate in an external device a procedure for receiving or issuing a data byte in the direct access mode to the external memory.

The output information bus 35 of the external device serves to output information from the external device to the registers of 14 features, 24 bytes of the current state and 25 input information.

The device works as follows.

Before the start of operation, the signal on the setup bus 36 all the device memory elements are reset. Initiation of device operation is performed both from the processor and from an external device.

The processor can access the record in the mode register 7 and the output information register 9, while the device receives a record byte of information for the processor using the output information bus 1 of the processor, and the address address bus 4 of the processor and bus 2 Processor record is the memory element address and control signal by record. The address of the memory element and the write control signal are fed to the control unit 18, where the control signal is generated.

write to the addressed memory element.

The processor can be accessed in register 14 of the signs, encoder 22, register 24 bytes of the current state and register 25 of the input information, while the device receives the address of the memory element and the signal through the processor’s address bus 4 and the processor 3. read control. The address of the memory element and the read control signal go to the control unit 18, where a read control signal of the addressed memory element is generated. Under the control of this signal, the value of the addressed memory element is read into the input information bus 5 of the processor. The external device can address by writing to the trigger 15 of the register of 14 features 14, the register 24 bytes of the current state, the register 25 of the input information, the trigger 72 of the node 26 fixing the operation mode, and the device receives an information byte for the external device 35 records, and on the address bus 31 of the external device and the bus 29 Recording of the external device are the address and the write control signal. The memory element address and the write control signal are fed to the control unit 18, where a write control signal is generated to the addressed memory element.

An external device can read by read into a register of 7 modes, a trigger 8 and a register 9 of output information, while the address and the read control signal are fed to the device via the address bus 31 of the external device and bus 30 of the external device. The memory element address and the read control signal go to control unit 18, where a read control signal is generated for the addressed memory element. Under the control of this signal, the value of the addressed memory element is read into the input information bus 28 of the external device. The outputs of the register of 7 modes and the trigger 8 are combined into a bus; when they are read, these memory elements have a single address and their meanings are read at the same time.

In the procedures for exchanging data bytes between a device and an external device, their interaction is carried out

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in the mode of direct access to the RAM of the external device. In the mode of data transfer from the processor to the external device, the read byte of data to the input information bus 28 of the external device from the output information register 9 is performed under control of signals on the bus 34 Direct access request, bus 30 Read external device, bus 33 Permission of direct access. In the mode of data transfer from the external device to the processor, the data byte is written from the output information bus 35 of the external device to the input information register 25 under control of signals on the bus 34 Request direct access, bus 29 Write, bus 33 Permission direct access, on bus 32 End of the block.

The device performs part of the control functions of the external device in I / O operations, which consist of the procedures:

-initial sample, which includes receiving a command from the processor and issuing the initial status byte,

-transmit data from the processor to an external device,

-transfer data from an external device to the processor,

-transmit byte state to the processor.

The initial sampling procedure in I / O devices is usually performed as follows.

I / O devices, after receiving the instruction code from the processor, analyze the state of the device, which can be Available, Zanto or Inaccessible. If the status of an I / O device is On or Off, it is issued as the initial byte of the device status; if the device status is Available, the code of the incoming command is analyzed. The instruction code may have values that are acceptable or unacceptable for a given I / O device. If the command code is not acceptable, a byte of initial state is issued to the processor. Device failure. If the command code is acceptable, the initial state byte is defined for each command code, for example: zero, Channel Finished, Channel Finished, external device ended. The execution of the initial sampling procedure according to this algorithm takes quite a long time, especially if the I / O device is a system console and at the time of receipt of a command from the processor, the system control firmware will work on other procedures and the processor interrupt signal for processing the incoming command code cannot be immediately worked out.

In this device, the procedure on

The status byte is from the encoder 22. The crypto rator 22 is a ROM whose address inputs receive a command code. The ROM stores the initial bytes of the state to all codes of existing commands for a given I / O device, as well as the values of Device Failure for all non-pending command codes. These values are read by the processor firmware and taken as the bytes of the initial state. After reading the byte of the initial state of the firmware

the initial sample is performed as follows, - the processor writes to

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in a way. The initiation of the procedure is performed by the processor. Before writing the instruction code, the processor's firmware reads a 24-byte register of the current state and analyzes its value. In the 24 byte register, the current state always stores the state of the external device Available, Occupied, or Not Available, which is recorded by the firmware of the external device 25 and changes when the state of the external device changes. The state of the external device is analyzed by the processor's firmware and, if it is set to Charge or Not available, it is taken as the value of the initial state byte in response to a command, which in this case is not written to the device. If the register value is 24 bytes of the current state Available, then the command code is written to register 9 by trick information, thus setting the trigger 8 and the trigger 15 of the register 14 of the signs. A processor interrupt signal appears on the input bus 6 interrupt processor. On the interrupt signal, the processor reads the value of the register of 14 signs and analyzes its value. A single trigger value 15 of register 14 of the attributes identifies an interrupt signal as a request to transmit a status byte, which may be the initial status byte, the final or asynchronous status byte. The value of the final or asynchronous initial status byte is stored in the input information register 25. The value of the initial status byte to the code of the incoming command is stored in the encoder 22. In the initial sampling procedure, the processor's microprogram reads the value of the initial

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register 7 mode value Reception. On the input bus 27 of the external device interrupt, a firmware interrupt signal appears on the external device, using which the external device firmware reads the values of the mode register 7 and the trigger 8 and analyzes them. A single trigger value 8 identifies information in register 9 of the output information as a command, and the value of Accept register of 7 modes indicates the completion of the byte of the initial state by the process. The firmware of the external device reads the value of the output register where the command is stored. Thus, in devices, the initial sampling procedure is completed at the processor-device level. The external device is only contacted to send a command code to perform the procedures that follow the initial sampling procedure.

Before the external device firmware executes these procedures, the 24 byte register of the current state is written to the value of Zanto, which blocks the device for writing new commands, until the execution of the previous command is completed. After the completion of the command, the register 24 bytes of the current state writes the value Available.

Writing to the 24 byte register of the current state is performed next time. On the output informational width 35 of the external device, the value of the status band of the external device is input to the input of the 24-byte register. The register address is 24 bytes of the current state via the address bus 31 of the external device is fed to the input of the decoder 69 address.

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register 7 mode value Reception. An external device firmware interrupt signal appears on the input bus 27 of the external device, by which the external device firmware reads the values of the mode register 7 and the trigger 8 and analyzes them. A single trigger value 8 identifies the information in output register 9 as a command, and the Receive value of register 7 mode indicates that the processor has finished receiving the initial state byte. The firmware of the external device reads the value of the output register 9, where the command code is stored. Thus, in the device, the initial sampling procedure is completed at the processor-device level. The external device is only accessed to transmit the command code to perform the procedures following the initial sampling procedure.

Before these procedures are executed by the external device firmware, the 24 byte register of the current state is written to the value of Zan that locks the device to write new commands until the previous command is completed. After the command is completed, the value of Available is written to the 24 byte register of the current status.

Writing into the register 24 bytes of the current state is carried out as follows. The output information bus 35 of the external device enters the register 24 bytes of the current state and receives the value of the external device status band. The register address is 24 bytes of the current status via the address bus 31 of the external device to the input of the address address decoder 69 of the control node 18, the output of which is a signal that arrives at the input of the AND element 62. To another input of the AND element 62 via the bus 29 Write external the device receives a write control signal. A signal from the output of the element 62, which from output 49 is fed to the control input of the register 24 bytes of the current state, records the byte of the current state.

When reading the register value of 24 bytes of the current state, the address bus 4 of the processor sends a two-bit register address 24 bytes of the current state to the control input of multiplexer 23, and 3 reads the processor to the control input of the bus driver 12 receives a read control signal. The presence of the address at the input of the multiplexer 23 and the read control signal at the control input of the bus driver 12

It provides information to the input information. The address of the encoder 22 is defined by the processor bus 5 of the register value of 24 bytes of the current state.

When writing a command to a device

over the output data bus 1 Read control signal controls

The processor receives the instruction code at the input of the output information register 9, the address of the instruction write address in the output information register 9 enters the processor address bus 4, and the write control signal via the bus 2 processor write. The address bit and the write control signal go to the control unit 18 at the inputs of the element 59, the output of which forms a signal and enters through the element OR 19 at the input of the record 9 of the output information and at the installation inputs of the triggers 8, 15. At register 9 the output terminal -, the formation is recorded command code,

and the trigger 8, 15 is set to a single value. The unit value of the trigger 8 goes to the first information input of the multiplexer 20, and the command code value from the output information register 9 goes to the second information input of the multiplexer 20 and the encoder input 22, The unit value of the trigger 15 of the register 14 signs goes to the input of the multiplexer 23 and input of the signalizer 10 interrupts. At the output of the interrupt signal generator 10, an interrupt signal appears that

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passing this value through the bus driver 12 to the input information bus 5 of the processor.

When writing the value to the register of 7 modes, the output information bus 1 of the processor inputs the register of the 7 modes and node 18 of the control to the information bit, the address bus 4 of the processor receives the register address of the 7 modes, and the bus 2 writes the processor management record. In control unit 18, the And control unit 58 generates a write control signal and, via the & e 39 bus, enters the input of the register of 7 modes, where the And circuit element 86 generates a recording signal of the value Receive to trigger 89. A single trigger value 89 is fed to the input of the second driver 21 of the interrupt signal and causes the appearance of a signal on the input bus 27 of the external device interrupt. In the control unit 18 on the element AND 56, the signal is normalized, which through the element OR 11 arrives at the reset input of the trigger 15 and resets it.

When reading the values of the register 7 modes and trigger 8 on the address bus

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on the input bus 6 interrupt processor enters the processor.

When reading the value of the trigger 15 of the register of 14 signs on the processor address bus 4 and bus 3 of the processor, the register of the 14 signs and the read control signal are received. The address of the register of signs 14, defined by two bits, is fed to the control input of the multiplexer 23 and controls the passage of the value of register 14 of signs through the multiplexer 23. The read control signal goes to the control input of the bus driver 2 to control the passage of the value of register 14 of signs to the input information bus 5 processor.

When reading the value of the initial status byte of the encoder 22 via the address bus 4 of the processor and bus 3 Read processor receives the address of the encoder 22 and the control signal readable in two bits, is fed to the control input of the multiplexer 23 and controls the passage of the value of the encoder 22 through the multiplexer 23,

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passing this value through the bus driver 12 to the input information bus 5 of the processor.

When writing a value to the register of 7 modes, the output information bus 1 of the processor inputs the register information of the register of the 7 modes and the control node 18, the address of the register of the 7 modes and the bus 2 of the processor write the control signal by record. The control unit 18 on the And 58 element generates a write control signal and enters the register of 7 modes on bus E 39, where on the And 86 element a value record signal is received. Receive in trigger 89. A single value of trigger 89 is fed to the input of the second interrupt signal generator 21 and causes a signal on the input bus 27 to interrupt the external device. In node 18 control on the element And 56 Normalized signal, which through the element OR 11 enters the reset input of the trigger 15 and resets it.

When reading the values of the register 7 modes and the trigger 8 on the address bus

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31 external device and bus 30 Read external device receives: the address common for the mode register 7 and the trigger 8, and the read control signal. Since in the absence of a control signal for reading regxgra 9 output information at the control input of multiplexer 20, it is always set to pass information from the output of the register- and page 8 of the mode and the trigger 8, and the bus driver 13 is controlled by a signal on the bus 30 Read external device - with control signal

reading on the bus 30 reading the external

devices a single trigger value is read into the input information bus 28 of an external device. At the control node 18, the address is fed to the input of the decoder 69 and from its output JQ to the input of the AND element 66, the second input of which receives the read control signal. The signal from the output of the element And 66 is fed to the synchronous inputs of the trigger

Ditch 87 - 89 register 7 mode and trig 25). The data byte is from register 9 of schiger 8, which are reset to the initial state by the falling edge of the read control signal.

When reading the command code from the output information register 9, the address bus 31 of the external device and the bus 30 Read the external device to the control unit 18 receives the address of the output information register 9 and the read control signal. The address is fed to the input of the decoder 69 and from its output to the input of the And 67 element. The And 67 also receives the read control signal. The signal formed on the element AND 67 through the element OR 70 is fed to the control input of the multiplexer 20, setting it to pass information from the output of the register 9 of the output information.

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Signal on the bus Reading the external device, the further reading of the register of the 9th resolution permits the passage of the information output is not performed, from the output of the multiplexer 20 to the input information bus of the external device. Thus, the command code from the output information register 9, the passage through the multiplexer 20 and the bus driver 13, is read into the input information bus 28 of the external device.

The procedure for transferring data from the processor to an external device is performed by executing a write command and is initiated by the firmware.

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During the initial recording in the trigger 16 of the register of 14 signs, the address of the bus 31 of the external device and the bus 29 of the external device receive the address of the trigger 16 and the write control signal, from which in the control unit 18 the write control signal appears at the output of the And 63 element 16, which enters the node 26 fixing the mode of operation, through the .OR element 77, to the installation input of the trigger 16.

external device. After analysis

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the command code for writing and receiving the value of receiving the register of 7 modes, the firmware of the external device writes the value of Zan into the register 24 bytes

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current status and attribute Required data in the trigger 16 register 14 signs. A single trigger value I6 causes a processor firmware interrupt signal on the processor interrupt input bus 6. On the interrupt signal, the processor firmware reads the register value of 14 features and analyzes it. After reading the register of 14 features, it is reset. On the basis of Required data processor firmware writes data bytes in the register 9 of the output information. When writing a data byte, a flip-flop 73 is set and a signal appears at its output, which, via bus 34, requests a direct access to the device (external

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goes to external device. When reading the output register 9, trigger 16 is set again. Register data 14 characters are required. For a single trigger value 16, an interrupt appears on the output bus 6 of the processor. The next cycle of data byte transfer from the processor to the external device is organized. The cycle is repeated until the data block in the processor is exhausted. To complete the procedure, the processor for the attribute Required data responds by writing to the register of 7 modes of indication. End of data transfer. Firmware external device, reading the register value of 7 modes with the pointer End of data transfer, completes

the procedure, further reading of the register 9 of the output information is not performed,

During the initial recording in the trigger 16 of the register of 14 signs, the address of the bus 31 of the external device and the bus 29 of the external device receive the address of the trigger 16 and the write control signal, from which in the control unit 18 the write control signal appears at the output of the And 63 element 16, which enters the node 26 fixing the mode of operation, through the .OR element 77, to the installation input of the trigger 16.

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When reading the register value of 14 signs on the address bus 4 of the processor and the mine of the processor, the address and the read control signal are received. At the control node 18, the address value is fed to the inputs of the decoder 68, at the output of which a signal appears that goes to the element's stroke AND 60. The other input of the element And 60 receives the control signal, reading. At the output of the | 4 60 element, a read control signal is generated for the register of 14 signs, which is fed to the trigger inputs of the flip-flops 6 and 17 and, on the falling edge of the signal L, resets them to the initial state.

When writing a data byte to the output register 0, the address of the data byte entry into the output information register 9 and the recording control signal are sent to the address bus 4 of the processor and bus 2 Record of the Processor. At node 18 of the control and at the output of the element 57, a signal appears to control writing the data to the register 9 of the output information. This signal through the element OR 19 is fed to the recording of the register of the output information and to the operation-fixing unit 26. In the output information register 9, a data byte is written, at the fixing mode of the operation mode through the element OR 75, the signal enters the set trigger input 73 and sets it to a single value. At the output of the flip-flop 73, a signal appears, which, via bus 34, requests a direct access to the external device.

When reading a byte of data from the output information register 9 via bus 33 Direct access permission and bus 30 An external device is fed to the input element And 80 of the node 26 fixing the operating mode, a feedback signal from an external device and a read control signal. At the output of the element And 80, a signal appears that goes through the element OR 76 to the Reset input of the trigger 73 and resets it, through the element OR 77 enters the installation input of the trigger 16 of the register of 14 signs and sets it to a single value, as well as through the element OR 70 of the control unit 18 enters the control input of the cultlexer 20 and controls the passage of the register information 9 the output

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information through the multiplexer 20. At this point in time, the bus driver 13 is opened by a signal on the bus 30 Read an external device, and the output information register 9 appears on the input information bus 28 of the external device.

The procedure for transferring data from an external device to the processor is initiated by the firmware of the external device. After analyzing the command code for reading and receiving the value of register reception 7 modes, the external firmware, the device writes the value of Zanto to the register 24 bytes of the current state, configures the external device to read data in direct access mode from the external memory and to initiate the mode direct access writes to the trigger 72 of the read mode of the node of the fixation of the output-receive mode. Trigger 72 is set to trigger 73 by a single value. Bus 34 A request for direct access11 receives a signal, in response to which an external device on the output information bus 35 interferes with a byte of information, on bus 33 the permission of direct access feedback signal, and Bus 29 Write external device - write control signal, which records the data byte to the input information register 25. This sets the trigger 17 in the register of 14 features. The installation of the trigger 17 causes an interrupt signal to appear on the input bus 6 of the processor interrupt. The processor firmware organizes reading a byte of data from the register 25 of the input information. When the output information register 25 is read, trigger 73 is set again and a signal appears on bus 34 A direct access request, in response to which a byte of information appears on the output information bus 35, a signal on bus 29 External device recording and bus 33 Direct access permission . The cycle of transmitting the data byte to the processor is repeated. When transferring the last byte of data, except for the signal on the bus 29 Recording the external device and bus 33 Permission of direct access, there is a signal on the bus 32 End of the block. With this signal present, trigger 73 is not set and afterwards

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Data transfer from an external device to the processor does not take place.

When writing to the trigger 72 via the output information bus 35 of the external device, the information input of the trigger 7.2 receives a single value, the address of the trigger 72, common with the address of the trigger 15, goes to the address bus 31 of the external device, and the control signal by record. In the control unit 18 on the AND 64 element, the write control signal is generated in the trigger 72, which from the output 48 enters the synchronous input of the trigger 72. The trigger 72 is set to a single value. The signal from the trigger output 72 is fed to the trigger trigger 73, the information input of which contains the unit value of the single potential bus 38. The trigger 73 is set to a single value and a signal appears on the bus 34 A direct access request. A flip-flop 73 is set on the signal front from flip-flop 72.

When writing a data byte to the input information register 25, the data information output bus of the external device receives a data byte, and bus 33 Enable direct access and the bus 29 Write external device receive feedback and recording control signals. On the element 81, a signal is generated, which through the element OR 76 enters the reset input of the trigger 73 and brings it to its initial state, through the element OR 78 enters the input of the record of the input information register 25, as well as the input of the element 82. In register 25 input data is written to the data byte, and the trigger 17 is set to a single value. A single trigger value 17 causes the appearance of an interrupt signal on the input bus 6 of the processor interrupt.

When reading the data byte of the register 25 of the input information via the address bus 4 of the processor and bus 3 of the processor, the address of the input information register 25 and the read control signal are received. The address of the input information register 25, specified in two bits, is fed to the input of the multiplexer 23 and to the inputs of the decoder 68 of the control unit 18. Register value

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25 of the input information passes through the multiplexer 23 and the bus driver 12 to the input information block 5 of the processor. The element And 61 of the control node 18 receives signals from the output of the decoder 68 and from the bus 3 Read processor. At the output of the element And 61, a signal is generated, which arrives at the node 26 of fixing the mode of operation to the input of the element And 83. The inputs of the element And 83 also receive signals from the inverse arm of the trigger 71, which by this moment is in the reset state, as well as from the straight shoulder of the trigger 72, which is in the established state. At the output of the element And 83, a signal arises, which through the element OR 75 enters the installation input of the flip-flop 73, sets it to one state. On bus 34 Request Direct Access, a request signal for the next data byte occurs.

When writing the last byte of data into the input information register 25, B, the operation mode fixation node 26 via bus 33 Direct access permission and 29 External device recording receives a feedback signal and a recording control signal, in addition, bus 32 receives a tracking signal for the last device. data byte. On the element 82 of the Form a-1 signal, which arrives at the installation input of the trigger 71 and sets it to one state, and also, through the element OR 78, enters the input of the record of the input information register 25. A data byte is written to the input register 25. The trigger 17 is set to a single value. A single trigger value 17 causes the appearance of an interrupt signal on the input bus 6 of the processor interrupt.

When reading the last byte of data from register 25 of the input information, trigger 73 is not set, since the inverse output of trigger 71 in this case has a zero value and element 83 does not generate a trigger setup signal 73.

The procedure for transferring the status byte to the processor is initiated by the firmware of the external device. The firmware of the external device writes the status byte to the input information register 25 and the unit value30.

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the trigger 15 register of 14 signs. A single trigger value 15 causes an interrupt signal to occur on the processor interrupt bus 6. On the interrupt signal, the processor firmware reads the value of the register of 14 signs and analyzes it. For a single trigger value 159 identifying the interrupt signal Q as a request for transmitting a status byte, and information in the input information register 25 as a status byte, the value of the status ban is read into the processor from the input information register 25. The processor firmware updates the 7 modes of the characteristic to the register. The reception, which causes the appearance of the interrupt signal on the input bus 2Q, is not 27 of the external device interruption, as well as the reset of the trigger 15. On the interrupt signal, the firmware of the external device reads the register 7 modes and his analysis. After 25 readings of register 7, it is reset to zero. The state byte transfer procedure is terminated.

When writing the status byte to the input information register 25, the output by JQ informational bus 35 receives the status byte, the address bus 31 of the external device and the bus 29 Write the address of the input information register 25 and the write control signal. where on the element AND 65 A control signal is written to the input information register 25, which enters the operation mode fixation section 26 and, via the OR element 79, writes the input information to the input information register input 25, In input information register 25 neither .

When writing to the trigger 15 of the register 14 of the sign of the status byte, the information input of the trigger 15 via the input information bus 35 of the external device receives a single value of the write bit to the trigger 15, the address of the trigger 15 arrives on the address bus 31 of the external device and recording control signal. In the control node 18 on the AND 64 element, the write control signal is generated in the trigger 15 and sets it to a single value, and also enters the operation mode fixation section 26 at the information input

50

55

 ,

0

five

trigger 72 for writing a zero value thereto. Thus, when a single value is written to the trigger 15, a zero value is written to the trigger 72. A single trigger value 15 is fed to the input of the interrupt signal generator 10, causing an interrupt signal to appear on the input bus 6 of the processor, as well as to the operation mode fixing unit 26, where the passage through the OR 74 element enters the reset input of the trigger 71 and resets it in the initial state -. the

The reading of the trigger value 15 is performed in the same way as when performing the initial sampling procedure.

The reading of the status byte from the input information register 25 differs from reading the data byte in that by the time of reading the status byte, the trigger 72 of the operation mode node 26 is in the reset state and the setting signal 73 is not generated on the AND 83 element. The mode register 7 is implemented in the same way as in the initial sampling procedure.

When writing to the trigger 89 of the register of 7 modes on the element And 56 of the control unit 18, a reset signal is generated for the trigger 15, with which the trigger 15 is reset. A single trigger value 89 causes an interrupt signal to appear on the input bus 27 of the external device,

The reading of register 7 modes is done in the same way as in the initial sampling procedure.

Thus, the device, in comparison with the prototype, has enhanced functionality that allows identifying information as a command or status byte, storing the current status byte, storing the initial state bytes, and generating an interrupt signal to an external device. Extending the functionality in the device allows, in addition to the data transfer procedure, to perform the initial sampling and the state byte transfer procedures, i.e. the whole set of procedures., input - output according to the logic of the EC interface of the computer.

Storing the byte of the current state and the bytes of the initial state in the device shortens the execution time of the initial sampling procedure. In known devices, to perform an initial sample, the command code is transmitted to an external device, where the firmware analyzes the current state byte, generates and transfers the initial state byte to the processor. Because

In this device, the initial sampling procedure is performed in hardware at the processor-interface level, its execution time is significantly less than in known conditions. For example, it takes about 370 ms to program the initial sampling in the EC1007 computer, which add up to an average of , from the execution time of 100 interrupt handling commands (with a single command execution time of 7.5 microseconds), 30 device interrogation commands, 350 ms to wait for a response from the device and the execution time of 100 commands to analyze the incoming command and Write the initial byte. condition When using this device, the execution time of the initial sample does not exceed 7 microseconds. By increasing the speed of the initial sampling procedure, the speed of the entire I / O procedure is improved.

Claims (3)

1. A device for interfacing a processor with an external device, containing a control unit, a latching unit, a mode register, an input information register, an output information register, the first interrupt generator, and a group of information inputs of the mode register, output information register and the first input of the logic condition of the control node forms a group of device inputs for connecting to the group of information outputs of the processor, the output of the interrupt generator of the first interrupt signal generator is swing device for connecting to the input of the interrupt processing, a first gate input and an output request direct access node operation mode locking are input and output device for connection respectively to the output enable direct access to the input query and direct access 0 j 0 5 o five about 0 external device, characterized in that, in order to improve speed, a feature register, two multiplexers and two bus drivers, a current state byte register, an encoder, a second interrupt signal generator, two OR elements, a trigger with the second logic state input the control node is the input of the device for connection to the write output of the processor, the third input of the logic condition of the control node is connected to the control input of the first bus driver and is the input of the device At the readout connection of the processor, the first group of inputs of the logic condition of the control node and the group of control inputs of the first multiplexer form a group of device inputs for connecting the processor to the output address group, the group of information outputs of the first bus converter forms a group of device outputs to connect to the group information inputs of the processor, the output of the chopper of the second interrupt signal generator is the output of the device for connection to the interrupt input of the external Triplets, the group of information outputs of the second bus driver forms a group of device outputs for connection to a group of information inputs of an external device, a group of information inputs of the current state byte register and an input information register, the first information inputs of the operation mode fixing node and the register of attributes form a group of device inputs for connecting to the group of information outputs of the external device, the second gate input of the latching node of the operation mode is the device input for Connected to the output end of an external device block, the second group of inputs of the logic condition of the control node forms a group of inputs of the device for connecting to the group of address outputs of the external device, the fourth input of the logic condition of the control node is connected to the third gate input of the fixing node of the operating mode and is the input of the device for connecting and the output of the external device, the fifth input of the logic condition of the control node is connected to the fourth 23155 the gate input of the latching mode, with the control input of the second bus driver and is the device input for connecting to the read output of the external device, the setup input of the mode register is connected to the zero trigger input, with the first, second, zero signs register inputs, with the first input the first element OR, with the first installation input of the Latching register of the operation mode and is the installation input of the device, the information inputs of the mode register, the trigger, the first, second information inputs the feature register is connected to the zero potential bus of the device, the second information input of the fixation unit of the operating mode is connected to the error of the unit potential of the device, while the first output of the control node Penalties are connected to the recording register register input, the read input of which is connected to the second output of the control node and to the trigger synchronous input, the output of which and the group of information outputs of the mode register are connected to the input group of the interrupt request signal of the second interrupt generator and the first group of information inputs of the second multiplexer , the second group of information inputs of which is connected to the group of Information outputs of the register of output information and with the group of information inputs of the encoder, the group O one of which is connected to the first group of information inputs of the first multiplexer, the second group of information inputs of which is connected to the group of inputs of the interrupt request of the first Interrupt signal generator, with the third information input of the fixing node of the operation mode and the group of information outputs of the characteristics register, the first and second single inputs of which are connected respectively, with the petey and second installation outputs of the fixing unit of the operation mode, the recording output of which is connected to the input of the register entry I discharge information, the group of information outputs of which is connected with the third group of information inputs of the first multiplexer, a fourth group bayga register which is connected to a group of information inputs with information output current 24 0 0 five 0 five five five the recording input of which is connected to the third output of the control node, the fourth, fifth, sixth outputs and the sixth input of the logic condition of which are connected respectively to the first, second, third inputs of the logic condition and the reading output of the fixation node of the operation mode, the synchronous input of which connected to the seventh output of the control unit and to the first synchronized input of the sign register, the second and third synchronized inputs of which are connected to the eighth output of the controlling node, the ninth output of which is connected to the second input of the first OR element, the stroke of which is connected to the third zero input of the feature register, the third single input of which is connected to the single trigger input, to the first input of the second OR element and to the tenth output of the control node, the eleventh output of which is connected to the second installation input of the Operation mode hold node and to the second the input of the OR element, the output of which is connected to the input of the output register recording, the group of information inputs of the first bus driver is connected to the group of information outputs of the first multiplexer, group The information input of the second bus driver is connected to the group of information outputs of the second multiplexer, the control input of which is connected to the twelfth output of the control node, 2 "Device according to claim I, characterized in that the control node contains two decoders, twelve AND elements and an OR element, the first input of the first AND element being the first input of the logical condition of the node, the first input of the second AND element connected to the first inputs of the third, the fourth AND element is the second input of the logical condition of the node, the first input of the fifth element AND is connected to the first input of the sixth AND element and is the third input of the logical condition of the node, the first input of the seventh AND element is connected to the first inputs of mogo, ninth, and tenth members and is fourth input node of the logical conditions, the first input of the eleventh AND gate is connected to the first input of the twelfth AND gate and EMC is a fifth input node logical conditions, lane 2515 the second input of the OR element is the sixth input of the logical condition of the node; the second inputs of the second, third, fourth elements AND the group of information inputs of the first decoder form the first group of inputs of the logical condition of the node; the group of information inputs of the second decoder forms the second group of inputs of the logical node condition; And is connected to the second input of the first element AND, and is the first output of the node, the outputs of the eleventh, seventh, eighth, sixth, tenth, ninth, fifth, first, fourth , the second And elements and the output of the OR element are respectively the second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleven, and twelfth node outputs, while in the control node the first and second outputs of the first decoder are connected respectively, with the second inputs of the fifth and sixth elements And, the second input of the element OR is connected to the output of the twelfth element And, the second input of which is connected to the second input of the seventh element And and to the first output of the second decoder, the second output of which is connected to the second the input of the eighth element And; the second input of the ninth element I is connected to the second input of the eleventh element I and to the third output of the second decoder, the fourth output of which is connected to the second input of the tenth element I. 40 3. The device according to claim 1, characterized in that the latching operation node contains three flip-flops, six OR elements, four AND elements, and the information inputs of the first, second triggers and the first input of the first OR element are respectively the first, second and third information the inputs of the node, the second input of the first element OR connected to the zero input of the first 26 0 the trigger and with the first input of the DTODOIO of the OR element, and the first input of the third OR element are respectively the first and second installation inputs of the node, the synchronous input of the first trigger is synchronized with the first input of the first element And connected to the first input of the second element AND, the first the input of the third element AND, the second inputs of the second and first elements I are the first, second, third and fourth gates of the node, the first input of the fourth element OR, the first input of the fourth element AND and the first input n th 0 25 0 five 0 the OR elements are respectively the first, second and third inputs of the logical condition of the node, the output of the second trigger is the output of the direct access request of the node, the output of the fourth OR element and the output of the sixth OR element connected to the second input of the fifth OR element are respectively the first and the second installation outputs of the node, the output of the first AND element, connected to the second inputs of the second and fourth OR elements, and the output of the fifth OR element are respectively the read and write outputs of the node, while in the node mode of operation, the output of the first element OR is connected to the zero input of the third trigger, the single input of which is connected to the first input of the sixth OR element and to the third output of the AND element, the second input of which is connected to the output of the second AND element, to the second input of the sixth OR element and to the third the input of the second element OR, the output of which is connected to the zero input of the second trigger, the sync input of which is connected to the output of the first trigger and to the second input of the fourth element I, the output of which is connected to the second input of the third el ment OR, whose output is connected to a single input of the second flip-flop, third flip-flop output coupled to a third input of the fourth element I. FIG A