CN116169037B - Preparation method of chip packaging structure - Google Patents

Abstract

The invention provides a method for preparing a chip packaging structure, comprising: providing a temporary carrier; forming a laminated metal layer on the temporary carrier; forming a rewiring structure on the surface of the laminated metal layer away from the temporary carrier; A chip body is provided on the side of the wiring structure away from the stacked metal layer; a conductive connector is formed between the chip body and the rewiring structure; an underfill glue layer encapsulating the conductive connector is formed; a wrapped chip is formed on the side of the rewiring structure The plastic encapsulation layer of the body; after that, the temporary carrier and the laminated metal layer are debonded; after the temporary carrier and the laminated metal layer are debonded, the laminated metal layer is removed by a wet etching process, and the medium in the rewiring structure is exposed layer; after the stacked metal layer is removed by wet etching, a part of the thickness of the dielectric layer is removed from the side of the rewiring structure away from the chip body by dry etching. The preparation method of the chip packaging structure improves the reliability of the chip packaging structure.

Description

A kind of preparation method of chip packaging structure

technical field

The invention relates to the technical field of semiconductor packaging, in particular to a method for preparing a chip packaging structure.

Background technique

A method for preparing a wafer-level fan-out packaging structure, comprising: preparing a laminated metal layer M' by sputtering on a temporary bonding adhesive layer F1' on a temporary carrier C1'; preparing a laminated metal layer M' on the laminated metal layer M' A rewiring structure 10', wherein the rewiring structure 10' includes a dielectric layer 10b' and a conductive layer 10a'; on one side of the rewiring structure 10', the chip body 20' is electrically connected to the On the rewiring structure 10'; in the space between the chip body 20' and the rewiring structure 10', an underfill glue layer 40' surrounding the interconnect conductor 30' is formed; on one side of the rewiring structure 10' Cover the underfill adhesive layer 40' and the plastic sealing layer 50' of the chip body 20', and thin the plastic sealing layer 50' until the passive surface of the chip body 20' is exposed; as shown in Figure 1, debonding removes the temporary Carrier C1'; chemical etching removes the stacked metal layer M' and exposes the dielectric layer 10b' of the rewiring structure 10', and then prepares an electrical terminal layer on the surface of the rewiring structure 10' facing away from the chip body 20' desired seed layer.

However, the above-mentioned package structure has low reliability.

Contents of the invention

Therefore, the technical problem to be solved by the present invention is to solve the problem of low reliability of the chip packaging structure in the prior art, so as to provide a method for preparing the chip packaging structure.

The invention provides a method for preparing a chip packaging structure, comprising: providing a temporary carrier; forming a laminated metal layer on the temporary carrier; forming a metal layer on the surface of the laminated metal layer away from the temporary carrier A rewiring structure; a chip body is provided on a side of the rewiring structure away from the stacked metal layer; a conductive connection is formed between the chip body and the rewiring structure; and a conductive connection is formed to encapsulate the conductive connection an underfill adhesive layer; form a plastic encapsulation layer wrapping the chip body on one side of the rewiring structure; after forming the plastic encapsulation layer, debond the temporary carrier and the stacked metal layer; After the temporary carrier board and the stacked metal layer are debonded, the stacked metal layer is removed by wet etching process, and the dielectric layer in the rewiring structure is exposed; the stacked metal layer is removed by wet etching process After layering, a partial thickness of the dielectric layer is removed from the side of the rewiring structure away from the chip body by using a dry etching process.

Optionally, the step of forming a stacked metal layer on the temporary carrier includes: sequentially forming a stacked first metal layer to a Wth metal layer on the temporary carrier, where W is an integer greater than or equal to 2; The step of removing the laminated metal layer by using a wet etching process includes: sequentially removing the first metal layer to the Wth metal layer; the step of removing any wth metal layer is: using the wth wet etching solution to remove the wth metal layer, w is an integer greater than or equal to 1 and less than or equal to W.

Optionally, the step of forming a stacked metal layer on the temporary carrier includes: sequentially forming a stacked first metal layer, a second metal layer and a third metal layer on the temporary carrier, the first metal layer , the materials of the second metal layer and the third metal layer are different; the step of removing the laminated metal layer by using a wet etching process includes: removing the first metal layer by using a first wet etching solution; After the etching solution removes the first metal layer, the second wet etching solution is used to remove the second metal layer; after the second wet etching solution is used to remove the second metal layer, the third wet etching solution is used to remove the third metal layer. The first wet etching solution, the second wet etching solution and the third wet etching solution are different.

Optionally, the material of the first metal layer is Al, the material of the second metal layer is Ti or a titanium-based alloy, and the material of the third metal layer is Cu.

Optionally, the first metal layer has a thickness of 0.1 micron to 1 micron; the second metal layer has a thickness of 0.1 micron to 1 micron; and the third metal layer has a thickness of 0.1 micron to 1 micron.

Optionally, the material of the dielectric layer includes epoxy resin; the dry etching process is a plasma dry etching process, and the plasma dry etching process uses oxygen plasma.

Optionally, the thickness of the dielectric layer removed from the side of the rewiring structure away from the chip body by a dry etching process is 0.1 microns to 5 microns.

Optionally, the thickness of the dielectric layer removed from the side of the rewiring structure away from the chip body by using a dry etching process is 0.2 micron to 1 micron.

Optionally, it also includes: after removing a partial thickness of the dielectric layer from the side of the rewiring structure away from the chip body by using a dry etching process, on the surface of the side of the rewiring structure away from the chip body Forming a seed layer; forming an electrical terminal layer on a part of the surface of the seed layer facing away from the rewiring structure.

Optionally, after removing a partial thickness of the dielectric layer from the side of the rewiring structure away from the chip body by using a dry etching process and before forming the seed layer, the dielectric layer is away from the plastic package The concentration of metal ions on one side surface of the layer is less than or equal to 10 ppm.

Optionally, it also includes: forming a sacrificial adhesive protective layer covering the electrical terminal layer on the side of the seed layer away from the rewiring structure; after forming the sacrificial adhesive protective layer, sealing the plastic sealing layer Grinding the side surface away from the rewiring structure until the passive surface of the chip body is exposed; forming a heat conducting layer on the surface of the plastic encapsulation layer and the chip body facing away from the rewiring structure; after forming the heat conducting layer and peeling off the sacrificial bonding protection layer from the electrical terminal layer and the seed crystal layer.

Optionally, after the sacrificial bonding protective layer is peeled off from the electrical terminal layer and the seed layer, the seed layer not covered by the electrical terminal layer is removed; or, after forming the sacrificial bonding layer, Before the protective layer, the seed layer not covered by the electrical terminal layer is removed.

Optionally, the seed layer is a single-layer structure or a multi-layer structure; when the seed layer is a multi-layer structure, the method for forming the seed layer includes: On one side of the body, the stacked first sub-seed layer to the Gth sub-seed layer are sequentially formed, and G is an integer greater than or equal to 2; the method for forming the electrical terminal layer includes: part of the seed layer deviates from the One side surface of the rewiring structure is sequentially formed with stacked first sub-terminal layer to Nth sub-terminal layer, N is an integer greater than or equal to 2; when the seed crystal layer is a single-layer structure, the seed crystal layer The material is the same as that of the first sub-terminal layer; when the seed layer has a multi-layer structure, the material of the Gth sub-seed layer is the same as that of the first sub-terminal layer.

The technical solution of the present invention has the following beneficial effects:

In the preparation method of the chip packaging structure in the technical solution of the present invention, in the step of removing the laminated metal layer by using a wet etching process, the metal ions of the corresponding layers in the laminated metal layer will also be dissolved in the wet etching process. In the chemical solution, metal ions in the chemical solution inevitably remain on the surface of the rewiring structure, especially on the surface of the dielectric layer exposed to the chemical solution environment. However, after the stacked metal layer is removed by wet etching, a part of the thickness of the dielectric layer is removed from the side of the rewiring structure away from the chip body by dry etching, so as to remove as much as possible the embedded The metal ions on the surface of the dielectric layer, the metal complexes produced in the step of removing the laminated metal layer by the wet etching process also become gaseous and removed from the dielectric layer in the dry etching process, which greatly reduces the weight The concentration of metal ions on the surface of the dielectric layer on the side of the wiring structure away from the chip body, and then cut off the stray transmission path established by the current signal or power signal through the metal ions and metal complexes in the dielectric layer, is conducive to realizing The integrity of the signal or power transmission path in the conductive layer of the redistribution structure. In summary, the reliability of the chip packaging structure is improved.

Further, a seed layer is formed on a surface of the rewiring structure away from the chip body. Since metal ions and metal complexes are not dispersed on the surface of the dielectric layer, the interface bonding strength between the dielectric layer and the seed layer is improved, and the gap between the dielectric layer and the seed layer is avoided in the subsequent packaging process and reliability test involving heat treatment. layered between.

Further, after removing a partial thickness of the dielectric layer from the side of the rewiring structure away from the chip body by using a dry etching process and before forming the seed layer, the side of the dielectric layer away from the plastic encapsulation layer The concentration of metal ions on one surface is less than or equal to 10ppm, so that the concentration of metal ions on the surface of the dielectric layer on the side of the rewiring structure away from the chip body is very small, further improving the reliability of the chip packaging structure.

Description of drawings

In order to more clearly illustrate the specific implementation of the present invention or the technical solutions in the prior art, the following will briefly introduce the accompanying drawings that need to be used in the specific implementation or description of the prior art. Obviously, the accompanying drawings in the following description The drawings show some implementations of the present invention, and those skilled in the art can obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic diagram of the preparation process of a chip packaging structure in the prior art;

2 is a flowchart of a method for preparing a chip package structure provided by an embodiment of the present invention;

FIG. 3 to FIG. 12 are structural schematic diagrams of the manufacturing process of the chip packaging structure provided by an embodiment of the present invention.

Detailed ways

The technical solution of the background technology has the problem of poor reliability. After research by the inventor, the reason is that:

First of all, after debonding and removing the temporary carrier C1′, the stacked metal layer M′ is usually removed by chemical etching, and the metal ions of the corresponding layers in the stacked metal layer M′ will also be dissolved in the chemical corrosion solution, which is unavoidable. The metal ions in the chemical solution remain on the surface of the dielectric layer 10b' in the rewiring structure 10', and the metal complexes formed in the step of removing the stacked metal layer M' by chemical etching will also remain on the rewiring structure 10' On the surface of the dielectric layer 10b', the metal ions and metal complexes remaining or embedded in the dielectric layer 10b' will accelerate the diffusion in the subsequent packaging process involving heat treatment, and the chip packaging structure in the working state will also intensify The diffusion of metal ions and metal complexes in the medium layer 10b' may cause the metal ions and metal complexes to diffuse in the medium layer 10b' of a wider area, and the metal atoms in the conductive layer 10a' may be dispersed in the medium layer 10b'. A weak stray transmission path of electrons is established between the metal ions and metal complexes in the dielectric layer 10b', thereby affecting the integrity of the power signal transmission path; moreover, the dispersion of metal ions and metal complexes on the surface of the dielectric layer will also Reducing the interfacial bonding strength between the dielectric layer 10b' and the seed layer will easily lead to delamination between the dielectric layer 10b' and the seed layer in subsequent packaging processes involving heat treatment and reliability testing. In summary, the reliability of the chip packaging structure is reduced.

On this basis, the present invention provides a method for preparing a chip packaging structure, comprising: providing a temporary carrier; forming a laminated metal layer on the temporary carrier; A rewiring structure is formed on one side surface of the rewiring structure; a chip body is provided on the side of the rewiring structure away from the stacked metal layer; a conductive connection is formed between the chip body and the rewiring structure; an encapsulation is formed The underfill adhesive layer of the conductive connector; a plastic encapsulation layer wrapping the chip body is formed on one side of the rewiring structure; after the plastic encapsulation layer is formed, the temporary carrier and the laminated metal layer Debonding; after debonding the temporary carrier and the stacked metal layer, using a wet etching process to remove the stacked metal layer, and exposing the dielectric layer in the rewiring structure; using a wet etching process to remove After the stacked metal layers, a partial thickness of the dielectric layer is removed from the side of the rewiring structure away from the chip body by using a dry etching process.

The technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, or in a specific orientation. construction and operation, therefore, should not be construed as limiting the invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and should not be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that unless otherwise specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention in specific situations.

In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as there is no conflict with each other.

This embodiment provides a method for preparing a chip package structure, referring to FIG. 2 , including:

Step S1: Provide a temporary carrier board.

Step S2: forming a laminated metal layer on the temporary carrier.

Step S3: forming a rewiring structure on the surface of the laminated metal layer facing away from the temporary carrier.

Step S4: disposing a chip body on a side of the rewiring structure away from the stacked metal layer.

Step S5: forming a conductive connection between the chip body and the rewiring structure.

Step S6 : forming an underfill adhesive layer encapsulating the conductive connector.

Step S7: forming a plastic encapsulation layer wrapping the chip body on one side of the rewiring structure.

Step S8: after forming the plastic encapsulation layer, debonding the temporary carrier and the laminated metal layer.

Step S9: After debonding the temporary carrier and the laminated metal layer, the laminated metal layer is removed by wet etching process, and the dielectric layer in the rewiring structure is exposed.

Step S10: After removing the stacked metal layer by wet etching, remove a part of the thickness of the dielectric layer from the side of the rewiring structure away from the chip body by using dry etching.

In this embodiment, in the step of removing the stacked metal layer by wet etching process, the metal ions of the corresponding layers in the stacked metal layer will also be dissolved in the chemical solution of the wet etching process, which inevitably causes The metal ions in the chemical solution remain on the surface of the rewiring structure, especially on the surface of the dielectric layer exposed to the chemical solution environment. However, after the stacked metal layer is removed by wet etching, a part of the thickness of the dielectric layer is removed from the side of the rewiring structure away from the chip body by dry etching, so as to remove as much as possible the embedded The metal ions on the surface of the dielectric layer, the metal complexes produced in the step of removing the laminated metal layer by the wet etching process also become gaseous and removed from the dielectric layer in the dry etching process, which greatly reduces the weight The concentration of metal ions on the surface of the dielectric layer on the side of the wiring structure away from the chip body, and then cut off the stray transmission path established by the current signal or power signal through the metal ions and metal complexes in the dielectric layer, is conducive to realizing The integrity of the signal or power transmission path in the conductive layer of the redistribution structure. In summary, the reliability of the chip packaging structure is improved.

3 to 12 will be described in detail below.

Referring to FIG. 3 , a temporary carrier C1 is provided; a stacked metal layer M is formed on the temporary carrier C1 .

The material of the temporary carrier C1 includes glass, stainless steel or silicon.

The temporary carrier C1 provides mechanical support for the preparation of the laminated metal layer M.

Specifically, a temporary carrier C1 is provided, and one side surface of the temporary carrier C1 has a temporary bonding adhesive layer F1; a laminated metal layer M is formed on the side of the temporary bonding adhesive layer F1 away from the temporary carrier C1.

The process of forming the stacked metal layer M includes a sputtering process.

The step of forming the stacked metal layer M on the temporary carrier C1 includes: sequentially forming stacked first to Wth metal layers on the temporary carrier, W is an integer greater than or equal to 2.

In some embodiments, the step of forming a stacked metal layer M on the temporary carrier C1 includes: sequentially forming a stacked first metal layer m1, a second metal layer m2, and a third metal layer M on the temporary carrier C1. The materials of the metal layer m3, the first metal layer m1, the second metal layer m2 and the third metal layer m3 are different.

In some embodiments, the material of the first metal layer m1 is Al, the material of the second metal layer m2 is Ti or a titanium-based alloy, and the material of the third metal layer m3 is Cu.

The first metal layer m1 is used for better bonding with the temporary bonding adhesive layer F1. The second metal layer m2 is used to increase the bonding force between the first metal layer m1 and the third metal layer m3. The third metal layer m3 is used to generate better bonding force with the conductive layer in the subsequent rewiring structure.

In some embodiments, the thickness of the first metal layer m1 is 0.1 micron to 1 micron; the thickness of the second metal layer m2 is 0.1 micron to 1 micron; the thickness of the third metal layer m3 is 0.1 micron ~1 micron.

Referring to FIG. 4 , a rewiring structure 10 is formed on the surface of the laminated metal layer M facing away from the temporary carrier C1 .

The temporary carrier C1 provides mechanical support for the preparation of the redistribution structure 10 .

It should be noted that, in this embodiment, before the rewiring structure 10 is formed on the side surface of the laminated metal layer M away from the temporary carrier C1 , the laminated metal layer M is patterned. In other embodiments, before the rewiring structure 10 is formed on the surface of the metal layer M facing away from the temporary carrier C1 , there is no need to pattern the metal layer M.

In this embodiment, the rewiring structure 10 includes: a dielectric layer 10b and a conductive layer 10a located in the dielectric layer 10b, and the conductive layer 10a may be provided with several layers. The dielectric layer 10b includes a first dielectric layer to a Qth dielectric layer, the first dielectric layer to the Qth dielectric layer are arranged in the thickness direction of the redistribution structure 10, and Q is an integer greater than or equal to 2. The conductive layer 10a includes a first conductive layer to a Qth conductive layer. The qth dielectric layer has a qth patterned opening. The qth conductive layer is located in the qth patterned opening. The material of the medium layer includes epoxy resin. Wherein, q is an integer greater than or equal to 1 and less than or equal to Q.

The step of forming the rewiring structure 10 includes: sequentially forming the first dielectric layer to the Qth dielectric layer on the surface of the laminated metal layer M facing away from the temporary carrier C1, and the qth dielectric layer has a q patterning openings; sequentially forming the first conductive layer to the Qth conductive layer on the surface of the laminated metal layer M facing away from the temporary carrier C1; the step of forming the qth conductive layer is: A qth conductive layer is formed in the q patterned opening. The first conductive layer is electrically connected to the laminated metal layer M.

In this embodiment, it further includes: forming an interconnection pad 301 on one side surface of the rewiring structure 10 . The interconnect pad 301 is electrically connected to the conductive layer 10a.

Continuing to refer to FIG. 4 , a chip body 20 is provided on a side of the rewiring structure 10 away from the stacked metal layer M. Referring to FIG.

The chip body 20 includes an embedded chip pad located on one side of the active surface of the chip body 20 .

A conductive post 302 is provided on the surface of the built-in pad of the chip; a soldering layer 303 is provided on the surface of the conductive post 302 facing away from the chip body 20 .

In some embodiments, the conductive pillar 302 is connected to the interconnection pad 301 through the solder layer 303 by a reflow process, so as to realize the interconnection between the chip body 20 and the rewiring structure 2 . The conductive pillar 302 is connected to the interconnect pad 301 through the solder layer 303 . The solder layer 303 is located between the conductive pillar 302 and the interconnection pad 301 . The conductive pillar 302 , the solder layer 303 and the interconnection pad 301 form a conductive connection 30 . There is a conductive connection 30 between the chip body 20 and the rewiring structure 10 . The chip body 20 is electrically connected to the rewiring structure 10 through the chip built-in pads, the conductive pillars 302 , the soldering layer 303 , and the interconnection pads 301 in sequence.

In some other embodiments, the conductive connectors are prepared by direct bonding of the conductive pillars and the interconnection pads. In this case, the chip body is electrically connected to the rewiring structure through the chip built-in pads, the conductive columns, and the interconnection pads in sequence.

Referring to FIG. 5, an underfill adhesive layer 40 is formed between the chip body 20 and the rewiring structure 10, and the underfill adhesive layer 40 wraps the sidewalls of the conductive connectors 30; in the rewiring structure One side of 10 forms a plastic encapsulation layer 50 wrapping the chip body 20 , and the plastic encapsulation layer 50 also wraps the underfill adhesive layer 40 .

The underfill adhesive layer 40 is filled on the surface of the redistribution structure 10 facing the chip body 20 to wrap the conductive connector 30 and the active surface of the chip body 20 .

The forming process of the underfill glue layer 40 includes: forming an underfill glue solution between the chip body 20 and the rewiring structure 10, and filling the underfill glue solution into the rewiring structure 10 and the chip body 20 by capillary phenomenon. Afterwards, the underfill glue solution is cured to form the underfill glue layer 40 in the gap between them. The underfill adhesive layer 40 is used to protect the conductive connector 30 , reduce the thermal stress of the solder layer 303 in subsequent processes or tests involving heat treatment and increase the fatigue life of the solder layer 303 .

In some embodiments, the material of the underfill liquid includes capillary underfill (CUF) or molded underfill (MUF).

In other embodiments, the underfill adhesive layer 40 uses NCF (Non-Conductive Film) to encapsulate the conductive connector 30 .

After the plastic encapsulation layer 50 is formed, the chip body 20 and the underfill adhesive layer 40 are all wrapped by the plastic encapsulation layer 50 to realize the isolation of the chip body 20 from the external environment, thereby realizing the protection of the chip body 20 and reducing the impact of external environmental factors on the chip body. 20 impact.

Referring to FIG. 6 , after the molding layer 50 is formed, the temporary carrier C1 and the stacked metal layer M are debonded.

Specifically, the ultraviolet light is used to irradiate the interface between the temporary carrier C1 and the rewiring structure 10, and the ultraviolet light reacts photochemically with the temporary bonding adhesive layer F1 to break the chemical bonds of the materials in the temporary bonding adhesive layer F1, thereby realizing temporary loading. The board C1 is separated from the laminated metal layer M, and the debonding of the temporary carrier C1 and the laminated metal layer M is completed.

Debond the temporary carrier C1 and the laminated metal layer M. During the debonding, the temporary bonding adhesive layer F1 may have insufficient debonding, resulting in residual glue that will destroy the stack as the temporary carrier C1 is peeled off. The physical structure of the metal layer M in turn affects the structural integrity of the signal or power transmission path. Therefore, the stacked metal layer M needs to be removed.

Referring to FIG. 7 , after debonding the temporary carrier C1 and the laminated metal layer M, the laminated metal layer M is removed by a wet etching process, and the dielectric layer 10b in the redistribution structure 10 is exposed. .

The step of removing the laminated metal layer by using a wet etching process includes: sequentially removing the first metal layer to the Wth metal layer; the step of removing any wth metal layer is: using the wth wet etching solution to remove the wth metal layer, w is an integer greater than or equal to 1 and less than or equal to W.

An etching tank T1 is provided, and in the step of removing the wth metal layer by using the wth wet etching solution, the wth wet etching solution is placed in the etching tank T1.

In this embodiment, the step of removing the stacked metal layer M by using a wet etching process includes: using a first wet etching solution to remove the first metal layer; after using the first wet etching solution to remove the first metal layer, using The second wet etching solution removes the second metal layer; after the second wet etching solution is used to remove the second metal layer, the third wet etching solution is used to remove the third metal layer, the first wet etching solution, the second wet etching solution The etching solution and the third wet etching solution are different.

When the material of the first metal layer m1 is Al, the first wet etching solution is a mixed solution of phosphoric acid and nitric acid. In the step of removing the first metal layer by using the first wet etching solution, Al atoms dissolve in the first wet etching solution to form Al ions, and some Al ions remain on the surface of the second metal layer m2.

When the material of the second metal layer m2 is Ti, the second wet etching solution is a mixed solution of hydrogen peroxide and potassium hydroxide. In the step of using the second wet etching solution to remove the second metal layer, Ti atoms are dissolved in the second wet etching solution to form Ti4 ^+-based complexes, and the Al ions remaining on the surface of the second metal layer will also be Dissolved in the second wet etching solution, so Al ions and Ti ⁴⁺ -based complexes will remain on the surface of the third metal layer.

When the material of the third metal layer m3 is Cu, the third wet etching solution is a mixed solution of hydrogen peroxide and phosphoric acid. In the step of using the third wet etching solution to remove the third metal layer, Cu atoms dissolve in the third wet etching solution to form Cu ions, and the remaining Al ions and Ti ⁴⁺ based complexes on the surface of the third metal layer also It will then be dissolved in the third wet etching solution, so there will be Al ions, Ti ⁴⁺ -based complexes and Cu ions embedded on the surface of the dielectric layer 10b at the same time.

It should be noted that although Al ions, Ti ⁴⁺ -based complexes and Cu ions will also remain on the surface of the first conductive layer, given that Al ions, Ti ⁴⁺ -based complexes and Cu ions are all conductive , so it does not affect the electron transmission and power signal transmission of the conductive layer in the rewiring structure 10 .

Referring to FIG. 8 , after the stacked metal layer M is removed by a wet etching process, a partial thickness of the dielectric layer 10 b is removed from the side of the rewiring structure 10 away from the chip body 20 by a dry etching process.

The dry etching process is a plasma dry etching process.

The material of the dielectric layer 10b includes epoxy resin. The plasma dry etching process uses oxygen plasma.

In some embodiments, the thickness of the dielectric layer 10 b removed from the side of the rewiring structure 10 away from the chip body 20 by dry etching process is 0.1 μm˜5 μm.

In some embodiments, the thickness of the dielectric layer 10 b removed from the side of the rewiring structure 10 away from the chip body 20 by dry etching process is 0.2 micron to 1 micron.

In some embodiments, after removing a partial thickness of the dielectric layer 10b from the side of the rewiring structure 10 away from the chip body 20 by using a dry etching process, and before forming the seed layer subsequently, the The concentration of metal ions on the surface of the dielectric layer 10b away from the plastic encapsulation layer 50 is less than or equal to 10ppm, such as 10ppm, 8ppm, 6ppm, 4ppm or 2ppm, so that the dielectric layer on the side of the rewiring structure 10 away from the chip body 20 The concentration of metal ions on the surface of the layer 10b is very small, which further improves the reliability of the chip packaging structure.

In some embodiments, the concentration of metal ions on the surface of the medium layer away from the plastic sealing layer is detected by using a metal ion detection machine, and the concentration of metal ions on the surface of the medium layer away from the plastic sealing layer is The concentration is lower than the test lower limit concentration of the metal ion detection machine.

While using a dry etching process to remove a partial thickness of the dielectric layer 10b from the side of the rewiring structure 10 away from the chip body 20, the metal ions and metal complexes embedded in the surface of the dielectric layer 10b are also dry-processed. During the etching process, it becomes gaseous and is cleaned and removed by the exhaust system of the dry etching machine, so that the concentration of metal ions on the surface of the dielectric layer 10b is extremely low.

It should be noted that since most of the materials used to prepare the dielectric layer 10b are epoxy resin systems, oxygen plasma can be used to bombard the surface of the dielectric layer 10b; when the dielectric layer 10b uses other resin systems, the dielectric layer 10b can be The corresponding plasma components that can react with the dielectric layer 10b are selected.

FIG. 9 is a schematic diagram after a partial thickness of the dielectric layer 10 b is removed from the side of the rewiring structure 10 away from the chip body 20 by using a dry etching process.

Referring to FIG. 10 and FIG. 11 , after removing a partial thickness of the dielectric layer 10b from the side of the rewiring structure 10 away from the chip body 20 using a dry etching process, after the rewiring structure 10 is away from the chip body 20 One side surface of the 20 is prepared with an external body 60.

The step of forming the external body 60 includes: referring to FIG. 10 , forming a seed layer 61 on the side of the rewiring structure 10 away from the chip body 20 , referring to FIG. 11 , forming a part of the seed layer 61 away from the One surface of the redistribution structure 10 forms an electrical terminal layer.

The deposition process of the seed layer 61 includes a physical vapor deposition process, such as a magnetron sputtering process.

The seed layer is a single-layer structure or a multi-layer structure; when the seed layer 61 is a multi-layer structure, the method for forming the seed layer 61 includes: placing the rewiring structure 10 away from the chip body The first sub-seed layer to the Gth sub-seed layer are sequentially formed on one side of 20, and G is an integer greater than or equal to 2. The G-th sub-seed layer provides nucleation points for the subsequent plating process of the first sub-terminal layer, so the G-th sub-seed layer uses the same conductive metal material as the first sub-terminal layer.

In some embodiments, G is equal to 2, and the seed layer 61 includes a first sub-seed layer 611 and a second sub-seed layer 612 . Wherein, the first sub-seed layer 611 includes titanium or a titanium-based alloy, and the second sub-seed layer 612 provides nucleation points for the plating process of the subsequent first sub-terminal layer, so the second sub-seed layer 612 adopts the same method as the first sub-seed layer. A sub-terminal layer of the same conductive metal material. Preferably, the material of the second sub-seed layer 612 includes copper.

The first sub-seed layer 611 is used to have better bonding force with the rewiring structure 10 .

In some embodiments, the material costs of the second to Gth sub-seed layers are all less than the material costs of the first sub-seed layer.

In this embodiment, before forming the electrical terminal layer, a photoresist layer with patterned openings is formed on the surface of part of the seed layer 61 away from the rewiring structure 10; 61 The step of forming an electrical terminal layer on the surface of the side away from the rewiring structure 10 is: forming an electrical terminal layer in the patterned opening; after forming the electrical terminal layer in the patterned opening, removing the electrical terminal layer The photoresist layer; after the photoresist layer is removed, and before the subsequent formation of the sacrificial bonding initial protection layer, reflow soldering is performed on the electrical terminal layer. The process of forming the electrical terminal layer in the patterned opening includes an electroplating process or an electroless plating process.

In some embodiments, the method for forming the electrical terminal layer includes: sequentially forming stacked first sub-terminal layers to Nth sub-terminal layers on the surface of a part of the seed layer 61 facing away from the rewiring structure 10 , N is an integer greater than or equal to 2; when the seed layer is a single-layer structure, the material of the seed layer is the same as that of the first sub-terminal layer; when the seed layer 61 is a multilayer In the structure, the material of the G-th sub-seed layer is the same as that of the first sub-terminal layer.

In some embodiments, N is equal to 3, and the method for forming the electrical terminal layer includes: sequentially forming a laminated first sub-terminal layer 62 and a second sub-terminal layer on the surface of a part of the seed layer 61 away from the rewiring structure 10 The second sub-terminal layer 63 and the third sub-terminal layer 64 . The material of the first sub-terminal layer 62 is Cu, the material of the second sub-terminal layer 63 is Ni, and the material of the third sub-terminal layer 64 is a Sn-based alloy.

The material of the first sub-terminal layer 62 is the same as that of the Gth sub-seed layer, so that the plating thickness of the first sub-terminal layer can be reduced.

In some embodiments, the material of the second sub-terminal layer 63 is nickel with a higher modulus of elasticity, so that the second sub-terminal layer 63 has a higher shape retention capability during the reflow process of the electrical terminal layer. Well, avoid the collapse and deformation of the electrical terminal layer during the reflow process.

In some embodiments, the material of the third sub-terminal layer 64 is tin or a tin-based alloy, so that the surface of the third sub-terminal layer 64 away from the rewiring structure 10 is protruding, and the subsequent electrical terminal layer and other substrates During soldering, it is beneficial for the third sub-terminal layer 64 to melt at a relatively low soldering temperature and form a soldering interconnection with other substrates.

In other embodiments, the material of the first sub-terminal layer is different from that of the Gth sub-seed layer.

In this embodiment, it further includes: before forming the sacrificial bonding protection layer f1 , removing the seed layer 61 not covered by the electrical terminal layer.

Referring to FIG. 11 , on the side of the seed layer 61 facing away from the rewiring structure 10 , a sacrificial glue protection layer f1 wrapping the electrical terminal layer is formed.

The sacrificial glue protection layer f1 wraps and covers the electrical terminal layer to prevent the electrical terminal layer from being bumped by external force.

The step of forming a sacrificial adhesive protection layer f1 covering the electrical terminal layer on the side of the seed layer 61 away from the rewiring structure 10 includes: on the side of the seed layer 61 away from the rewiring structure 10 A sacrificial adhesive initial protection layer wrapping the electrical terminal layer 51 is formed on one side; the sacrificial adhesive initial protective layer is cured by light, so that the sacrificial adhesive initial protective layer forms a sacrificial adhesive protective layer f1.

The sacrificial glued initial protective layer is cured by light, so that the sacrificial glued initial protective layer forms a sacrificial glued protective layer f1, which improves the elastic modulus of the sacrificial glued protective layer f1, which is beneficial to the encapsulation machine in the subsequent encapsulation process. The sacrificial glue protection layer f1 is used to achieve a solid mechanical support for the package structure. At the same time, the adhesive force between the cured sacrificial adhesive protection layer f1 and the seed layer 61 is greatly reduced, which is also conducive to the peeling of the sacrificial adhesive protection layer f1 from the seed layer 61 .

Referring to FIG. 12 , after forming the sacrificial glue protection layer f1, the surface of the plastic encapsulation layer 50 facing away from the rewiring structure 10 is ground until the passive surface of the chip body 20 is exposed; The adhesive protection layer f1 is peeled off from the electrical terminal layer and the seed layer 61 .

In this embodiment, it also includes: forming a heat conduction layer (not shown) on the surface of the plastic encapsulation layer and the chip body away from the rewiring structure; Peel off from the electrical terminal layer and the seed layer 61 . In other embodiments, after the sacrificial adhesive protection layer f1 is peeled off from the electrical terminal layer and the seed layer 61, the surface on the side of the plastic encapsulation layer and the chip body away from the rewiring structure Form a thermally conductive layer.

In other embodiments, after the sacrificial glue protection layer f1 is peeled off from the electrical terminal layer and the seed layer 61 , the seed layer 61 not covered by the electrical terminal layer is removed.

It should be noted that metal ions in this application include: metal atoms without valence electrons, metal ions with valence electrons, and metal complexes composed of metal atoms or ions.

Apparently, the above-mentioned embodiments are only examples for clear description, rather than limiting the implementation. For those of ordinary skill in the art, other changes or changes in different forms can be made on the basis of the above description. It is not necessary and impossible to exhaustively list all the implementation manners here. And the obvious changes or changes derived therefrom are still within the scope of protection of the present invention.

Claims (13)

1. A preparation method for a chip packaging structure, characterized in that, comprising: Provide temporary carrier board; forming a laminated metal layer on the temporary carrier; forming a rewiring structure on the surface of the laminated metal layer away from the temporary carrier; A chip body is provided on a side of the rewiring structure away from the laminated metal layer; forming a conductive connection between the chip body and the rewiring structure; forming an underfill adhesive layer encapsulating the conductive connector; forming a plastic encapsulation layer wrapping the chip body on one side of the rewiring structure; After forming the molding layer, debonding the temporary carrier and the stacked metal layer; After debonding the temporary carrier and the stacked metal layer, using a wet etching process to remove the stacked metal layer and expose the dielectric layer in the rewiring structure; After the stacked metal layer is removed by wet etching, a part of the thickness of the dielectric layer is removed from the side of the rewiring structure away from the chip body by using a dry etching process, so as to reduce the deviation of the rewiring structure from the chip The concentration of metal ions on the surface of the dielectric layer on one side of the body. 2. The method for manufacturing a chip package structure according to claim 1, wherein the step of forming a stacked metal layer on the temporary carrier comprises: sequentially forming stacked first metal layers on the temporary carrier layer to the Wth metal layer, W is an integer greater than or equal to 2; the step of removing the laminated metal layer using a wet etching process includes: sequentially removing the first metal layer to the Wth metal layer; removing any wth metal layer The step of layering is: using the wth wet etching solution to remove the wth metal layer, where w is an integer greater than or equal to 1 and less than or equal to W. 3. The method for manufacturing a chip package structure according to claim 2, wherein the step of forming a stacked metal layer on the temporary carrier comprises: sequentially forming stacked first metal layers on the temporary carrier layer, the second metal layer and the third metal layer, the materials of the first metal layer, the second metal layer and the third metal layer are different; the step of removing the laminated metal layer by wet etching process includes: using the first metal layer A wet etching solution to remove the first metal layer; after the first wet etching solution is used to remove the first metal layer, a second wet etching solution is used to remove the second metal layer; a second wet etching solution is used to remove the second metal layer After that, the third metal layer is removed by using a third wet etching solution, the first wet etching solution, the second wet etching solution and the third wet etching solution are different. 4. The method for preparing a chip packaging structure according to claim 3, wherein the material of the first metal layer is Al, the material of the second metal layer is Ti or a titanium-based alloy, and the third The material of the metal layer is Cu. 5. The method for preparing a chip packaging structure according to claim 3 or 4, wherein the thickness of the first metal layer is 0.1 micron to 1 micron; the thickness of the second metal layer is 0.1 micron to 1 micron. micron; the thickness of the third metal layer is 0.1 micron to 1 micron. 6. The preparation method of the chip packaging structure according to claim 1, wherein the material of the dielectric layer comprises epoxy resin; the dry etching process is a plasma dry etching process, and the plasma The bulk dry etching process uses oxygen plasma. 7. The method for preparing a chip packaging structure according to claim 1, wherein the thickness of the dielectric layer removed from the side of the rewiring structure away from the chip body by using a dry etching process is 0.1 micron~ 5 microns. 8. The method for preparing a chip packaging structure according to claim 7, wherein the thickness of the dielectric layer removed from the side of the rewiring structure away from the chip body by using a dry etching process is 0.2 microns~ 1 micron. 9. The method for preparing a chip package structure according to claim 1, further comprising: after removing a partial thickness of the dielectric layer from the side of the rewiring structure away from the chip body by using a dry etching process A seed layer is formed on a surface of the rewiring structure away from the chip body; an electrical terminal layer is formed on a part of the surface of the seed layer away from the rewiring structure. 10. The method for preparing a chip package structure according to claim 9, wherein a dry etching process is used to remove a partial thickness of the dielectric layer from the side of the rewiring structure away from the chip body and after Before forming the seed layer, the concentration of metal ions on the surface of the dielectric layer away from the plastic encapsulation layer is less than or equal to 10 ppm. 11. The method for preparing a chip packaging structure according to claim 9, further comprising: forming a sacrificial bonding protection covering the electrical terminal layer on the side of the seed layer away from the rewiring structure layer; after forming the sacrificial glue protection layer, grind the surface of the plastic sealing layer away from the rewiring structure until the passive surface of the chip body is exposed; when the plastic sealing layer and the chip body are away from the rewiring structure A heat conduction layer is formed on one side surface of the wiring structure; after forming the heat conduction layer, the sacrificial adhesive protection layer is peeled off from the electrical terminal layer and the seed crystal layer. 12. The method for preparing a chip packaging structure according to claim 11, wherein the electrical terminal is removed after the sacrificial adhesive protective layer is peeled off from the electrical terminal layer and the seed layer. layer not covering the seed layer; or, before forming the sacrificial glue protection layer, removing the seed layer not covering the electrical terminal layer. 13. The method for preparing a chip packaging structure according to claim 9, wherein the seed crystal layer is a single-layer structure or a multi-layer structure; when the seed crystal layer is a multi-layer structure, the seed crystal layer The layer forming method includes: sequentially forming stacked first sub-seed layer to G-th sub-seed layer on the side of the rewiring structure away from the chip body, where G is an integer greater than or equal to 2; forming the The method for the electrical terminal layer includes: sequentially forming stacked first sub-terminal layers to Nth sub-terminal layers on the surface of a part of the seed layer facing away from the rewiring structure, where N is an integer greater than or equal to 2; When the seed crystal layer is a single-layer structure, the material of the seed crystal layer is the same as that of the first sub-terminal layer; when the seed crystal layer is a multi-layer structure, the G sub-seed layer The material is the same as that of the first sub-terminal layer.