CN104851816A - Method for packaging multiple chips in high density - Google Patents

Abstract

The invention discloses a multi-chip high-density packaging method, which comprises the following steps: 1) using a silicon wafer as a substrate material, and processing multi-layer metal interconnections, metal pads and insulating layers on the surface; Chips are mounted at the wafer level, and wafer-level plastic packaging is performed on the mounting surface of the silicon wafer on which the chip is attached; 3) all substrate materials of the silicon wafer are removed until multiple layers are exposed. The insulating layer under the metal interconnection; 4) patterning the insulating layer under the multilayer metal interconnection, exposing the bottom metal of the multilayer metal interconnection; 5) processing metal solder balls on the back side, the metal Solder balls form an electrical connection with the bottom metal of the multilayer metal interconnection; 6) cutting the wafer after the wafer-level process to obtain discrete packages or integrated devices. The above multi-chip high-density packaging method has the advantages of high integration density, convenient processing, low cost and low high-frequency loss.

Description

A multi-chip high-density packaging method

technical field

The invention belongs to the technical field of electronic packaging, in particular to a multi-chip high-density packaging method.

Background technique

At present, the existing multi-chip high-density packaging methods have some limitations or problems:

1) Flip chip packaging (Flip chip), in order to achieve high density, it is necessary to process high-density packaging substrates. On the one hand, it is difficult to process thin line width and fine spacing, and on the other hand, the packaging substrate is easy to warp, and high-density assembly is difficult;

2) Fan-out wafer level packaging (Fan-out), wiring processing is performed on the front of the chip after plastic packaging, due to substrate warping and alignment deviation, thin line width, multi-layer redistribution layer (RDL) processing is difficult;

3) 2.5D packaging requires the use of TSV (Through Silicon Vias, through-silicon vias), the process is complex, the cost is high, and TSV is transmitted in the silicon substrate, there is substrate loss, which is not conducive to high-frequency applications.

Contents of the invention

The purpose of the present invention is to provide a multi-chip high-density packaging method, which has the characteristics of high integration density, convenient processing, low cost and low high-frequency loss, so as to solve the above-mentioned problems existing in the multi-chip high-density packaging in the prior art.

For reaching this purpose, the present invention adopts following technical scheme:

A multi-chip high-density packaging method, comprising the following steps:

1) Using a silicon wafer as the substrate material, processing multilayer metal interconnections and metal pads on the surface of the silicon wafer, including a layer of insulating material between the multilayer metal and the silicon substrate;

2) Mount multi-chips in the form of wafer level, mount at least 2 chips in each integrated area, and perform wafer-level plastic packaging on the mounting surface of the silicon wafer with chips attached, and place the mounted Chips are covered in injection molding material;

3) removing all the substrate material of the silicon wafer until the insulating material under the multilayer metal interconnection is exposed;

4) patterning the insulating material under the multilayer metal interconnection to form an insulating layer window, exposing the bottom metal of the multilayer metal interconnection in the window;

5) processing metal solder balls on the back side, the metal solder balls are electrically connected to the bottom metal of the multi-layer metal interconnection through the insulating layer window;

6) Cutting the wafer that has completed the wafer-level process to obtain discrete packages or integrated devices.

In particular, discrete integrated devices are obtained after wafer dicing in step 6), and the discrete integrated devices are further assembled on an organic substrate in a flip-chip manner to finally form a package.

In particular, the method of mounting the multi-chips at the wafer level in the step 2) adopts any one of thermocompression bonding based on solder bumps or direct metal bonding.

In particular, in the step 2), the multi-chips are mounted in the form of wafer-level thermocompression bonding, and after the thermocompression bonding of the multi-chips, the underfill resin is filled and cured in areas other than the solder joints, To improve the reliability of solder joints.

In particular, after the wafer-level molding treatment is performed on the mounting surface of the silicon wafer in the step 2), it also includes planarizing the surface of the molding material to form a flat upper surface.

In particular, in the step 3), the substrate material of the silicon wafer is completely removed. The specific removal method is: reduce the silicon thickness of the substrate to less than 50um by grinding, and then perform surface polishing treatment. It may be any one of dry polishing or chemical mechanical polishing, and then adopt wet etching or dry etching to remove all remaining thin silicon layers.

In particular, in the step 4), the insulating material under the multilayer metal interconnection is patterned, the insulating material is silicon oxide material, photoresist is used as a mask, and dry etching or wet etching is used. Silicon oxide is patterned.

In particular, in the step 5), the metal solder balls are processed on the back surface by any one of electroplating, ball planting or printing.

The beneficial effect of the present invention is that, compared with the prior art, the multi-chip high-density packaging method is based on silicon-based technology, multi-layer wiring processing is performed, and the integration density is improved; moreover, TSV technology is not used, and the cost has a great advantage, and high The frequency loss is smaller.

Description of drawings

1 is a cross-sectional view of processing multi-layer high-density wiring and pads on a silicon base in the multi-chip high-density packaging method provided by Embodiment 1 of the present invention;

Fig. 2 is the cross-sectional view of processing micro-bumps on the chip to be packaged in the multi-chip high-density packaging method provided by Embodiment 1 of the present invention;

FIG. 3 is a schematic diagram of wafer-level chip mounting of the multi-chip high-density packaging method provided in Embodiment 1 of the present invention;

Fig. 4 is a cross-sectional view of a single integrated area chip mounted in the multi-chip high-density packaging method provided in Embodiment 1 of the present invention;

Fig. 5 is a cross-sectional view of a single integrated area of the multi-chip high-density packaging method provided in Embodiment 1 of the present invention after chip mounting and injection molding encapsulation;

6 is a cross-sectional view of the multi-chip high-density packaging method provided in Embodiment 1 of the present invention after all silicon substrates are removed;

7 is a cross-sectional view of the multi-chip high-density packaging method provided in Embodiment 1 of the present invention after patterning the insulating material;

8 is a cross-sectional view of the multi-chip high-density packaging method provided in Embodiment 1 of the present invention after processing metal solder balls and making electrical connections between the metal solder balls and the bottom metal of the multi-layer gold interconnection.

Detailed ways

The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings and through specific implementation methods.

Please refer to Figures 1 to 8, in this embodiment, a multi-chip high-density packaging method, which includes the following steps:

1) Using a silicon wafer as the substrate material, process multi-layer metal interconnections and metal pads on the surface of the silicon wafer, and include a layer of insulating material between the multi-layer metal and the silicon substrate; due to the use of silicon-based technology , there are many options, you can use the back-end (BEOL) process of the foundry to achieve high-density interconnection processing, or you can use the wafer-level interconnection process of the packaging plant, that is, the semi-additive plating process , to achieve medium density interconnection processing. As shown in Figure 1, an insulating layer 11 is made on the surface of a silicon substrate 10 and multilayer metal wiring 12 is processed, and an intermetal dielectric layer 13 is arranged between the multilayer metal wiring 12, and is processed for chip micro-bumps Solder pad 14. More specifically, the insulating layer 11 is made of silicon oxide with a thickness of 200nm-2um, preferably a silicon oxide layer of 1um. In a specific embodiment, the multi-layer metal wiring 12 is obtained by Damascene copper process, and the inter-metal dielectric layer 13 is a combination of silicon oxide, silicon nitride, and silicon oxynitride. In another specific embodiment, the multilayer metal wiring 12 is processed by a wafer-level packaging interconnection process, that is, semi-additive electroplating, and the inter-metal dielectric layer 13 is a polymer layer. The pad 14 adopts a stacked structure of multiple metals. In a typical embodiment, the pad 14 is stacked with copper/nickel/gold. A typical thickness combination is copper 5um, nickel 1um, and gold 0.5um. In another typical In the embodiment, 14 adopts a copper/tin combination, and a typical thickness combination is copper 10um and tin 5um.

2) Mount multi-chips in the form of wafer level, mount at least 2 chips in each integrated area, and perform wafer-level plastic packaging on the mounting surface of the silicon wafer with chips attached, and place the mounted The chips are all covered in the injection molding material 16 ; as shown in FIG. 2 to FIG. 5 , in this embodiment, two chips are placed in each integrated area, namely the first chip 100 and the second chip 200 . The first chip 100 includes a substrate 101 , a device and internal interconnection layer 102 , a surface passivation layer 103 , and surface micro-bumps 104 . The substrate 101 is a material suitable for processing electronic integrated circuits such as silicon, gallium arsenide, gallium nitride, and silicon germanium. The surface micro-bumps 104 are typically made of a combination of copper/nickel/tin materials, with a typical thickness of Copper 10um, nickel 1um, tin 15um. The second chip 200 includes a substrate 201 , a device and internal interconnection layer 202 , a surface passivation layer 203 , and surface micro-bumps 204 . The substrate 201 is a material suitable for processing electronic integrated circuits such as silicon, gallium arsenide, gallium nitride, and silicon germanium. The surface micro-bumps 204 typically use a combination of copper/nickel/tin materials, with a typical thickness of Copper 10um, nickel 1um, tin 15um. After welding, the micro-bumps on the surface of the first chip 100 and the second chip 200 are combined with the pads on the surface of the silicon substrate 10 to form a welding interface 15. After welding, in order to improve the reliability of the solder joints, outside the solder joints The area is filled with underfill resin (not shown in the figure). Using wafer-level plastic packaging, the mounted first chip 100 and the second chip 200 are both covered in the injection molding material 16, and the first chip 100 and the second chip 200 are fixed on the silicon substrate 10, And through planarization treatment, a flat upper surface is formed.

3) Remove all of the silicon substrate 10 until the insulating layer 11 under the multilayer metal interconnection is exposed; as shown in FIG. The grinding method reduces the thickness of the silicon substrate 10 to less than 50um, and then performs surface polishing treatment. The polishing method can be dry polishing or chemical mechanical polishing (CMP), and then wet etching or dry etching is used to remove the remaining The thin layer of silicon is completely removed. The insulating layer 11 can be used as a stop layer during the wet etching or dry etching process of the substrate, which can ensure that the substrate silicon can be completely removed by etching even if there is a difference in the distribution of etching or etching in the chip.

4) Patterning the insulating layer 11 below the multilayer metal interconnection to form an insulating layer window, exposing the bottom metal of the multilayer metal interconnection in the window; as shown in Figure 7, using photoresist as A mask is used to pattern the insulating layer 11 by dry etching or wet etching. Typically, fluorine-based gases such as carbon tetrafluoride and sulfur hexafluoride are used for dry etching, and hydrofluoric acid corrosion inhibitor (BHF) is used for wet etching.

5) Process metal solder balls 17 on the back side, and the metal solder balls 17 form an electrical connection with the bottom metal of the multi-layer metal interconnection through the window of the insulating layer 11; the wafers that have completed the wafer-level process are cut to obtain discrete package or integrated device. As shown in FIG. 8 , metal solder balls 17 are processed on the back surface, and the processing method can be electroplating, ball planting or printing. In one embodiment, the typical diameter of the metal solder balls 17 is 200-300um, and the typical pitch is 0.35-0.5mm. The metal solder balls 17 can be used for surface mount (SMT) directly facing the PCB board, and the wafer is thus completed. Level packaging, after cutting, the packaged product can be obtained. In another embodiment, the typical diameter of the metal solder ball 17 is 60-100um, and the typical pitch is 100-200um. The metal solder ball 17 is used for welding to the organic substrate, and the integrated device is flip-chip (FlipChip) Carry out secondary assembly, and finally form a packaged product.

The above embodiments have only set forth the basic principles and characteristics of the present invention, the present invention is not limited by the above-mentioned examples, and on the premise of not departing from the spirit and scope of the present invention, the present invention also has various changes and changes, and these changes and changes all fall within the scope of the claimed invention. The protection scope of the present invention is defined by the appended claims and their equivalents.

Claims (8)

1. A multi-chip high-density packaging method is characterized in that it comprises the following steps: 1) Using a silicon wafer as the substrate material, processing multilayer metal interconnections and metal pads on the surface of the silicon wafer, including a layer of insulating material between the multilayer metal and the silicon substrate; 2) Mount multi-chips in the form of wafer level, mount at least 2 chips in each integrated area, and perform wafer-level plastic packaging on the mounting surface of the silicon wafer with chips attached, and place the mounted Chips are covered in injection molding material; 3) removing all the substrate material of the silicon wafer until the insulating material under the multilayer metal interconnection is exposed; 4) patterning the insulating material under the multilayer metal interconnection to form an insulating layer window, exposing the bottom metal of the multilayer metal interconnection in the window; 5) processing metal solder balls on the back side, the metal solder balls are electrically connected to the bottom metal of the multi-layer metal interconnection through the insulating layer window; 6) Cutting the wafer that has completed the wafer-level process to obtain discrete packages or integrated devices. 2. The multi-chip high-density packaging method according to claim 1, characterized in that, after the wafer cutting in the step 6) is completed, discrete integrated devices are obtained, and the discrete integrated devices are flip-chip The form is further assembled on an organic substrate to finally form a package. 3. The multi-chip high-density packaging method according to claim 1 or 2, characterized in that, in said step 2), the method of mounting multi-chips in the form of wafer level adopts thermal pressing based on solder bumps Either of the bonding method or the metal direct bonding method. 4. The multi-chip high-density packaging method according to claim 3, characterized in that, in the step 2), the multi-chips are mounted in the form of wafer-level thermocompression bonding, and the multi-chip thermocompression bonding After bonding, the underfill resin is filled and cured in areas other than the solder joints to improve the reliability of the solder joints. 5. The multi-chip high-density packaging method according to claim 1 or 2, characterized in that, in the step 2), after the wafer-level plastic packaging process is carried out on the mounting surface of the silicon wafer, the surface of the plastic packaging material is also included Planarization is performed to form a flat upper surface. 6. The multi-chip high-density packaging method according to claim 1 or 2, characterized in that, in the step 3), the substrate material of the silicon wafer is completely removed, and the specific removal method is: use a grinding method to reduce the silicon thickness of the substrate to less than 50um, and then perform surface polishing. The polishing method can be either dry polishing or chemical mechanical polishing, and then wet etching or dry etching is used to remove the remaining thin layer. Silicon is completely removed. 7. The multi-chip high-density packaging method according to claim 1 or 2, characterized in that, in the step 4), the insulating material under the multilayer metal interconnection is patterned, and the insulating material is a silicon oxide material, The photoresist is used as a mask, and the silicon oxide is patterned by dry etching or wet etching. 8. The multi-chip high-density packaging method according to claim 1 or 2, characterized in that, in the step 5), processing metal solder balls on the back surface is carried out by any one of electroplating, ball planting or printing.