CN116111816B

CN116111816B - High efficiency gate drive circuit

Info

Publication number: CN116111816B
Application number: CN202310144528.5A
Authority: CN
Inventors: 陈珍海
Original assignee: Jiangsu Zhongkehanyun Semiconductor Co ltd
Current assignee: Jiangsu Zhongkehanyun Semiconductor Co ltd
Priority date: 2023-02-21
Filing date: 2023-02-21
Publication date: 2025-06-27
Anticipated expiration: 2043-02-21
Also published as: CN116111816A

Abstract

The present invention discloses a high-efficiency gate drive circuit for driving a power switch SiC MOSFET. The circuit includes: an input receiving circuit, a high-voltage bandgap reference, an internal power generation circuit, a high-efficiency output drive circuit, an overcurrent protection circuit, an overtemperature protection circuit, an undervoltage protection circuit, an oscillator OSC, a waveform modulation circuit, a control logic and an error amplifier. It also includes 5 external pins, namely: a chip power pin VDD, an external input pulse pin INX, a current detection pin CS, an output drive switch pin VO, and a ground pin GND. The high-efficiency gate drive provided by the present invention improves the overall chip function reliability by adopting a variety of chip abnormal state monitoring protection circuits; the present invention also adopts a high-output efficiency output drive circuit, which adaptively identifies the load size and the frequency of the input control pulse, and adaptively adjusts in real time to provide the optimal output drive current, thereby achieving the goal of improving efficiency.

Description

High efficiency gate drive circuit

Technical Field

The invention relates to a high-efficiency gate driving circuit for a power device in a switching power supply, and belongs to the technical field of integrated circuits.

Background

In recent years, various portable electronic products are layered endlessly, and the corresponding power consumption of the power supply is also larger and larger, so that new requirements are put forward on the conversion efficiency and the power consumption of the power supply. The early power supply is mainly powered by using a linear power supply, the linear power supply is simple in structure, good in stability and better in noise resistance, but when the linear voltage-stabilizing power supply works, the adjusting tube can generate a large amount of heat, so that the efficiency is low, the loss is serious, larger cooling fins are needed to be matched with the periphery of the adjusting tube for eliminating the generated heat, the linear voltage-stabilizing power supply generally needs to use an industrial frequency transformer, and the cooling fins of the adjusting tube are added, so that the linear voltage-stabilizing power supply is huge in size, low in power efficiency and generally capable of reaching 50% at most. For small and portable electronic products, linear power supplies cannot meet the power supply requirements, so that people gradually start to research on switching power supplies to meet new power supply requirements. The switching power supply has the greatest advantages of higher conversion efficiency, smaller volume and lighter weight, thereby reducing cost, providing convenience for charging small-sized equipment, and ensuring the safety of using electronic products by various open-circuit/short-circuit/over-temperature overvoltage protection functions. Compared with a linear power supply working in a linear state, the switching power supply controls output voltage through the on and off of a power switching tube.

Common power devices include Bipolar Junction Transistors (BJTs), insulated Gate Bipolar Transistors (IGBTs), metal-oxide semiconductor field effect transistors (MOSFETs), and Junction Field Effect Transistors (JFETs). Si IGBTs are used as the main power devices in switching power converters, the technology tends to be mature, but the performance of Si IGBTs gradually approaches the theoretical limit of Si materials, and power devices with better performance are sought. With the rise of wide band gap semiconductor devices, siC MOSFETs have the potential to replace Si IGBTs in the power electronics field by virtue of their high frequency, high voltage, high temperature resistance, strong heat dissipation capability, etc. In order to improve the efficiency of the switching power supply, the loss of the power switching device is not negligible, and therefore, the gate driving circuit thereof needs to be optimized.

In practical application, the pulse control signal required by the SiC MOSFET switch tube is a 15V-25V high current signal, and in order to prevent the gate output driving current from damaging the gate terminal of the external power switch SiC MOSFET to be driven, a resistor is usually connected in series to the output terminal of the gate driving circuit to inhibit the voltage overshoot effect of the gate terminal. When the equivalent capacitance of the gate terminal is larger, the series protection resistance needs to be smaller, otherwise, the series protection resistance needs to be larger. The relatively large series protection resistor can bring 2 problems, namely, the switching loss on the resistor is increased, the efficiency of the driving circuit is reduced, the driving delay is increased, and finally, the switching frequency of the system is reduced. In addition, the use of the series protection resistor increases the design workload of the design engineer and reduces the reliability of the overall system.

Disclosure of Invention

The invention provides a high-efficiency gate driving circuit with self-adaptive driving capability, which can adaptively adjust the output driving current by adaptively identifying the load size and the frequency of input control pulse.

The invention provides a high-efficiency gate driving circuit which structurally comprises an input receiving circuit, a high-voltage band gap reference, an internal power supply generating circuit, a high-efficiency output driving circuit, an overcurrent protection circuit, an overtemperature protection circuit, an undervoltage protection circuit, an oscillator, a waveform modulation circuit, a control logic and an error amplifier, and also comprises 5 external pins, namely a chip power supply pin VDD, an external input pulse pin INX, a current detection pin CS, an output driving switch pin VO and a ground pin GND;

The input end of the input receiving circuit is connected with an external input pulse pin INX, the output end of the input receiving circuit is connected with the input end of the waveform modulation circuit, the input end of the waveform modulation circuit is also connected with an oscillator, the output end of the waveform modulation circuit outputs a modulation pulse signal DX, the input end of the error amplifier is connected with a current detection pin CS, the error amplifier amplifies external sampling current to obtain a current input signal CSIN, the current input signal CSIN is connected with an overcurrent protection circuit, the high-voltage band gap reference is used for providing a reference voltage Vref, the internal power supply generating circuit is used for generating an internal power supply voltage VCC and various bias signals according to the reference voltage Vref and is used by other circuits in the chip, the overcurrent protection circuit, the overvoltage protection circuit and the undervoltage protection circuit respectively generate an overcurrent protection signal OCP, an overvoltage protection signal OTP and an undervoltage protection signal UVLO according to the reference voltage Vref, the overcurrent protection signal OTP and the modulation pulse signal UVLO are all connected to control logic through processing to obtain an output control pulse Din, the output control pulse Din is connected to a high-efficiency output driving circuit and an output driving circuit Guan Yinjiao through a high-efficiency output driving buffer driving circuit;

After a chip power supply pin VDD meets the power-on requirement, the high-voltage band gap reference works normally at first and provides a 1.2V reference voltage Vref, an input receiving circuit receives an external input pulse and converts the external input pulse into a logic level VIN with a high level VCC, then the logic level VIN and an oscillation clock generated by an oscillator are modulated to obtain a modulation pulse signal DX, an error amplifier amplifies an external sampling current to obtain a current input signal CSIN, the current input signal CSIN enters an overcurrent protection circuit and is compared to obtain an overcurrent protection signal OCP, a control logic carries out logic processing on the overcurrent protection signal OCP, the overvoltage protection signal OTP, an undervoltage protection signal UVLO and the modulation pulse signal DX, an output control pulse Din for output driving is output, the output control pulse Din is buffered and driven by a high-efficiency output driving circuit to obtain an output driving signal, and the output driving signal VO is output by an output driving switch pin.

Specifically, the over-temperature protection circuit comprises an NPN triode Q61, an NPN triode Q60, a resistor R61, a resistor R62, a PMOS tube P60, an inverter Inv60, a capacitor C60 and a Schmitt trigger Schmitt, wherein the collector of the NPN triode Q61 is connected to an internal power supply voltage VCC, the emitter of the NPN triode Q61 is connected to the upper end of the resistor R61, the base of the NPN triode Q61 is connected to a reference voltage Vref, the lower end of the resistor R61 is connected to the upper end of the resistor R61 and the base of the NPN triode Q60, the collector of the NPN triode Q60 is connected to the upper end of the capacitor C60, the output end of the inverter Inv60, the drain of the PMOS tube P60 and the input end of the Schmitt trigger Schmitt, the grid of the PMOS tube P60 is connected to a bias voltage Vb6, the signal Ctrl connected to the input end of the inverter Inv60 is a chip global control signal, the output end of the Schmitt trigger Schmitt is an over-temperature protection signal, and the lower end of the resistor R62, the capacitor C60 and the emitter of the NPN triode Q60 are connected to the ground GND.

The high-efficiency output driving circuit comprises a P-end output adjustable buffer driving circuit, an N-end output adjustable buffer driving circuit, a sampling switch SW, a working time sequence generating circuit, a load comparison quantization circuit and a driving current selecting circuit;

The output control pulse Din is simultaneously connected to the data input ends of the P-end output adjustable buffer driving circuit, the N-end output adjustable buffer driving circuit and the working time sequence generating circuit; the P end output adjustable buffer driving circuit is connected with the driving signal output end of the N end output adjustable buffer driving circuit, is used as an output end for outputting driving signals, is connected to the input end of the load comparison quantization circuit through a sampling switch SW, performs tracking judgment on the frequency of an output control pulse Din to obtain a frequency judgment code Dfin, and generates a control clock Ck1 and a control clock Ck2 with high levels not overlapped, wherein the frequency judgment code Dfin is connected to the load comparison quantization circuit, the control clock Ck1 is connected to the load comparison quantization circuit and the driving current selection circuit, the control clock Ck2 is connected to the driving current selection circuit, the output driving signals are sampled by the sampling switch SW and then enter the load comparison quantization circuit, are connected to the driving current selection circuit under the control of a reference voltage Vr, the control clock Ck1 and the frequency judgment code Dfin, and are respectively connected to the load quantization code Dlot, the load quantization code Dlot, the control clock Ck1 and the control clock Ck2 enter the driving current selection circuit at the same time to obtain N switch control signals Kp 1-N1-Kn 4, the switch control signals Kp 1-N4 are respectively connected to the positive end of the load comparison quantization circuit, and the P1-N control signals are respectively connected to the positive end of the load comparison quantization circuit;

After the power supply voltage is electrified, the working time sequence generating circuit tracks and judges the frequency of the output control pulse Din to obtain a frequency judging code Dfin, and generates a control clock Ck1 and a control clock Ck2; when Ck1 clock is effective, the load comparison quantization circuit will generate a default set of load quantization codes Dlot _pre and enter the drive current selection circuit according to the output drive signal VO sampled by the sampling switch SW, reference voltage Vr and frequency discrimination code Dfin, the drive current selection circuit will output a default set of switch control signals Kp1_pre-Kpn_pre and switch control signals Kn1_pre, the output drive signal will drive the external load under the action of default drive current and make the voltage of the output drive signal gradually increase, when Ck1 clock is over, the load quantization code Dlot _pre will be adjusted according to the magnitude of the output drive signal at this time, the adjusted load quantization code Dlot _lock will remain unchanged, when Ck2 clock is effective, the drive current selection circuit will output a new set of switch control signals Kp1_lock-Kpn_lock and switch control signals Kn1_lock to 3, the voltage of the output buffer circuit will be increased under the action of the output drive signal Kpn_lock, when Ck1 clock is over, the drive signal is over the buffer circuit will be reset, the drive current is controlled to the end of the drive signal Kn1, the buffer circuit will be reset, the drive current is controlled to be turned off when Ck1 clock is over, the buffer circuit is reset, the output voltage is reset, P35 is reset, P is reached, the N-terminal output inverters in the N-terminal output adjustable buffer driving circuit are turned on to control the switches, and the output driving signal is quickly pulled from the voltage VCC to the ground voltage GND, so that the external load power device is turned off.

The P-end output adjustable buffer driving circuit comprises an inverter chain, wherein the input end of the inverter chain is connected with an output control pulse Din, the output end of the inverter chain is respectively connected with the input ends of n P-end output inverters through n P-end output inverter control switches, the output ends of the n P-end output inverters are respectively connected with the grid ends of n P-end output PMOS pipes, and the source ends of the n P-end output PMOS pipes are simultaneously connected to an internal power supply voltage VCC;

The N-end output adjustable buffer driving circuit comprises an inverter chain, wherein the input end of the inverter chain is connected with an output control pulse Din, the output end of the inverter chain is respectively connected with the input ends of N N-end output inverters through N N-end output inverter control switches, the output ends of the N N-end output inverters are respectively connected with the grid ends of N N-end output NMOS tubes, the source ends of the N N-end output NMOS tubes are simultaneously connected to a ground voltage GND, and the N N-end output inverter control switches are respectively controlled by switch control signals Kn 1-Knn;

The drain ends of the N P-end output PMOS tubes are connected with the drain ends of the N N-end output NMOS tubes, and are connected to the input end of the load comparison quantization circuit through the sampling switch SW and also connected to the output drive switch pin VO.

The working time sequence generating circuit comprises an oscillator, a pulse width counter, a counting period selecting circuit, a comprehensive counter, a first clock waveform generating circuit and a second clock waveform generating circuit, wherein an OSC signal generated by the oscillator is connected to the pulse width counter and the comprehensive counter, an output control pulse Din is simultaneously connected to the pulse width counter and the comprehensive counter, the pulse width counter counts the pulse time width of the output control pulse Din according to the OSC signal and carries out tracking judgment and comparison on the counted pulse time width to output a frequency judging code Dfin, the frequency judging code Dfin is connected to the counting period selecting circuit to generate a comprehensive counter mode selecting signal sel0, the comprehensive counter generates a clock control signal ct1 and a clock control signal ct2 according to the mode selecting signal sel0, the OSC signal and the output control pulse Din, and finally the clock control signal ct1 and the clock control signal ct2 are respectively connected to the first clock waveform generating circuit and the second clock waveform generating circuit, and the first clock waveform generating circuit and the second clock waveform generating circuit respectively output final control clocks Ck1 and Ck2.

The load comparison quantization circuit comprises a quantization voltage generation circuit, a high-low speed mode selection circuit, N comparators, an error filter circuit, a path selection circuit, a serial shift register, a serial-parallel conversion circuit and an M-bit buffer output circuit; the input end of the quantized voltage generating circuit is connected with the reference voltage Vr, the control clock Ck1 and a mode control signal mod output by the high-low speed mode selecting circuit, and the quantized voltage generating circuit converts the reference voltage Vr into N quantized reference voltages Vr 1-VrN under the control of the control clock Ck1 and is respectively connected to the reference voltage input ends of N comparators; the detection voltage input ends of the N comparators are all connected with the output driving switch pins VO, the N comparators respectively compare the output driving signals with N quantization reference voltages Vr 1-VrN to output N-bit quantized values D1-DN, then the N-bit quantized values D1-DN enter an error filtering circuit to output N-bit quantized codes Dlo, the high-low speed mode selection circuit outputs a mode control signal mod according to the size of the frequency discrimination code Dfin so as to change the mode of the load comparison quantization circuit, the speed and the power consumption of the load comparison quantization circuit are changed, the mode control signal mod is respectively connected to a quantization voltage generation circuit, the N comparators, the error filtering circuit and a path selection circuit, the path selection circuit selects a signal path of the N-bit quantized codes Dlo under the control of the mode control signal mod, the high speed path output port of the path selection circuit is N-bit parallel data and is directly output to the first data input port of the M-bit buffer output circuit, the low speed path output port of the path selection circuit is 1-bit serial data and is firstly connected to the serial shift register, the serial shift register outputs and then enters the serial-parallel conversion circuit to obtain M-bit parallel quantized codes Dlp which are connected to a second data input port of the M-bit buffer output circuit, and the M-bit buffer output circuit outputs a final M-bit load quantized code Dlot under the control of a control clock Ck1, wherein M and N are integers larger than 1.

Specifically, the load comparison quantization circuit includes a high-speed mode and a low-speed mode;

The high-speed mode comprises the following working modes that a quantization voltage generating circuit outputs N quantization reference voltages under the control of a control clock Ck1, N comparators respectively compare an output driving signal with the N quantization reference voltages at the same time and output N quantization values D1-DN which are output in parallel, and then an N-bit quantization code Dlo is obtained through an error filtering circuit, wherein the N-bit quantization code Dlo is N-bit parallel data, a high-speed path output port through a path selecting circuit is directly output to a first data input port of an M-bit buffer output circuit, and the M-bit buffer output circuit outputs a final M-bit load quantization code Dlot under the control of the control clock Ck 1;

The working mode of the low-speed mode comprises that only a first comparator of N comparators works, the rest N-1 comparators are dormant, the quantized voltage generating circuit sequentially outputs N quantized reference voltages through one output port according to time sequence under the control of a control clock Ck1, the first comparator sequentially compares output driving signals with the N quantized reference voltages according to time sequence, the output port of the first comparator sequentially outputs quantized values D1-DN of N-bit serial output according to time sequence, then N-bit quantized codes Dlo are obtained through an error filtering circuit, at the moment, the N-bit quantized codes Dlo are 1-bit serial data, the output port of a low-speed path through a path selection circuit sequentially enters a serial shift register, the output of the serial shift register sequentially enters a serial-parallel conversion circuit, M-bit parallel quantized codes Dlp are output to a second data input port of an M-bit buffer output circuit, and the M-bit buffer output circuit obtains final M-bit load quantized codes Dlot under the control of the control clock Ck 1.

The invention has the advantages that the high-efficiency gate drive provided by the invention improves the functional reliability of the whole chip by adopting a plurality of chip abnormal state monitoring protection circuits, and in addition, the output drive part of the invention adopts a specially-made high-output-efficiency output drive circuit, and the optimal output drive current can be provided by self-adaptively identifying the load size and the frequency of input control pulse and self-adaptively adjusting in real time, thereby realizing the aim of improving the efficiency.

Drawings

Fig. 1 is a block diagram of the overall circuit configuration of the present invention.

Fig. 2 is a schematic diagram of a high voltage bandgap reference circuit in an embodiment of the invention.

Fig. 3 is a schematic diagram of an internal power generation circuit according to an embodiment of the invention.

Fig. 4 is a schematic diagram of an error amplifier circuit in an embodiment of the invention.

Fig. 5 is a schematic diagram of an over-temperature protection circuit according to an embodiment of the invention.

FIG. 6 is a schematic diagram of an under-voltage protection circuit according to an embodiment of the present invention.

Fig. 7 is a schematic diagram of an overcurrent protection circuit according to an embodiment of the invention.

Fig. 8 is a block diagram of a high-efficiency output driving circuit according to an embodiment of the present invention.

FIG. 9 is a schematic diagram of the waveform of the high efficiency output driving circuit according to the present invention.

Fig. 10 is a schematic diagram of a P-terminal output adjustable buffer driving circuit according to an embodiment of the invention.

FIG. 11 is a schematic diagram of an N-terminal output adjustable buffer driving circuit according to an embodiment of the invention.

FIG. 12 is a block diagram of an operation timing generation circuit according to an embodiment of the invention.

Fig. 13 is a block diagram of a load comparison quantization circuit according to an embodiment of the present invention.

Detailed Description

The invention will now be described in further detail with reference to the accompanying drawings and examples.

As shown in fig. 1, the high-efficiency gate driving circuit according to the present invention includes an input receiving circuit 1, a high-voltage bandgap reference 2, an internal power supply generating circuit 3, a high-efficiency output driving circuit 4, an overcurrent protection circuit 5, an overcurrent protection circuit 6, an undervoltage protection circuit 7, an Oscillator (OSC) 8, a waveform modulation circuit 9, a control logic 10, and an error amplifier 11. The high-efficiency gate driving circuit is provided with 5 pairs of external pins, wherein VDD is a chip power supply pin, INX is an external input pulse pin, CS is a current detection pin, VO is an output driving switch pin, and GND is a ground pin. The signal names input or output by the pins are sometimes also denoted by pin names in the following description.

After the power pin VDD of the chip meets the power-up requirement, the high-voltage bandgap reference 2 first operates normally and provides a 1.2V reference voltage Vref. The internal power supply generating circuit 3 generates an internal power supply voltage VCC and various bias signals according to the reference voltage Vref. The over-current protection circuit 5, the over-temperature protection circuit 6 and the under-voltage protection circuit 7 respectively generate an over-current protection signal OCP, an over-temperature protection signal OTP and an under-voltage protection signal UVLO according to the reference voltage Vref. The internal power supply voltage VCC and various bias signals are used by other circuit modules in the chip.

The input receiving circuit 1 receives an external input pulse INX and converts the external input pulse INX into a logic level VIN having a high level VCC, and then modulates VIN with an oscillation clock generated by the oscillator 8 to obtain a modulated pulse signal DX. The error amplifier 11 amplifies the external sampling current CS to obtain a current input signal CSIN, and the current input signal CSIN enters the overcurrent protection circuit 5 to be compared to obtain an overcurrent protection signal OCP. The over-current protection signal OCP, the over-temperature protection signal OTP, the under-voltage protection signal UVLO and the modulation pulse signal DX are all connected to the control logic 10, and are processed to obtain an output control pulse Din for output driving. The output control pulse Din is buffer-driven by the high-efficiency output drive circuit 4 to obtain an output drive signal VO.

The method for modulating the logic level VIN and the oscillation clock to obtain the modulated pulse signal DX can be implemented by adopting the conventional digital modulation technology.

Fig. 2 is a circuit diagram of an embodiment of the high voltage bandgap reference 2 of the invention. The characteristics of circuit references in the chip circuit can greatly affect the performance of the whole chip, and an accurate and reliable reference is a powerful guarantee for the chip to work normally. The core structure of the circuit is a resistor R31, a resistor R32, a triode Q31, a triode Q32, a PMOS tube P31 and a PMOS tube P32.MOS tubes P34-P36 are high-voltage MOS tubes which can resist high voltage between source and drain, and after the MOS tubes P34-P36 are added, the power supply is isolated from the output reference voltage Vref, so that the power supply inhibition capability of the whole circuit is remarkably improved. The MOS transistor P33 is added to inhibit the variation of Vref caused by the variation of bias current.

In fig. 2, the circuit has two feedback loops, a first feedback loop from the lower side of the MOS transistor N31 to the transistor Q32 and a second feedback loop from the upper side of the MOS transistor N31 to the PMOS transistors P31 and P32. The feedback loop I is used for providing base currents for the triode Q31 and the triode Q32 and forming negative feedback to ensure the stability of Vref. The second feedback loop is due to the MOS transistors P34-P36, and the change of the base voltage of the MOS transistor N31 directly affects the source voltage of the PMOS transistor P31 in the same direction through the MOS transistor N31. Therefore, the MOS transistor P33 is added to counteract the influence of the change of the base voltage of the MOS transistor N31 on the source voltage of the PMOS transistor P31. Meanwhile, due to the effect of the P33 tube, the source voltage of the PMOS tube P31 becomes larger, and the sizes of the MOS tube N31 and the MOS tube P33 are properly selected, so that the source voltage of the PMOS tube P31 is not influenced by the base voltage of the MOS tube N31 under the combined effect of the two. In addition, the capacitor C31 is used as a compensation capacitor to provide a better phase margin for the feedback loop two. R33 represents a resistive divider network that functions to generate a number of reference voltages that are less than the bandgap reference voltage.

Fig. 3 is a circuit diagram of an embodiment of the internal power supply generating circuit 3 according to the present invention. The reference voltage obtained from the high-voltage bandgap reference 2 is only 1.2V, and the required operating voltage VCC of other operating modules in the chip is 5V, and the power supply requirements of other modules in the chip cannot be met by the bandgap reference circuit alone, so that a voltage regulator is required to regulate the voltage so as to meet the requirements of other modules. The circuit in fig. 3 can generate a plurality of slightly different power supply voltages in the chip, and since the voltages of the gates and the drains of the MOS transistors N41, N42, N43 and N44 are the same, we can draw a conclusion that if the same load is carried under the MOS transistors N41 to N44, the magnitudes of the four values VCC1, VCC2, VCC3 and VCC4 are all equal, and if the loads are not equal, the magnitude of the voltage difference between the values is determined by the magnitude of the load, and the greater the load is, the greater the voltage is.

In this embodiment, VCC1 is used for some modules that are relatively static, and VCC 2-VCC 4 are used for some modules that are dynamic. Generally, the load of the VCC1 band is the largest. However, this may create a problem that if the load carried by VCC2 to VCC4 is much greater than VCC1 for every voltage, a large voltage difference may be generated, which may cause some logic circuits to fail to operate. In order to solve the problem, 3 PMOS transistors may be added between VCC1 and VCC2 to VCC4 to form a voltage limiting circuit, and when VCC2 to VCC4 is greater than VCC1 and exceeds a threshold voltage, the corresponding MOS transistors P42 to P44 are turned on to reduce the voltage of VCC2 to VCC4 below VCC 1. The method is simple and convenient, and a level conversion circuit is not needed to be additionally arranged, so that the area of a chip is saved.

Fig. 4 is a circuit diagram of an embodiment of the error amplifier 11 of the present invention, which employs a two-stage op amp configuration. The first-stage amplifier adopts a folding type common-source common-gate structure, and MOS tubes N53 and N54 are input pair tubes of the first stage, so that the error amplifier 11 has higher bandwidth and open-loop gain, and has larger input common-mode level, larger output swing and easy input and output short circuit to form a proportional operation circuit compared with a sleeve type common-source common-gate operational amplifier. The second-stage amplifier adopts a common single-end common source circuit and consists of MOS transistors N57 and P58 for improving the output swing amplitude, and in order to improve the phase margin of the amplifier, a Miller compensation increasing loop phase margin is formed between the output stage series resistor R53 and the capacitor C51 of the second-stage output stage and the output stage of the first-stage output stage, so that the output stage point of the first-stage amplifier is pushed to the low frequency to become a main pole. If the feedback signal and the reference voltage differ too much, the error amplifier 11 will operate in the comparator state, i.e. when the sampled CS is much higher than the reference voltage Vref, the error amplifier 11 will output a high level, otherwise a low level. If the feedback signal and the reference voltage do not differ much, the error amplifier 11 will operate in a linear amplification state.

Fig. 5 is a circuit diagram of an embodiment of the over-temperature protection circuit 6 of the present invention. The chip heats up during operation, especially at elevated frequencies, so that a thermal protection circuit must be present inside the chip, which may burn out due to excessive temperatures. The thermal protection circuit must be extremely sensitive to temperature, and the common thermal protection circuit uses the over-temperature protection signal generated by the voltage of the base emitter of the bipolar transistor along with the temperature sensitivity, so the design of the chip thermal protection circuit is also based on the characteristic of a triode. When the working temperature of the chip exceeds the set temperature threshold, the over-temperature protection circuit 6 outputs a protection signal to stop the chip, and when the temperature is reduced to a certain value, the chip is restarted to enter a normal working state.

As shown in fig. 5, the over-temperature protection circuit 6 used in this embodiment includes an NPN triode Q61, an NPN triode Q60, a resistor R61, a resistor R62, a PMOS tube P60, an inverter Inv60, a capacitor C60, and a Schmitt trigger Schmitt. The collector of NPN triode Q61 is connected to internal power supply voltage VCC, and NPN triode Q61's projecting pole is connected resistance R61 upper end, and NPN triode Q61 base is connected reference voltage Vref. The lower end of the resistor R61 is connected with the upper end of the resistor R61 and is also connected to the base electrode of the NPN triode Q60. The collector of NPN triode Q60 connects the upper end of capacitor C60, the output end of inverter Inv60, the drain electrode of PMOS tube P60 and the input end of Schmitt trigger Schmitt. The source of the PMOS tube P60 is connected with an internal power supply voltage VCC, and the grid of the PMOS tube P60 is connected with a bias voltage Vb6. The input Ctrl signal of the inverter Inv60 is a chip global control signal, which may be a power-on reset signal or other control signals, and the output of the Schmitt trigger Schmitt is an over-temperature protection signal OTP. The lower end of the resistor R61, the lower end of the capacitor C60 and the emitter of the NPN triode Q60 are all connected to the ground voltage GND.

The Vbe (base-emitter voltage) of transistor Q61 has a negative temperature coefficient. When the chip is operating normally, the Vref voltage is less than the Vbe on voltage of transistor Q61, so transistor Q61 will not conduct. When the temperature increases, the Vbe of the transistor Q61 decreases, the voltages across the resistors R61 and R62 change with the temperature at the same time, when the Vbe decreases to the Vref voltage, the transistor Q61 is turned on, and when the voltage at point a increases until the on voltage of the transistor Q60 increases, the transistor Q60 is turned on, and the collector voltage (voltage at point B) of the transistor Q60 becomes low. The low level is triggered to turn from the low level to the high level OTP through Schmitt trigger Schmitt delay, and the OTP is an overheat protection signal. The Schmidt trigger Schmidt hysteresis loop design can effectively prevent the problem that the chip cannot work normally due to thermal shock.

Fig. 6 shows an embodiment of the undervoltage protection circuit 7 of the present invention. If the output voltage is below the nominal value, which would damage the load, the output voltage must be limited, and thus the undervoltage protection circuit 7 is designed. Triggering under-voltage protection when the VDD is lower than 6.5V according to the chip design index. The voltage division of the VDD pin is detected through the negative input end of a two-stage operational amplifier comparator, and when the amplifier detects that the VDD voltage division is larger than the set reference voltage, the output level of the comparator latches the SR latch into '1' through an inverter to generate a UVLO signal.

Fig. 7 shows an embodiment of the overcurrent protection circuit 5 according to the present invention. If the feedback resistor outside the current detection pin CS is short-circuited or open-circuited, the CSIN signal will be abnormal and cannot be normally sampled and output, so that an open-circuit and short-circuit protection circuit is designed inside the chip. The operating principle is that when Ctrl signal rises to indicate that the primary side is conducted, the transformer transmits energy to the secondary side winding, at the moment, the internal power supply voltage VCC charges the capacitor C through PCH1 to reach the forward threshold voltage of the Schmitt trigger, and the protection signal OCP is not triggered. After the turn-on Ctrl signal disappears, the capacitor C is discharged to ground through PCH2, and after a small delay, the capacitor voltage drops to the inverted threshold voltage of the schmitt trigger, at which time OCP will be triggered.

For the implementation of the output driving circuit, the prior art is generally implemented by using cascaded step-by-step amplifying inverter chains. The output driving capability of the conventional output driving circuit is solidified after the chip is designed and shaped. In practical applications, to prevent the VO output current from damaging the gate terminal of the external power switch MOSFET to be driven, a resistor is usually connected in series to the VO output terminal to suppress the voltage overshoot effect of the gate terminal. When the equivalent capacitance of the MOSFET gate end is larger, the series protection resistance needs to be smaller, otherwise, the series protection resistance needs to be larger. The relatively large series protection resistor can bring 2 problems, namely, the switching loss on the resistor is increased, the efficiency of the driving circuit is reduced, the driving delay is increased, and finally, the switching frequency of the system is reduced. In addition, the use of the series protection resistor increases the design workload of the design engineer and reduces the reliability of the overall system. The invention designs a high-efficiency output driving circuit with self-adaptive driving capability aiming at the problems. The circuit can adaptively adjust the driving current by adaptively recognizing the load size and the frequency of the input control pulse.

As shown in fig. 8, the high-efficiency output driving circuit 4 of the present invention includes a P-terminal output adjustable buffer driving circuit 41, an N-terminal output adjustable buffer driving circuit 42, a sampling switch SW, an operation timing generating circuit 43, a load comparison quantizing circuit 44, and a driving current selecting circuit 45.

The output control pulse Din is connected to the data input terminals of the P-terminal output adjustable buffer driving circuit 41, the N-terminal output adjustable buffer driving circuit 42, and the operation timing generation circuit 43 at the same time. The output driving signal of the P end output adjustable buffer driving circuit 41 is connected with the driving signal output end of the N end output adjustable buffer driving circuit 42, is used as an output end of an output driving signal, is connected with an output driving switch pin VO and is connected to the left side of a sampling switch SW, enters a load comparison quantization circuit 44 after being sampled by the sampling switch SW, and obtains a load quantization code Dlot under the control of a reference voltage Vr, a control clock Ck1 and a frequency discrimination code Dfin and enters a driving current selection circuit 45. The operation timing generation circuit 43 performs tracking discrimination on the frequency of the output control pulse Din to obtain a Din frequency discrimination code Dfin, and generates high-level non-overlapping control clocks Ck1 and Ck2. The load quantization code Dlot and the control clocks Ck1 and Ck2 enter the driving current selection circuit 45 at the same time to obtain N control signals Kp 1-Kpn (controlling the switch in the P end output adjustable buffer driving circuit 41) and N switch control signals Kn 1-Knn (controlling the switch in the N end output adjustable buffer driving circuit 42), the switch control signals Kp 1-Kpn are respectively connected to N switch signal input ends of the P end output adjustable buffer driving circuit 41, and the switch control signals Kn 1-Knn are respectively connected to N switch signal input ends of the P end output adjustable buffer driving circuit 41. Wherein n is any positive integer.

Fig. 9 is a schematic diagram of VO output waveforms of the high-efficiency output driving circuit 4 under three different loads. The waveforms correspond to loads of 0.5nF, 1nF, 1.5nF from top to bottom, respectively. When the power supply voltage is powered on, the operation timing generation circuit 43 performs tracking discrimination on the frequency of the output control pulse Din to obtain a frequency discrimination code Dfin, and generates control clocks Ck1 and Ck2. When Ck1 clock is effective, the load comparison quantization circuit 44 will generate a default set of load quantization codes Dlot _pre and enter the drive current selection circuit 45 according to the output drive signal VO sampled by the sampling switch SW, the reference voltage Vr and the state of the frequency discrimination code Dfin, the drive current selection circuit 45 will output a default set of switch control signals Kp1_pre to Kpn_pre (control P terminal outputs the switch in the adjustable buffer drive circuit 41) and Kn1_pre to Knn _pre (control N terminal outputs the switch in the adjustable buffer drive circuit 42), the output drive signal VO will drive the external load under the action of the default drive current Iout_pre and make the voltage of the output drive signal VO gradually increase, when Ck1 clock is over, the load quantization code Dlot _pre will be adjusted according to the size of the output drive signal at this moment, the load quantization code Dlot _lock after adjustment is kept unchanged, when Ck2 clock is effective, the current selection circuit will output a current 45 will drive the load quantization signal in the load quantization code according to Kp29_pre (control P terminal outputs the switch in the adjustable buffer drive circuit 42) and the load quantization signal VO 1 is turned off, when the output signal Ck1 clock is clear, the load quantization circuit can be turned off gradually, the load quantization circuit can be turned off according to the load quantization code of the load quantization code 45 is adjusted according to the size of the output at this time, the output signal P29_pre is turned off, and the load quantization code is adjusted by the load quantization code, and the load quantization code is adjusted according to the size is adjusted by the size at the level of the output by the output signal P1, and simultaneously, switch control signals Kn 1-Knn are turned on (the switch in the N-end output adjustable buffer driving circuit 42 is turned on), and the output driving signal VO is quickly pulled from the power supply voltage VCC to the ground voltage GND, so that the external load power device is turned off.

In the above operation, during the period when the Ck1 clock is active, the output driving signal VO will drive the external load under the action of the default driving current iout_pre, and the voltage of the output driving signal VO will be gradually increased. The output drive signal VO will produce different dv/dt changes for different external loads. For a fixed output drive current iout_pre, it is apparent that the larger the load capacitance is driven, the lower the rising slope of the output drive signal VO, and the magnitude of the output drive signal VO at the end of the Ck1 clock is inversely related to the load capacitance, i.e. the output drive signal VO voltage at a load of 0.5nF should be 3 times the output drive signal VO voltage at a load of 1.5 nF. Therefore, under a fixed driving current condition, the magnitude of the output driving load can be determined according to the magnitude of the output driving signal VO voltage at the end of the Ck1 clock, and the magnitude of the output driving load is quantized by the load comparison quantization circuit 44, so as to obtain the load quantization code Dlot _lock. When the Ck2 clock is active, the driving current selecting circuit 45 outputs a new set of switch control signals according to the load quantization code Dlot _lock, and the output driving signal VO drives the external load under the action of the new driving current iout_lock, so that the voltage of the output driving signal VO rises rapidly to the power supply voltage VCC. When the load quantization code Dlot _lock indicates a larger external load, the driving current selection circuit 45 outputs a set of larger switching control signals so that the output driving signal VO outputs a larger output driving current iout_lock, and when the load quantization code Dlot _lock indicates a smaller external load, the driving current selection circuit 45 outputs a set of smaller switching control signals so that the output driving signal VO outputs a smaller output driving current iout_lock.

Fig. 10 is a circuit diagram of an embodiment of the P-side output adjustable buffer driving circuit 41 according to the present invention. The P-end output adjustable buffer driving circuit 41 comprises an inverter chain, n P-end output inverter control switches Sp 1-Spn, n P-end output inverters Invpk _1-Invpk_n and n P-end output PMOS tubes MP 1-Mpn. The input end of the inverter chain is connected with the output control pulse Din, the output end of the inverter chain is respectively connected with the input end of n P-end output inverters Invpk _1-Invpk_n through n P-end output inverter control switches Sp 1-Spn, namely, the control switch Sp1 is connected with the input end of an inverter Invpk _1, the control switch Sp2 is connected with the input end of an inverter Invpk _2, the control switch Spn is connected with the input end of an inverter Invpk _n, the output ends of n P-end output inverters Invpk _1-Invpk_n are respectively connected with the gate ends of n P-end output PMOS tubes MP 1-Mpn, namely, the output end of the inverter Invpk _1 is connected with the gate end of a PMOS tube MP1, the output end of the inverter Invpk _2 is connected with the gate end of a PMOS tube MP2, the output end of the inverter Invpk _n is connected with the gate end of the PMOS tube MP, and the source ends of the n P-end output tubes MP 1-Mpn are simultaneously connected with a power supply voltage VCC. The n P-terminal output inverter control switches Sp1 to Spn are controlled by switch control signals Kp1 to Kpn, respectively.

Fig. 11 is a circuit diagram of an embodiment of the N-terminal output adjustable buffer driving circuit 42 according to the present invention. The N-terminal output adjustable buffer driving circuit 42 comprises an inverter chain, N N-terminal output inverter control switches Sn 1-Snn, N N-terminal output inverters Invnk _1-Invnk_n and N N-terminal output NMOS transistors Mn 1-Mnn. The circuit structure is similar to the P-side output adjustable buffer driving circuit 41 and will not be described in detail here. The input end of the inverter chain is also connected to an output control pulse Din, the source ends of N N-terminal output NMOS tubes Mn 1-Mnn are simultaneously connected to a ground voltage GND, and N N-terminal output inverter control switches Sn 1-Snn are respectively controlled by switch control signals Kn 1-Knn.

In fig. 10 and 11, the drain terminals of N P-terminal output PMOS transistors Mp1 to Mpn and the drain terminals of N-terminal output NMOS transistors Mn1 to Mnn are connected together to generate an output driving signal VO.

Fig. 12 is a block diagram showing the operation timing generation circuit 43 of fig. 8 according to the present invention. The operation timing generation circuit 43 includes an oscillator 121, a pulse width counter 122, a count period selection circuit 123, a comprehensive counter 124, a first clock waveform generation circuit 125, and a second clock waveform generation circuit 126.

The oscillator 121 generates an OSC signal and is connected to the pulse width counter 122 and the integration counter 124, and the output control pulse Din is simultaneously connected to the pulse width counter 122 and the integration counter 124. The pulse width counter 122 counts the pulse time width of the output control pulse Din according to the OSC signal, performs tracking discrimination on the counted pulse time width, performs comparison and quantization to obtain a frequency discrimination code Dfin, and then the frequency discrimination code Dfin enters the count period selection circuit 123 to generate the integrated counter mode selection signal sel0. The integrated counter 124 generates a clock control signal ct1 and a clock control signal ct2 according to the integrated counter mode selection signal sel0, the OSC signal, and the output control pulse Din, respectively. The clock control signal ct1 enters the first clock waveform generation circuit 125 and outputs the control clock Ck1. The clock control signal ct2 enters the second clock waveform generation circuit 126 and outputs the control clock Ck2.

The operation timing generation circuit 43 may generate different Dfin codes according to the pulse width of the output control pulse Din, so as to adjust the output clock frequencies of the control clock Ck1 and the control clock Ck2, thereby adjusting the load detection time during the effective period of the control clock Ck1 and improving the detection accuracy. For example, when the Dfin code= "11" is 2 bits Dfin codes, it means that the input pulse width is wide, the switching frequency of the output control pulse Din is low, and the output clocks of the control clock Ck1 and the control clock Ck2 can output control timings with long clock cycles. Dfin code= "00" indicates that the input pulse width is narrow, the switching frequency of the output control pulse Din is high, and the output clocks of the control clock Ck1 and the control clock Ck2 need to output control timings with the shortest clock period.

Fig. 13 is a block diagram showing a structure of the load comparison quantization circuit 44 in fig. 8, which includes a quantization voltage generation circuit 131, a high-low speed mode selection circuit 132, N comparators, an error filter circuit 133, a path selection circuit 134, a serial shift register 135, a serial/parallel conversion circuit 136, and an M-bit buffer output circuit 137. The quantization voltage generating circuit 131 converts the reference voltage Vr into N quantization reference voltages Vr 1-VrN under the control of the control clock Ck1, the N quantization reference voltages Vr 1-VrN are respectively connected to the reference voltage input ends of N comparators, the detection voltage input ends of the N comparators are respectively connected to the output driving signals VO, the N comparators respectively compare the output driving signals VO with the N quantization reference voltages Vr 1-VrN to obtain N bit quantization values D1-DN, and the N bit quantization values enter the error filtering circuit 133 to output an N bit quantization code Dlo to the channel selecting circuit 134. The high-low speed mode selection circuit 132 changes the mode control signal mod according to the magnitude of the frequency discrimination code Dfin. The mode control signal mod is connected to the quantization voltage generation circuit 131, the N comparators, the error filtering circuit 133, and the path selection circuit 134, respectively. The mode control signal mod is capable of changing the mode of the load comparison quantization circuit 44, ultimately changing the speed and power consumption of the load comparison quantization circuit 44.

The path selection circuit 134 selects the signal path of the N-bit quantized code Dlo under the control of the mode control signal mod. The high-speed path output port of the path selection circuit 134 is N-bit parallel data, and directly outputs to the first data input port of the M-bit buffer output circuit 137. The low-speed path output port of the path selection circuit 134 is 1-bit serial data, which first enters the serial shift register 135, and then outputs M-bit parallel quantized codes Dlp through the serial/parallel conversion circuit 136, which is connected to the second data input port of the M-bit buffer output circuit 137.

The operation modes of the load comparison quantization circuit 44 include a high-speed mode and a low-speed mode. When in the high-speed mode, the quantization voltage generating circuit 131 outputs N quantization reference voltages Vr 1-VrN under the control of the control clock Ck1, N comparators compare the output driving signal VO with N quantization reference voltages Vr 1-VrN to obtain N parallel output quantization values D1-DN, and then the N parallel output values are obtained through the error filtering circuit 133 to obtain N quantization codes Dlo, where the N quantization codes Dlo are N parallel data, and after being output from the high-speed path output port of the path selecting circuit 134, the N parallel data are directly output to the first data input port of the M buffer output circuit 137, and the M buffer output circuit 137 outputs the final M load quantization codes Dlot under the control of the control clock Ck 1. When in the low speed mode, only the first of the N comparators is active and the remaining N-1 comparators sleep. The quantized voltage generating circuit 131 sequentially outputs N quantized reference voltages Vr 1-VrN through an Vr1 output port according to time sequence under the control of the control clock Ck1, the first comparator sequentially compares the output driving signal VO with N quantized reference voltages Vr 1-VrN output by Vr1 according to time sequence, sequentially outputs N quantized values D1-DN serially output through an output port according to time sequence, and then obtains N quantized codes Dlo through the error filtering circuit 133. At this time, the N-bit quantized code Dlo is 1-bit serial data, which is output from the low-speed path output port of the path selection circuit 134, then enters the serial shift register 135, passes through the serial/parallel conversion circuit 136 to obtain the M-bit parallel quantized code Dlp, and then is output to the second data input port of the M-bit buffer output circuit 137, where the M-bit buffer output circuit 137 obtains the final M-bit load quantized code Dlot under the control of the control clock Ck 1.

The load comparison and quantization circuit 44 uses both high speed and low speed modes to save power consumption of the circuit. The N reference voltages Vr 1-VrN can be set at uniform intervals by adopting thermometer codes or set by binary different weights. Therefore, in actual implementation, the type of the suitable comparator and the combination strategy can be selected according to the requirements of the application system of the driving chip. Because the comparator has certain offset, and the higher the working speed of the comparator is, the more serious the offset is, so that the error filtering is required to be carried out on the N-bit quantized values D1-DN, and the implementation strategies of the error filtering circuit 133 are quite different. If N comparators work in parallel, a digital algorithm for offset calibration of the Flash ADC comparator is needed to carry out error filtering, and if one comparator is used for multiplexing, a digital algorithm for offset calibration of the SARADC is needed to carry out error filtering.

The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims

1. A high-efficiency gate drive circuit, characterized in that it includes: an input receiving circuit, a high-voltage bandgap reference, an internal power generation circuit, a high-efficiency output drive circuit, an overcurrent protection circuit, an over-temperature protection circuit, an undervoltage protection circuit, an oscillator, a waveform modulation circuit, a control logic and an error amplifier; and also includes 5 external pins, namely: a chip power pin VDD, an external input pulse pin INX, a current detection pin CS, an output drive switch pin VO, and a ground pin GND;

The input end of the input receiving circuit is connected to the external input pulse pin INX, the output end of the input receiving circuit is connected to the input end of the waveform modulation circuit, the input end of the waveform modulation circuit is also connected to the oscillator, and the output end of the waveform modulation circuit outputs a modulated pulse signal DX; the input end of the error amplifier is connected to the current detection pin CS, the error amplifier amplifies the external sampling current to obtain a current input signal CSIN, and is connected to the overcurrent protection circuit; the high-voltage bandgap reference is used to provide a reference voltage Vref; the internal power generation circuit is used to generate an internal power supply voltage VCC and various bias signals according to the reference voltage Vref for use by other circuits in the chip; the overcurrent protection circuit, the overtemperature protection circuit, and the undervoltage protection circuit generate an overcurrent protection signal OCP, an overtemperature protection signal OTP, and an undervoltage protection signal UVLO according to the reference voltage Vref respectively; the overcurrent protection signal OCP, the overtemperature protection signal OTP, the undervoltage protection signal UVLO and the modulated pulse signal DX are all connected to the control logic, and the output control pulse Din is obtained after processing; the output control pulse Din is connected to the high-efficiency output drive circuit, and the output drive signal obtained by the high-efficiency output drive circuit buffer drive is connected to the output drive switch pin VO;

The high-efficiency output drive circuit comprises: a P-terminal output adjustable buffer drive circuit, an N-terminal output adjustable buffer drive circuit, a sampling switch SW, a working timing generation circuit, a load comparison quantization circuit and a drive current selection circuit;

The output control pulse Din is simultaneously connected to the data input end of the P-end output adjustable buffer driving circuit, the N-end output adjustable buffer driving circuit and the working timing generation circuit; the driving signal output ends of the P-end output adjustable buffer driving circuit and the N-end output adjustable buffer driving circuit are connected as the output end of the output driving signal, and are connected to the input end of the load comparison quantization circuit through the sampling switch SW; the working timing generation circuit tracks and determines the frequency of the output control pulse Din, obtains the frequency determination code Dfin, and generates a high-level non-overlapping control clock Ck1 and a control clock Ck2; wherein the frequency determination code Dfin is connected to the load comparison quantization circuit, the control clock Ck1 is connected to the load comparison quantization circuit and the driving current selection circuit, and the control clock Ck2 is connected connected to the driving current selection circuit; the output driving signal enters the load comparison quantization circuit after being sampled by the sampling switch SW, and obtains the load quantization code Dlot under the control of the reference voltage Vr, the control clock Ck1 and the frequency discrimination code Dfin, and is connected to the driving current selection circuit; the load quantization code Dlot, the control clock Ck1 and the control clock Ck2 enter the driving current selection circuit at the same time, and obtain n switch control signals Kp1~Kpn and n switch control signals Kn1~Knn; wherein the switch control signals Kp1~Kpn are respectively connected to the n switch signal input terminals of the P-end output adjustable buffer driving circuit, and the switch control signals Kn1~Knn are respectively connected to the n switch signal input terminals of the P-end output adjustable buffer driving circuit; n is an arbitrary positive integer.

2. The high-efficiency gate drive circuit according to claim 1 is characterized in that the over-temperature protection circuit comprises: an NPN transistor Q61, an NPN transistor Q60, a resistor R61, a resistor R62, a PMOS transistor P60, an inverter Inv60, a capacitor C60 and a Schmitt trigger Schmitt; the collector of the NPN transistor Q61 is connected to an internal power supply voltage VCC, the emitter of the NPN transistor Q61 is connected to an upper end of the resistor R61, and the base of the NPN transistor Q61 is connected to a reference voltage Vref; the lower end of the resistor R61 is connected to an upper end of the resistor R61 and a base of the NPN transistor Q60, The collector of the NPN transistor Q60 is connected to the upper end of the capacitor C60, the output end of the inverter Inv60, the drain of the PMOS tube P60 and the input end of the Schmitt trigger Schmitt; the source of the PMOS tube P60 is connected to the internal power supply voltage VCC, and the gate of the PMOS tube P60 is connected to the bias voltage Vb6; the signal Ctrl connected to the input end of the inverter Inv60 is the chip global control signal; the output end of the Schmitt trigger Schmitt outputs the over-temperature protection signal OTP; the lower end of the resistor R62, the lower end of the capacitor C60 and the emitter of the NPN transistor Q60 are all connected to the ground voltage GND.

3. The high-efficiency gate drive circuit according to claim 1 is characterized in that, after the power supply voltage is powered on, the working timing generation circuit tracks and determines the frequency of the output control pulse Din to obtain the frequency discrimination code Dfin, and generates the control clock Ck1 and the control clock Ck2; when the Ck1 clock is valid, the load comparison quantization circuit will first generate a set of default load quantization codes Dlot_pre according to the state of the output drive signal VO sampled by the sampling switch SW, the reference voltage Vr and the frequency discrimination code Dfin, and enter the drive current selection circuit, and the drive current selection circuit will output a set of default switch control signals Kp1_pre~Kpn_pre and the switch control signal Kn1_pre ~Knn_pre, the output drive signal will drive the external load under the default drive current and gradually increase the voltage of the output drive signal; when the Ck1 clock ends, the load quantization code Dlot_pre will be adjusted according to the size of the output drive signal at this time, and the adjusted load quantization code Dlot_lock will be obtained and remain unchanged; when the Ck2 clock is valid, the drive current selection circuit will output a set of new switch control signals Kp1_lock ~Kpn_lock and switch control signal Kn1_lock according to the load quantization code Dlot_lock ~Knn_lock, the output drive signal will drive the external load under the action of the new drive current and make the voltage of the output drive signal rise rapidly to the voltage VCC; when the Ck2 clock ends, the load quantization code Dlot will be cleared, and the switch control signals Kp1~Kpn output by the drive current selection circuit will be synchronously cleared, turning off the n P-end output inverter control switches in the P-end output adjustable buffer drive circuit, and at the same time, the switch control signals Kn1~Knn output by the drive current selection circuit are valid, turning on the n N-end output inverter control switches in the N-end output adjustable buffer drive circuit, and the output drive signal will be quickly pulled from the voltage VCC to the ground voltage GND, thereby turning off the external load power device.

4. The high-efficiency gate drive circuit according to claim 3, characterized in that the P-end output adjustable buffer drive circuit comprises: an inverter chain, the input end of the inverter chain is connected to the output control pulse Din, the output end of the inverter chain is connected to the input end of n P-end output inverters through n P-end output inverter control switches, the output ends of the n P-end output inverters are respectively connected to the gate ends of n P-end output PMOS tubes, and the source ends of the n P-end output PMOS tubes are simultaneously connected to the internal power supply voltage VCC; the n P-end output inverter control switches are respectively controlled by switch control signals Kp1~Kpn;

The N-terminal output adjustable buffer driving circuit comprises: an inverter chain, the input end of the inverter chain is connected to the output control pulse Din, the output end of the inverter chain is connected to the input end of n N-terminal output inverters through n N-terminal output inverter control switches, the output ends of the n N-terminal output inverters are respectively connected to the gate ends of n N-terminal output NMOS tubes, and the source ends of the n N-terminal output NMOS tubes are simultaneously connected to the ground voltage GND; the n N-terminal output inverter control switches are respectively controlled by switch control signals Kn1~Knn;

The drain ends of the n P-terminal output PMOS tubes are connected together with the drain ends of the n N-terminal output NMOS tubes, one end is connected to the input end of the load comparison quantization circuit through the sampling switch SW, and the other end is connected to the output drive switch pin VO.

5. The high-efficiency gate drive circuit according to claim 3 is characterized in that the working timing generation circuit comprises: an oscillator, a pulse width counter, a counting cycle selection circuit, a comprehensive counter, a first clock waveform generation circuit and a second clock waveform generation circuit; the OSC signal generated by the oscillator is connected to the pulse width counter and the comprehensive counter, and the output control pulse Din is simultaneously connected to the pulse width counter and the comprehensive counter; the pulse width counter counts the pulse time width of the output control pulse Din according to the OSC signal, and tracks, distinguishes and compares the pulse time width obtained by the count to quantize and output a frequency discrimination code Dfin; the frequency discrimination code Dfin is connected to the counting cycle selection circuit to generate a comprehensive counter mode selection signal sel0; the comprehensive counter generates a clock control signal ct1 and a clock control signal ct2 according to the mode selection signal sel0, the OSC signal and the output control pulse Din; finally, the clock control signal ct1 and the clock control signal ct2 are respectively connected to the first clock waveform generation circuit and the second clock waveform generation circuit, and the first clock waveform generation circuit and the second clock waveform generation circuit respectively output the final control clock Ck1 and the control clock Ck2.

6. The high-efficiency gate drive circuit according to claim 3 is characterized in that the load comparison quantization circuit comprises: a quantization voltage generation circuit, a high-speed and low-speed mode selection circuit, N comparators, an error filtering circuit, a path selection circuit, a serial shift register, a serial-to-parallel conversion circuit and an M-bit buffer output circuit; the input end of the quantization voltage generation circuit is connected to the reference voltage Vr, the control clock Ck1 and the mode control signal mod output by the high-speed and low-speed mode selection circuit, the quantization voltage generation circuit converts the reference voltage Vr into N quantization reference voltages Vr1~VrN under the control of the control clock Ck1, and connects them to the reference voltage input ends of the N comparators respectively; the detection voltage input ends of the N comparators are all connected to the output drive switch pins VO, the N comparators compare the output drive signal with the N quantization reference voltages Vr1~VrN respectively, and output N-bit quantization values D1~DN; then the N-bit quantization values D1~DN enter the error filtering circuit to output the N-bit quantization code Dlo; the high-speed and low-speed mode selection circuit The selection circuit outputs a mode control signal mod according to the size of the frequency discrimination code Dfin, thereby changing the mode of the load comparison quantization circuit to change the speed and power consumption of the load comparison quantization circuit. The mode control signal mod is respectively connected to the quantization voltage generation circuit, N comparators, an error filtering circuit, and a path selection circuit; the path selection circuit selects the signal path of the N-bit quantization code Dlo under the control of the mode control signal mod; the high-speed path output port of the path selection circuit is N-bit parallel data, which is directly output to the first data input port of the M-bit buffer output circuit, and the low-speed path output port of the path selection circuit is 1-bit serial data, which is first connected to the serial shift register, and the serial shift register output then enters the serial-to-parallel conversion circuit to obtain the M-bit parallel quantization code Dlp, which is connected to the second data input port of the M-bit buffer output circuit; the M-bit buffer output circuit outputs the final M-bit load quantization code Dlot under the control of the control clock Ck1; wherein M and N are both integers greater than 1.

7. The high-efficiency gate driving circuit according to claim 6, characterized in that the load comparison and quantization circuit includes a high-speed mode and a low-speed mode;

The working mode of the high-speed mode is as follows: the quantization voltage generating circuit outputs N quantization reference voltages simultaneously under the control of the control clock Ck1, and the N comparators respectively compare the output drive signal with the N quantization reference voltages simultaneously, and output N-bit parallel output quantization values D1~DN, and then pass through the error filtering circuit to obtain an N-bit quantization code Dlo; at this time, the N-bit quantization code Dlo is N-bit parallel data, which is directly output to the first data input port of the M-bit buffer output circuit through the high-speed path output port of the path selection circuit, and the M-bit buffer output circuit outputs the final M-bit load quantization code Dlot under the control of the control clock Ck1;

The working mode of the low-speed mode is as follows: only the first comparator among the N comparators works, and the remaining N-1 comparators are dormant. The quantization voltage generating circuit outputs N quantization reference voltages in chronological order from an output port under the control of the control clock Ck1. The first comparator compares the output drive signal with the N quantization reference voltages in chronological order, and outputs N-bit serial output quantization values D1~DN in chronological order at the output port of the first comparator, and then obtains an N-bit quantization code Dlo through an error filtering circuit; at this time, the N-bit quantization code Dlo is 1-bit serial data, which enters the serial shift register in sequence through the low-speed path output port of the path selection circuit, and the output of the serial shift register enters the serial-to-parallel conversion circuit to obtain an M-bit parallel quantization code Dlp, which is output to the second data input port of the M-bit buffer output circuit. The M-bit buffer output circuit obtains the final M-bit load quantization code Dlot under the control of the control clock Ck1.

8. The high-efficiency gate drive circuit according to claim 1 is characterized in that after the chip power pin VDD meets the power-on requirement, the high-voltage bandgap reference first works normally and provides a 1.2V reference voltage Vref; the input receiving circuit receives the external input pulse and converts it into a logic level VIN with a high level of VCC, and then the logic level VIN is modulated with the oscillation clock generated by the oscillator to obtain a modulated pulse signal DX; the error amplifier amplifies the external sampling current to obtain a current input signal CSIN, and the current input signal CSIN enters the overcurrent protection circuit and obtains the overcurrent protection signal OCP after comparison; the control logic performs logical processing on the overcurrent protection signal OCP, the over-temperature protection signal OTP, the undervoltage protection signal UVLO and the modulated pulse signal DX, and outputs an output control pulse Din for output driving; the output control pulse Din is then buffered and driven by the high-efficiency output driving circuit to obtain an output driving signal, which is output through the output driving switch pin VO.