CN116111816A - High efficiency gate drive circuit - Google Patents

Abstract

The invention discloses a high-efficiency gate driving circuit which is used for driving a power switch SiC MOSFET. The circuit comprises: the device comprises an input receiving circuit, a high-voltage band-gap reference, an internal power supply generating circuit, a high-efficiency output driving circuit, an overcurrent protection circuit, an overtemperature protection circuit, an undervoltage protection circuit, an oscillator OSC, a waveform modulation circuit, control logic and an error amplifier. Still include 5 external pins, respectively: the chip power supply pin VDD, the external input pulse pin INX, the current detection pin CS, the output drive switch pin VO, and the ground pin GND. The high-efficiency gate drive provided by the invention improves the functional reliability of the whole chip by adopting a plurality of chip abnormal state monitoring and protecting circuits; the invention also adopts an output driving circuit with high output efficiency, and provides the optimal output driving current through self-adaptive adjustment in real time by self-adaptive identification of the load size and the frequency of the input control pulse, thereby realizing the aim of improving the efficiency.

Description

High Efficiency Gate Drive Circuit

technical field

The invention relates to a high-efficiency gate drive circuit for power devices in switching power supplies, which belongs to the technical field of integrated circuits.

Background technique

In recent years, various portable electronic products emerge in an endless stream, and the corresponding power consumption is also increasing. Therefore, new requirements are put forward for the conversion efficiency and power consumption of the power supply. Most of the early power supplies were powered by linear power supplies. The linear power supply has a simple structure, good stability, and better anti-noise performance. However, when the linear regulated power supply is working, the adjustment tube will generate a lot of heat, so the efficiency is not high and the loss is serious. In order to Eliminating the generated heat requires the use of larger heat sinks around the adjustment tube, and the linear regulated power supply generally requires the use of a power frequency transformer, coupled with the heat sink of the adjustment tube, resulting in a large volume of the linear regulated power supply and low power efficiency. Generally, the maximum can only reach 50%. For small and portable electronic products, linear power supplies can no longer meet their power requirements, so people have gradually turned to switching power supplies to meet new power requirements. The biggest advantage of switching power supply is high conversion efficiency, small size and light weight, which reduces the cost and provides convenience for charging small devices, and switching power supply has various open circuit / short circuit / over temperature and overvoltage protection functions, This ensures the safety of our use of electronic products. Compared with the linear power supply that works in a linear state, the switching power supply controls the output voltage by turning on and off the power switch tube.

Common power devices include bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), metal-oxide semiconductor field effect transistors (MOSFETs), and junction field effect transistors (JFETs). As the main power device in switching power converters, Si IGBT technology is becoming mature, but its performance is gradually approaching the theoretical limit of Si material. It is the general trend to seek power devices with better performance. With the rise of wide bandgap semiconductor devices, SiC MOSFET has emerged in the field of power electronics by virtue of its advantages of high frequency, high voltage resistance, high temperature resistance, and strong heat dissipation, and has the potential to replace Si IGBT. In order to improve the efficiency of the switching power supply, the loss of the power switching device cannot be ignored, so it is necessary to optimize its gate drive circuit.

In practical applications, the pulse control signal required by the SiC MOSFET switch tube is a 15V-25V high-current signal. In order to prevent the gate output drive current from causing damage to the gate terminal of the external power switch SiC MOSFET to be driven, usually at the output terminal of the gate drive circuit Connect a resistor in series to suppress the overshoot effect of the gate voltage. When the equivalent capacitance at the gate terminal is large, the series connection protection resistor needs to be relatively small, otherwise, the series connection protection resistance needs to be relatively large. A relatively large series connection protection resistor will bring two problems: one is that the switching loss on the resistor becomes larger, which reduces the efficiency of the driving circuit; the other is that the driving delay is increased, and the switching frequency of the system is finally reduced. In addition, the use of series protection resistors will increase the design workload of design engineers and reduce the reliability of the whole system.

Contents of the invention

In order to improve the efficiency, the present invention proposes a high-efficiency gate drive circuit whose drive capability can be adaptively adjusted. The circuit can adaptively identify the load size and the frequency of the input control pulse, and adjust the output drive current size adaptively.

The structure of the high-efficiency gate drive circuit provided by the present invention includes: an input receiving circuit, a high-voltage bandgap reference, an internal power supply generating circuit, a high-efficiency output drive circuit, an overcurrent protection circuit, an overtemperature protection circuit, an undervoltage protection circuit, an oscillation device, waveform modulation circuit, control logic and error amplifier; also includes 5 external pins, namely: chip power supply pin VDD, external input pulse pin INX, current detection pin CS, output drive switch pin VO, ground pin GND;

The input terminal of the input receiving circuit is connected to the external input pulse pin INX, the output terminal of the input receiving circuit is connected to the input terminal of the waveform modulation circuit, the input terminal of the waveform modulation circuit is also connected to the oscillator, and the output terminal of the waveform modulation circuit outputs modulation The pulse signal DX; the input terminal of the error amplifier is connected to the current detection pin CS, and the error amplifier amplifies the external sampling current to obtain the current input signal CSIN, which is connected to the overcurrent protection circuit; the high-voltage bandgap reference is used to provide the reference voltage Vref; The internal power supply generating circuit is used to generate the internal power supply voltage VCC and various bias signals according to the reference voltage Vref for use by other circuits in the chip; Current protection signal OCP, over-temperature protection signal OTP, under-voltage protection signal UVLO; the over-current protection signal OCP, over-temperature protection signal OTP, under-voltage protection signal UVLO and modulation pulse signal DX are all connected to the control logic, and obtained after processing Output control pulse Din; the output control pulse Din is connected to the high-efficiency output drive circuit, which is buffered and driven by the high-efficiency output drive circuit to obtain the output drive signal and connected to the output drive switch pin VO;

After the chip power supply pin VDD meets the power-on requirements, the high-voltage bandgap reference first works normally and provides a 1.2V reference voltage Vref; the input receiving circuit receives an external input pulse and converts it into a high level logic level VIN of VCC , and then the logic level VIN is modulated with the oscillation clock generated by the oscillator to obtain the modulated pulse signal DX; the error amplifier amplifies the external sampling current to obtain the current input signal CSIN, and the current input signal CSIN enters the overcurrent protection circuit and is compared to obtain the overcurrent protection Signal OCP; the control logic performs logic processing on the overcurrent protection signal OCP, overtemperature protection signal OTP, undervoltage protection signal UVLO and modulation pulse signal DX, and outputs the output control pulse Din for output driving; the output control pulse Din is then passed through the high The efficiency output driving circuit buffers and drives to obtain an output driving signal, which is output through the output driving switch pin VO.

Specifically, the over-temperature protection circuit includes: NPN transistor Q61, NPN transistor Q60, resistor R61, resistor R62, PMOS transistor P60, inverter Inv60, capacitor C60 and Schmitt trigger Schmitt; the collector of NPN transistor Q61 Connect to the internal power supply voltage VCC, the emitter of the NPN transistor Q61 is connected to the upper end of the resistor R61, the base of the NPN transistor Q61 is connected to the reference voltage Vref; the lower end of the resistor R61 is connected to the upper end of the resistor R61 and the base of the NPN transistor Q60, and the collector of the NPN transistor Q60 Connect the upper end of the capacitor C60, the output end of the inverter Inv60, the drain of the PMOS transistor P60, and the input end of the Schmitt trigger Schmitt; the source of the PMOS transistor P60 is connected to the internal power supply voltage VCC, and the gate of the PMOS transistor P60 is connected to the bias voltage Vb6; the signal Ctrl connected to the input terminal of the inverter Inv60 is the global control signal of the chip; the output terminal of the Schmitt trigger Schmitt outputs the over-temperature protection signal OTP; the lower end of the resistor R62, the lower end of the capacitor C60 and the emission of the NPN transistor Q60 Both poles are connected to the ground voltage GND.

Specifically, the high-efficiency output drive circuit includes: a P-end output adjustable buffer drive circuit, an N-end output adjustable buffer drive circuit, a sampling switch SW, a working sequence generation circuit, a load comparison quantization circuit, and a drive current selection circuit;

The output control pulse Din is simultaneously connected to the P terminal output adjustable buffer drive circuit, the N terminal output adjustable buffer drive circuit and the data input terminal of the working sequence generation circuit; the P terminal output adjustable buffer drive circuit and the N terminal output adjustable buffer drive circuit The drive signal output terminal of the circuit is connected as the output terminal of the output drive signal, and is connected to the input terminal of the load comparison quantization circuit through the sampling switch SW; the working sequence generation circuit tracks and judges the frequency of the output control pulse Din to obtain the frequency discrimination code Dfin, and generate high-level non-overlapping control clock Ck1 and control clock Ck2; wherein the frequency discrimination code Dfin is connected to the load comparison quantization circuit, the control clock Ck1 is connected to the load comparison quantization circuit and the drive current selection circuit, and the control clock Ck2 is connected to to the drive current selection circuit; the output drive signal enters the load comparison and quantization circuit after being sampled by the sampling switch SW, and the load quantization code Dlot is obtained under the control of the reference voltage Vr, the control clock Ck1 and the frequency discrimination code Dfin, and is connected to the drive current selection circuit; The load quantization code Dlot, the control clock Ck1 and the control clock Ck2 enter the drive current selection circuit at the same time to obtain n switch control signals Kp1~Kpn and n switch control signals Kn1~Knn; the switch control signals Kp1~Kpn are respectively connected to the P terminal output n switch signal input terminals of the adjustable buffer drive circuit, and switch control signals Kn1 to Knn are respectively connected to the n switch signal input terminals of the P terminal output adjustable buffer drive circuit; n is any positive integer;

After the power supply voltage is powered on, the working sequence generation circuit tracks and judges the frequency of the output control pulse Din to obtain the frequency discrimination code Dfin, and generates the control clock Ck1 and the control clock Ck2; when the Ck1 clock is valid, the load comparison and quantization circuit will be based on the sampled The state of the output drive signal VO, reference voltage Vr and frequency discrimination code Dfin sampled by the switch SW first generates a set of default load quantization code Dlot_pre and enters the drive current selection circuit, and the drive current selection circuit will output a set of default switch control Signals Kp1_pre～Kpn_pre and switch control signals Kn1_pre～Knn_pre, the output driving signal will drive the external load under the action of the default driving current and make the voltage of the output driving signal gradually increase; when the clock of Ck1 ends, the load quantization code Dlot_pre will It will be adjusted according to the size of the output drive signal at this time, and the adjusted load quantization code Dlot_lock will be obtained and kept unchanged; when the Ck2 clock is valid, the drive current selection circuit will output a new set of switch control signals according to the load quantization code Dlot_lock Kp1_lock～Kpn_lock and switch control signal Kn1_lock～Knn_lock, the output driving signal will drive the external load under the new driving current and make the voltage of the output driving signal rise rapidly to the voltage VCC; when the Ck2 clock ends, the load The quantization code Dlot will be cleared, the switch control signals Kp1~Kpn output by the drive current selection circuit will be cleared synchronously, and the n P-terminal output inverter control switches in the P-terminal output adjustable buffer drive circuit will be turned off. At the same time, the switch control signals Kn1~Knn output by the drive current selection circuit are valid, and the n N-terminal output inverter control switches in the N-terminal output adjustable buffer driving circuit are turned on, and the output driving signal will be quickly pulled from the voltage VCC to the ground. Voltage GND, thus turning off the external load power device.

Specifically, the P-terminal output adjustable buffer drive circuit includes: an inverter chain, the input terminal of the inverter chain is connected to output the control pulse Din, and the output terminals of the inverter chain are respectively outputted through n P-terminals to invert The controller control switch is connected to the input terminals of the n P-terminal output inverters, the output terminals of the n P-terminal output inverters are respectively connected to the gate terminals of the n P-terminal output PMOS transistors, and the n P-terminal output PMOS transistors are connected to each other. The source terminal is connected to the internal power supply voltage VCC at the same time; n P-terminal output inverter control switches are respectively controlled by switch control signals Kp1~Kpn;

The N-terminal output adjustable buffer driving circuit includes: an inverter chain, the input end of the inverter chain is connected to the output control pulse Din, and the output ends of the inverter chain respectively pass through n N-terminal output inverter control switches Connect the input terminals of n N-terminal output inverters, the output terminals of n N-terminal output inverters are respectively connected to the gate terminals of n N-terminal output NMOS transistors, and the source terminals of n N-terminal output NMOS transistors are connected to Ground voltage GND; n N-terminal output inverter control switches are respectively controlled by switch control signals Kn1~Knn;

The drain ends of the n P-terminal output PMOS transistors are connected together with the drain ends of the n N-terminal output NMOS transistors, and one side is connected to the input end of the load comparison and quantization circuit through the sampling switch SW, and is also connected to the output drive switch lead. Foot VO.

Specifically, the working sequence generation circuit includes: an oscillator, a pulse width counter, a counting cycle selection circuit, a comprehensive counter, a first clock waveform generation circuit and a second clock waveform generation circuit; the OSC signal generated by the oscillator is connected to A pulse width counter and a comprehensive counter, the output control pulse Din is connected to the pulse width counter and the comprehensive counter at the same time; the pulse width counter counts the pulse time width of the output control pulse Din according to the OSC signal, and the pulse time width obtained by counting Carry out tracking discrimination and comparative quantization output frequency discrimination code Dfin; Frequency discrimination code Dfin is connected to counting period selection circuit and produces comprehensive counter mode selection signal sel0; Said comprehensive counter produces clock control according to mode selection signal sel0, OSC signal and output control pulse Din Signal ct1 and clock control signal ct2; finally, the clock control signal ct1 and clock control signal ct2 are respectively connected to the first clock waveform generation circuit and the second clock waveform generation circuit, and the first clock waveform generation circuit and the second clock waveform generation circuit respectively output The final control clock Ck1 and control clock Ck2.

Specifically, the load comparison quantization circuit includes: quantization voltage generation circuit, high and low speed mode selection circuit, N comparators, error filtering circuit, path selection circuit, serial shift register, serial-to-parallel conversion circuit and M-bit buffer output circuit; the input terminal of the quantization voltage generation circuit is connected to the reference voltage Vr, the control clock Ck1 and the mode control signal mod output by the high and low speed mode selection circuit, and the quantization voltage generation circuit converts the reference voltage Vr to N under the control of the control clock Ck1 Quantized reference voltages Vr1~VrN are respectively connected to the reference voltage input terminals of N comparators; the detection voltage input terminals of N comparators are all connected to the output drive switch pin VO, and the N comparators respectively connect the output drive signal with N quantized reference voltages Vr1-VrN are compared, and N-bit quantized values D1-DN are output; then N-bit quantized values D1-DN enter the error filtering circuit to output N-bit quantized code Dlo; the high and low speed mode selection circuit is based on the frequency discrimination code The size of Dfin, the output mode control signal mod, thereby changing the mode of the load comparison quantization circuit, to change the speed and power consumption of the load comparison quantization circuit, the mode control signal mod is respectively connected to the quantization voltage generation circuit, N comparators, error filtering circuit, path selection circuit; said path selection circuit selects the signal path of N-bit quantization code Dlo under the control of mode control signal mod; the high-speed path output port of said path selection circuit is N-bit parallel data, directly output To the first data input port of the M-bit buffer output circuit, the low-speed path output port of the path selection circuit is 1-bit serial data, which is first connected to the serial shift register, and the output of the serial shift register enters the serial-to-parallel conversion circuit. Obtain M-bit parallel quantization code Dlp, be connected to the second data input port of M-bit buffer output circuit; M-bit buffer output circuit outputs final M-bit load quantization code Dlot under the control of control clock Ck1; Wherein, M and N All are integers greater than 1.

Specifically, the load comparison quantization circuit includes a high-speed mode and a low-speed mode;

The working mode of the high-speed mode is: the quantization voltage generation circuit simultaneously outputs N quantization reference voltages under the control of the control clock Ck1, and N comparators respectively compare the output drive signal with the N quantization reference voltages at the same time, and output N-bit parallel output The quantized value D1～DN, and then an N-bit quantization code Dlo is obtained through the error filtering circuit; at this time, the N-bit quantization code Dlo is N-bit parallel data, and the high-speed channel output port passing through the channel selection circuit is directly output to the M-bit buffer output circuit The first data input port of the M-bit buffer output circuit outputs the final M-bit load quantization code Dlot under the control of the control clock Ck1;

The working mode of the low-speed mode is: only the first comparator among the N comparators is working, and the remaining N-1 comparators are dormant. N quantized reference voltages are output, the first comparator compares the output drive signal with the N quantized reference voltages in chronological order, and the output port of the first comparator sequentially outputs N-bit serial output in chronological order The quantized values D1~DN are then passed through the error filter circuit to obtain the N-bit quantization code Dlo; at this time, the N-bit quantization code Dlo is 1-bit serial data, which will be sequentially entered into the serial shift register through the low-speed channel output port of the channel selection circuit, The output of the serial shift register enters the serial-to-parallel conversion circuit to obtain the M-bit parallel quantization code Dlp, which is output to the second data input port of the M-bit buffer output circuit, and the M-bit buffer output circuit obtains the final output under the control of the control clock Ck1. The M-bit load quantization code Dlot.

The advantages of the present invention are: the provided high-efficiency gate drive improves the reliability of the overall chip function by using a variety of chip abnormal state monitoring and protection circuits; on the other hand, the output drive part of the present invention adopts a special output drive with high output efficiency The circuit can adaptively identify the load size and the frequency of the input control pulse, and provide the optimal output drive current through real-time adaptive adjustment to achieve the goal of improving efficiency.

Description of drawings

Fig. 1 is a block diagram of the overall circuit structure of the present invention.

Fig. 2 is a schematic diagram of a high-voltage bandgap reference circuit in an embodiment of the present invention.

Fig. 3 is a schematic diagram of an internal power generation circuit in an embodiment of the present invention.

FIG. 4 is a schematic diagram of the error amplifier circuit in the embodiment of the present invention.

Fig. 5 is a schematic diagram of an over-temperature protection circuit in an embodiment of the present invention.

FIG. 6 is a schematic diagram of an undervoltage protection circuit in an embodiment of the present invention.

FIG. 7 is a schematic diagram of an overcurrent protection circuit in an embodiment of the present invention.

FIG. 8 is a structural block diagram of a high-efficiency output driving circuit in an embodiment of the present invention.

FIG. 9 is a schematic diagram of working waveforms of the high-efficiency output drive circuit of the present invention.

FIG. 10 is a schematic diagram of a P-end output adjustable buffer driving circuit in an embodiment of the present invention.

FIG. 11 is a schematic diagram of an N-terminal output adjustable buffer driving circuit in an embodiment of the present invention.

FIG. 12 is a block diagram of a working sequence generating circuit in an embodiment of the present invention.

Fig. 13 is a block diagram of a load comparison and quantization circuit in an embodiment of the present invention.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings and examples.

As shown in Figure 1, the high-efficiency gate drive circuit of the present invention includes: input receiving circuit 1, high-voltage bandgap reference 2, internal power supply generating circuit 3, high-efficiency output driving circuit 4, over-current protection circuit 5, over-temperature Protection circuit 6 , undervoltage protection circuit 7 , oscillator (OSC) 8 , waveform modulation circuit 9 , control logic 10 and error amplifier 11 . The high-efficiency gate drive circuit has 5 external pins: VDD in the figure is a chip power pin, INX is an external input pulse pin, CS is a current detection pin, VO is an output drive switch pin, and GND is a ground lead foot. In the following descriptions, the pin name is sometimes used to indicate the signal name of the input or output of the pin.

After the chip power pin VDD meets the power-on requirements, the high-voltage bandgap reference 2 works normally first, and provides a 1.2V reference voltage Vref. The internal power generating circuit 3 generates an internal power voltage VCC and various bias signals according to the reference voltage Vref. The over-current protection circuit 5 , the over-temperature protection circuit 6 , and the under-voltage protection circuit 7 respectively generate an over-current protection signal OCP, an over-temperature protection signal OTP, and an under-voltage protection signal UVLO according to the reference voltage Vref. The internal power supply voltage VCC and various bias signals are used by other circuit modules in the chip.

The input receiving circuit 1 receives the external input pulse INX and converts it into a logic level VIN whose high level is VCC, and then modulates VIN with the oscillation clock generated by the oscillator 8 to obtain a modulated pulse signal DX. The error amplifier 11 amplifies the external sampling current CS to obtain a current input signal CSIN, and the current input signal CSIN enters the overcurrent protection circuit 5 to obtain an overcurrent protection signal OCP after comparison. The over-current protection signal OCP, over-temperature protection signal OTP, under-voltage protection signal UVLO and modulation pulse signal DX are all connected to the control logic 10 and processed to obtain the output control pulse Din for output driving. The output control pulse Din is buffered and driven by the high-efficiency output drive circuit 4 to obtain the output drive signal VO.

The above method of modulating the logic level VIN and the oscillation clock to obtain the modulated pulse signal DX can be realized by using existing conventional digital modulation technology.

Fig. 2 is a circuit diagram of an embodiment of the high-voltage bandgap reference 2 of the present invention. The characteristics of the circuit reference in the chip circuit will greatly affect the performance of the entire chip, and an accurate and reliable reference is a strong guarantee for the normal operation of the chip. The core structure of the circuit is a resistor R31, a resistor R32, a transistor Q31, a transistor Q32, a PMOS transistor P31 and a PMOS transistor P32. MOS transistors P34~P36 are high-voltage MOS transistors that can withstand high voltage between source and drain. After adding MOS transistors P34~P36, since there is an isolation between the power supply and the output reference voltage Vref, the power supply suppression capability of the entire circuit will be reduced. Significantly increased. The addition of the MOS transistor P33 is to suppress the change of Vref caused by the change of the bias current.

The circuit in Fig. 2 has two feedback loops, feedback loop 1 from the bottom of MOS transistor N31 to transistor Q32 and feedback loop 2 from the top of MOS transistor N31 to PMOS transistor P31 and PMOS transistor P32. The function of the feedback loop 1 is to provide base current for the transistor Q31 and the transistor Q32, and at the same time form a negative feedback to ensure the stability of Vref. The second feedback loop is due to the existence of the MOS transistors P34-P36, the change of the base voltage of the MOS transistor N31 will directly affect the source voltage of the PMOS transistor P31 in the same direction through the MOS transistor N31. Therefore, the MOS transistor P33 is added here to offset the influence of the change of the base voltage of the MOS transistor N31 on the source voltage of the PMOS transistor P31. Assuming that the base voltage of MOS transistor N31 increases, due to the effect of MOS transistor N31, the drain voltage of MOS transistor N31 will decrease, and the source voltage of PMOS transistor P31 will also decrease; at the same time, due to the effect of PMOS transistor P31, the source voltage of PMOS transistor P31 will decrease. The electrode voltage will become larger, and the size of the MOS transistor N31 and the MOS transistor P33 is properly selected. The combined effect of the two makes the source voltage of the PMOS transistor P31 not be affected by the base voltage of the MOS transistor N31. In addition, the function of the capacitor C31 is to compensate the capacitor, so as to provide a better phase margin for the second feedback loop. R33 represents a resistor divider network whose function is to generate some reference voltage which is smaller than the bandgap reference voltage.

As shown in FIG. 3 is a circuit diagram of an embodiment of the internal power supply generating circuit 3 of the present invention. The reference voltage obtained from the high-voltage bandgap reference 2 is only 1.2V, and the working voltage VCC required by other working modules in the chip is 5V. The bandgap reference circuit alone cannot meet the power supply requirements of other modules in the chip, so a A voltage regulator is used to adjust the voltage to meet the needs of other modules. The circuit in Figure 3 can generate multiple chip internal power supply voltages with slight differences. Since the gate and drain voltages of MOS transistors N41, N42, N43, and N44 are the same, we can draw a conclusion: if the MOS transistors N41~N44 are below All with the same load, then the four values of VCC1, VCC2, VCC3 and VCC4 are all equal; if the loads are not equal, then the voltage difference between these values is determined by the size of the load. Whoever carries the bigger load has the bigger voltage.

In this embodiment, VCC1 is used for some relatively static modules, and VCC2-VCC4 are used for some dynamic modules. Generally speaking, VCC1 carries the largest load. However, this may cause a problem. We are not sure about the load carried by each voltage. If the load carried by VCC2~VCC4 is much larger than VCC1, a large voltage difference will be generated, which will cause some Logic circuits don't work properly. In order to solve this problem, three PMOS transistors can be added between VCC1 and VCC2~VCC4 to form a voltage limiting circuit. When VCC2~VCC4 is greater than VCC1 and exceeds a threshold voltage, the corresponding MOS transistors P42~P44 will be turned on. Make the voltage of VCC2-VCC4 drop below VCC1. This is not only simple and convenient, but also does not need to add an additional level conversion circuit, which saves the area of the chip.

FIG. 4 is a circuit diagram of an embodiment of the error amplifier 11 of the present invention, which adopts a two-stage operational amplifier structure. The first-stage amplifier adopts a folded cascode structure, and the MOS transistors N53 and N54 are the input pairs of the first stage, so that the error amplifier 11 has a higher bandwidth and open-loop gain. Compared with the sleeve-type cascode The gate operational amplifier has a larger input common-mode level, a larger output swing, and the input and output are easily shorted to form a proportional operation circuit. The second-stage amplifier is connected to a common single-ended common-source circuit, which is composed of MOS transistors N57 and P58 to increase the output swing; at the same time, in order to improve the phase margin of the amplifier, the output stage of the second stage is connected in series with the output stage of the first stage. Resistor R53 and capacitor C51 form Miller compensation to increase the phase margin of the loop, and push the output point of the first stage amplifier to low frequency to become the dominant pole. If the difference between the feedback signal and the reference voltage is too large, then the error amplifier 11 will work in the state of the comparator, that is, when the sampled CS is much higher than the reference voltage Vref, the error amplifier 11 will output a high level, otherwise the output will be low level. If the difference between the feedback signal and the reference voltage is not large, then the error amplifier 11 will work in a linear amplification state.

FIG. 5 is a circuit diagram of an embodiment of the over-temperature protection circuit 6 of the present invention. When the chip is working, especially when the frequency increases, it will heat up, so there must be a thermal protection circuit inside the chip, otherwise the chip may burn out due to excessive temperature. The thermal protection circuit must be extremely sensitive to temperature. The general thermal protection circuit uses the base-emitter voltage of the bipolar transistor to change with temperature sensitivity to generate an over-temperature protection signal. Therefore, the thermal protection circuit design of this chip is also based on This characteristic of the triode. When the operating temperature of the chip exceeds the set temperature threshold, the over-temperature protection circuit 6 outputs a protection signal to stop the chip from working, and when the temperature drops to a certain value, the chip restarts and enters the normal working state.

As shown in Fig. 5, the over-temperature protection circuit 6 used in this embodiment includes: NPN transistor Q61, NPN transistor Q60, resistor R61, resistor R62, PMOS transistor P60, inverter Inv60, capacitor C60 and Schmitt trigger Schmitt. The collector of the NPN transistor Q61 is connected to the internal power supply voltage VCC, the emitter of the NPN transistor Q61 is connected to the upper end of the resistor R61, and the base of the NPN transistor Q61 is connected to the reference voltage Vref. The lower end of the resistor R61 is connected to the upper end of the resistor R61, and also connected to the base of the NPN transistor Q60. The collector of the NPN transistor Q60 is connected to the upper end of the capacitor C60, the output end of the inverter Inv60, the drain of the PMOS transistor P60 and the input end of the Schmitt trigger Schmitt. The source of the PMOS transistor P60 is connected to the internal power supply voltage VCC, and the gate of the PMOS transistor P60 is connected to the bias voltage Vb6. The input terminal Ctrl signal of the inverter Inv60 is a global chip control signal, which may be a power-on reset signal or other control signals; the output terminal of the Schmitt trigger Schmitt is the over-temperature protection signal OTP. The lower end of the resistor R61, the lower end of the capacitor C60 and the emitter of the NPN transistor Q60 are all connected to the ground voltage GND.

The Vbe (base-emitter voltage) of the transistor Q61 has a negative temperature coefficient. When the chip works normally, the Vref voltage is lower than the Vbe turn-on voltage of the transistor Q61, so the transistor Q61 will not be turned on. When the temperature rises, the Vbe of the transistor Q61 decreases, and the voltage on the resistors R61 and R62 changes with the temperature at the same time. When the Vbe drops to the Vref voltage, the transistor Q61 will be turned on. At this time, the voltage at point A rises until it rises to the transistor Q60 When the conduction voltage is higher, the transistor Q60 will be turned on, and the collector voltage of the transistor Q60 (voltage at point B) will become a low level. Afterwards, the low level is triggered from low level to high level OTP through the Schmitt delay trigger of the Schmitt trigger, and the OTP at this time is the overheating protection signal. Here, the Schmidt trigger Schmidt hysteresis loop design is used, which can effectively prevent the problem that the chip cannot work normally due to thermal shock.

FIG. 6 is an embodiment of the undervoltage protection circuit 7 of the present invention. If the output voltage is lower than the rated value, the load will be damaged, and the output voltage must be limited, so the undervoltage protection circuit 7 is designed. According to the chip design index, the undervoltage protection is triggered when VDD is lower than 6.5V. First, the voltage division of the VDD pin is detected through the negative input terminal of a two-stage operational amplifier comparator. When the amplifier detects that the voltage division of VDD is greater than the set reference voltage, the output level of the comparator latches the SR through an inverter. The device latch is set to "1" to generate the UVLO signal.

FIG. 7 is an embodiment of the overcurrent protection circuit 5 of the present invention. If the external feedback resistor of the current detection pin CS is short-circuited or open-circuited, the CSIN signal will be abnormal and cannot be sampled and output normally. Therefore, an open-circuit and short-circuit protection circuit is designed inside the chip. Its working principle is as follows: when the Ctrl signal rises, it means that the primary side is turned on, and the transformer transmits energy to the secondary winding. At this time, the internal power supply voltage VCC charges the capacitor C through PCH1, reaching the forward threshold voltage of the Schmitt trigger. , the protection signal OCP is not triggered at this time. When the Ctrl signal disappears, the capacitor C discharges to the ground through PCH2. After a short delay, the capacitor voltage drops to the inverting threshold voltage of the Schmitt trigger, and the OCP will be triggered at this time.

For the realization of the output driving circuit, the prior art usually adopts cascaded progressive amplification inverter chains. After the traditional output drive circuit is designed and finalized, the output drive capability of the output drive circuit will be solidified. In practical applications, in order to prevent the VO output current from causing damage to the gate terminal of the external power switch MOSFET to be driven, a resistor is usually connected in series with the VO output terminal to suppress the influence of the gate terminal voltage overshoot. When the equivalent capacitance at the gate terminal of the MOSFET is large, the series connection protection resistor needs to be relatively small, otherwise a large series connection protection resistance is required. A relatively large series connection protection resistor will bring two problems. One is that the switching loss on the resistor becomes larger, which reduces the efficiency of the drive circuit; the other is that the drive delay is increased, which ultimately reduces the switching frequency of the system. In addition, the use of series protection resistors will increase the design workload of design engineers and reduce the reliability of the whole system. Aiming at the above problems, the present invention designs a high-efficiency output driving circuit whose driving capability can be adaptively adjusted. The circuit can adaptively adjust the magnitude of the driving current by adaptively identifying the magnitude of the load and the frequency of the input control pulse.

As shown in FIG. 8, the high-efficiency output drive circuit 4 of the present invention includes: a P-end output adjustable buffer drive circuit 41, an N-end output adjustable buffer drive circuit 42, a sampling switch SW, a working sequence generation circuit 43, and a load comparison quantization circuit. circuit 44 and drive current selection circuit 45.

The output control pulse Din is simultaneously connected to the data input terminals of the P-terminal output adjustable buffer driver circuit 41 , the N-terminal output adjustable buffer driver circuit 42 and the working timing generation circuit 43 . The P-end output adjustable buffer drive circuit 41 is connected to the drive signal output end of the N-end output adjustable buffer drive circuit 42, as the output end of the output drive signal, connected to the output drive switch pin VO, and connected to the left side of the sampling switch SW Side: the output drive signal enters the load comparison and quantization circuit 44 after being sampled by the sampling switch SW, and obtains the load quantization code Dlot under the control of the reference voltage Vr, the control clock Ck1 and the frequency discrimination code Dfin and enters the drive current selection circuit 45. The working sequence generation circuit 43 tracks and judges the frequency of the output control pulse Din to obtain the Din frequency discrimination code Dfin, and generates high-level non-overlapping control clocks Ck1 and Ck2. The load quantization code Dlot, the control clocks Ck1 and Ck2 enter the drive current selection circuit 45 at the same time to obtain n control signals Kp1-Kpn (to control the switches in the P-end output adjustable buffer drive circuit 41) and n switch control signals Kn1-Knn (controlling the switches in the N terminal output adjustable buffer drive circuit 42); the switch control signals Kp1～Kpn are respectively connected to the n switch signal input terminals of the P terminal output adjustable buffer drive circuit 41, and the switch control signals Kn1～Knn are respectively connected to Output the n switch signal input terminals of the adjustable buffer driving circuit 41 to the P terminal. where n is any positive integer.

FIG. 9 is a schematic diagram of VO output waveforms of the above-mentioned high-efficiency output drive circuit 4 under three different loads. The waveforms correspond to loads of 0.5nF, 1nF, and 1.5nF from top to bottom. After the power supply voltage is powered on, the working sequence generation circuit 43 tracks and judges the frequency of the output control pulse Din, obtains the frequency discrimination code Dfin, and generates control clocks Ck1 and Ck2. When the Ck1 clock is valid, the load comparison and quantization circuit 44 will first generate a set of default load quantization codes Dlot_pre and enter the drive current selection according to the output drive signal VO sampled by the sampling switch SW, the reference voltage Vr and the state of the frequency discrimination code Dfin Circuit 45, the drive current selection circuit 45 will output a set of default switch control signals Kp1_pre～Kpn_pre (control the switches in the P terminal output adjustable buffer drive circuit 41) and Kn1_pre～Knn_pre (control the N terminal output adjustable buffer drive circuit 42), the output drive signal VO will drive the external load under the action of the default drive current Iout_pre and gradually increase the voltage of the output drive signal VO; when the Ck1 clock ends, the load quantization code Dlot_pre will be based on this When the size of the output drive signal VO is adjusted, the adjusted load quantization code Dlot_lock is obtained and remains unchanged; when the Ck2 clock is valid, the drive current selection circuit 45 will output a group of new switch control signals according to the load quantization code Dlot_lock Kp1_lock～Kpn_lock (controlling the switch in the adjustable buffer drive circuit 41 output by the P terminal) and Kn1_lock～Knn_lock (controlling the switch in the adjustable buffer drive circuit 42 output by the N terminal), the output drive signal VO will be at the new drive current Iout_lock Under the action, the external load is driven and the voltage of the output drive signal VO rises rapidly to the power supply voltage VCC; when the Ck2 clock ends, the load quantization code Dlot will be cleared, and the output switch control signal Kp1 of the drive current selection circuit 45 ~Kpn will be cleared synchronously (turn off the switch in the output adjustable buffer driving circuit 41 of the P terminal), and simultaneously open the switch control signals Kn1～Knn (turn on the switch in the adjustable buffer driving circuit 42 of the N terminal output), and output The driving signal VO will be quickly pulled from the power supply voltage VCC to the ground voltage GND, thereby turning off the external load power device.

In the above working process, when the Ck1 clock is valid, the output driving signal VO will drive the external load under the action of the default driving current Iout_pre and gradually increase the voltage of the output driving signal VO. For different external loads, the output drive signal VO will produce different dv/dt changes. For a fixed output driving current Iout_pre, it is obvious that the larger the driven load capacitance is, the lower the rising slope of the output driving signal VO is, and the voltage of the output driving signal VO at the end of the Ck1 clock is inversely proportional to the load capacitance, that is, when the load is 0.5nF The output drive signal VO voltage should be 3 times the output drive signal VO voltage when the load is 1.5nF. Therefore, under a fixed driving current condition, the size of the output driving load can be determined according to the voltage of the output driving signal VO at the end of the Ck1 clock, and the size of the output driving load is quantified by the load comparison quantization circuit 44 to obtain the load Quantization code Dlot_lock. When the Ck2 clock is valid, the drive current selection circuit 45 will output a set of new switch control signals according to the load quantization code Dlot_lock, and the output drive signal VO will drive the external load under the action of the new drive current Iout_lock and make the output drive The voltage of signal VO rapidly rises to power supply voltage VCC. When the load quantization code Dlot_lock shows that the external load is relatively large, the drive current selection circuit 45 will output a group of larger switch control signals, so that the output drive signal VO outputs a larger output drive current Iout_lock; when the load quantization code Dlot_lock shows When the external load is small, the driving current selection circuit 45 will output a group of small switching control signals, so that the output driving signal VO outputs a small output driving current Iout_lock.

FIG. 10 is a circuit diagram of an embodiment of the P-end output adjustable buffer driving circuit 41 of the present invention. The P-terminal output adjustable buffer drive circuit 41 includes: an inverter chain, n P-terminal output inverter control switches Sp1-Spn, n P-terminal output inverters Invpk_1-Invpk_n, and n P-terminal output inverters. PMOS transistors Mp1-Mpn. The input end of the inverter chain is connected to the output control pulse Din, and the output end of the inverter chain is respectively connected to n P-terminals to output inverter control switches Sp1-Spn and connected to n P-terminals to output the input ends of the inverters Invpk_1-Invpk_n , that is: the control switch Sp1 is connected to the input terminal of the inverter Invpk_1, the control switch Sp2 is connected to the input terminal of the inverter Invpk_2, and the control switch Spn is connected to the input terminal of the inverter Invpk_n; the n P terminals output the inverter Invpk_1 The output terminals of ~Invpk_n are respectively connected to n P terminals to output the gate terminals of the PMOS transistors Mp1~Mpn, that is, the output of the inverter Invpk_1 is connected to the gate terminal of the PMOS transistor Mp1, and the output of the inverter Invpk_2 is connected to the gate terminal of the PMOS transistor Mp2 At the gate terminal, the output of the inverter Invpk_n is connected to the gate terminal of the PMOS transistor Mpn; the source terminals of the n P-terminal output PMOS transistors Mp1-Mpn are simultaneously connected to the power supply voltage VCC. The n P-terminal output inverter control switches Sp1-Spn are respectively controlled by switch control signals Kp1-Kpn.

FIG. 11 is a circuit diagram of an embodiment of the N-terminal output adjustable buffer driving circuit 42 of the present invention. The N-terminal output adjustable buffer drive circuit 42 includes: an inverter chain, n N-terminal output inverter control switches Sn1-Snn, n N-terminal output inverters Invnk_1-Invnk_n and n N-terminal output inverters NMOS transistors Mn1-Mnn. Its circuit structure is similar to that of the P-end output adjustable buffer drive circuit 41, and will not be described in detail here. The input terminal of the inverter chain is also connected to the output control pulse Din, the source terminals of n N-terminal output NMOS transistors Mn1~Mnn are connected to the ground voltage GND at the same time, and the n N-terminal output inverter control switches Sn1~Snn are respectively Controlled by switch control signals Kn1~Knn.

In FIG. 10 and FIG. 11 , the drains of n P-terminal output PMOS transistors Mp1 ˜ Mpn and n N-terminal output NMOS transistors Mn1 ˜ Mnn are connected together to generate an output drive signal VO.

FIG. 12 is a structural block diagram of the working sequence generating circuit 43 in FIG. 8 of the present invention. The working sequence generation circuit 43 includes: an oscillator 121 , a pulse width counter 122 , a counting cycle selection circuit 123 , a comprehensive counter 124 , a first clock waveform generation circuit 125 and a second clock waveform generation circuit 126 .

The oscillator 121 generates an OSC signal and is connected to the pulse width counter 122 and the synthesis counter 124 , and the output control pulse Din is connected to the pulse width counter 122 and the synthesis counter 124 at the same time. The pulse width counter 122 counts the pulse time width of the output control pulse Din according to the OSC signal, tracks and judges the pulse time width obtained by counting, and compares and quantifies to obtain the frequency discrimination code Dfin; the frequency discrimination code Dfin then enters the counting period selection Circuit 123 generates integrated counter mode selection signal sel0. The integrated counter 124 generates a clock control signal ct1 and a clock control signal ct2 respectively according to the integrated counter mode selection signal sel0 , the OSC signal and the output control pulse Din. The clock control signal ct1 enters the first clock waveform generating circuit 125, and outputs the control clock Ck1. The clock control signal ct2 enters the second clock waveform generating circuit 126, and outputs the control clock Ck2.

The above-mentioned working sequence generating circuit 43 can generate different Dfin codes according to the pulse width of the output control pulse Din to adjust the output clock frequency of the control clock Ck1 and the control clock Ck2, thereby adjusting the load detection time during the effective period of the control clock Ck1 and improving the detection efficiency. precision. For example, for a 2-bit Dfin code, when Dfin code="11", it means that the input pulse width is very wide, the switching frequency of the output control pulse Din is very low, and the output clocks of the control clock Ck1 and the control clock Ck2 can be clocked with a long clock period. output control timing. When Dfin code = "00", it means that the input pulse width is very narrow, the switching frequency of the output control pulse Din is high, and the output clocks of the control clock Ck1 and the control clock Ck2 need to output control timing with the shortest clock period.

Fig. 13 is a structural block diagram of the load comparison and quantization circuit 44 in Fig. 8, which circuit includes: a quantization voltage generation circuit 131, a high and low speed mode selection circuit 132, N comparators, an error filtering circuit 133, a path selection circuit 134, a serial shifter bit register 135 , serial/parallel conversion circuit 136 and M-bit buffer output circuit 137 . The quantization voltage generating circuit 131 converts the reference voltage Vr into N quantization reference voltages Vr1-VrN under the control of the control clock Ck1, and the N quantization reference voltages Vr1-VrN are respectively connected to the reference voltage input terminals of the N comparators; The detection voltage input terminals of the N comparators are all connected to the output drive signal VO, and the N comparators compare the output drive signal VO with the N quantization reference voltages Vr1~VrN respectively to obtain N-bit quantized values D1~DN; N-bit quantized values The incoming error filter circuit 133 outputs an N-bit quantized code Dlo to the path selection circuit 134 . The high and low speed mode selection circuit 132 changes the mode control signal mod according to the magnitude of the frequency discrimination code Dfin. The mode control signal mod is respectively connected to the quantization voltage generation circuit 131 , N comparators, the error filter circuit 133 and the path selection circuit 134 . The mode control signal mod can change the mode of the load comparison and quantization circuit 44 , and ultimately change the speed and power consumption of the load comparison and quantization circuit 44 .

The path selection circuit 134 selects the signal path of the N-bit quantization code Dlo under the control of the mode control signal mod. The high-speed path output port of the path selection circuit 134 is N-bit parallel data, which is directly output to the first data input port of the M-bit buffer output circuit 137 . The low-speed path output port of the path selection circuit 134 is 1-bit serial data, which first enters the serial shift register 135, and then passes through the serial/parallel conversion circuit 136 to output the M-bit parallel quantization code Dlp, which is connected to the M-bit buffer The second data input port of the output circuit 137 .

The working modes of the load comparison and quantization circuit 44 include high-speed mode and low-speed mode. When in the high-speed mode, the quantization voltage generation circuit 131 outputs N quantization reference voltages Vr1-VrN simultaneously under the control of the control clock Ck1, and the N comparators output the driving signal VO and the N quantization reference voltages Vr1-VrN simultaneously Compare and obtain the quantized values D1～DN of the N-bit parallel output, and then obtain the N-bit quantization code Dlo through the error filter circuit 133; at this time, the N-bit quantization code Dlo is N-bit parallel data, which is output from the high-speed path output port of the path selection circuit 134 Afterwards, it is directly output to the first data input port of the M-bit buffer output circuit 137, and the M-bit buffer output circuit 137 outputs the final M-bit load quantization code Dlot under the control of the control clock Ck1. When in the low-speed mode, only the first comparator among the N comparators works, and the remaining N-1 comparators sleep. Under the control of the control clock Ck1, the quantization voltage generation circuit 131 outputs N quantization reference voltages Vr1-VrN sequentially from the output port of Vr1 in chronological order, and the first comparator outputs the drive signal VO in chronological order with Vr1 output Compared with the N quantized reference voltages Vr1-VrN, N-bit serially output quantized values D1-DN are sequentially output at the output port in chronological order, and then the N-bit quantized code Dlo is obtained through the error filter circuit 133. At this time, the N-bit quantization code Dlo is 1-bit serial data. After being output from the low-speed channel output port of the channel selection circuit 134, it first enters the serial shift register 135, and then passes through the serial/parallel conversion circuit 136 to obtain M-bit parallel data. The quantization code Dlp is output to the second data input port of the M-bit buffer output circuit 137, and the M-bit buffer output circuit 137 obtains the final M-bit load quantization code Dlot under the control of the control clock Ck1.

The load comparison and quantization circuit 44 adopts two modes of high speed and low speed to save power consumption of the circuit. The above-mentioned N reference voltages Vr1-VrN can be set at even intervals by thermometer codes, or can be set with different binary weights. Therefore, in actual implementation, an appropriate comparator type and combination strategy can be selected according to the application system requirements of the driver chip. Since the comparator has a certain offset, and the higher the operating speed of the comparator, the more serious the offset is. Therefore, it is necessary to perform error filtering on the N-bit quantization values D1˜DN, and the implementation strategies of the error filtering circuit 133 are very different. If N comparators work in parallel, the digital algorithm for offset calibration of the Flash ADC comparator needs to be used for error filtering; if one comparator is used for multiplexing, the digital algorithm for SARADC offset calibration needs to be used for error filtering.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (7)

1. A high efficiency gate drive circuit, comprising: the high-voltage band-gap voltage protection circuit comprises an input receiving circuit (1), a high-voltage band-gap reference (2), an internal power supply generating circuit (3), a high-efficiency output driving circuit (4), an overcurrent protection circuit (5), an overtemperature protection circuit (6), an undervoltage protection circuit (7), an oscillator (8), a waveform modulation circuit (9), control logic (10) and an error amplifier (11); still include 5 external pins, respectively: a chip power supply pin VDD, an external input pulse pin INX, a current detection pin CS, an output drive switch pin VO and a ground pin GND;

The input end of the input receiving circuit (1) is connected with an external input pulse pin INX, the output end of the input receiving circuit (1) is connected with the input end of the waveform modulating circuit (9), the input end of the waveform modulating circuit (9) is also connected with an oscillator (8), and the output end of the waveform modulating circuit (9) outputs a modulating pulse signal DX; the input end of the error amplifier (11) is connected with a current detection pin CS, the error amplifier (11) amplifies the external sampling current to obtain a current input signal CSIN, and the current input signal CSIN is connected to the overcurrent protection circuit (5); the high-voltage band gap reference (2) is used for providing a reference voltage Vref; the internal power supply generating circuit (3) is used for generating an internal power supply voltage VCC and various bias signals according to the reference voltage Vref for other circuits in the chip; the over-current protection circuit (5), the over-temperature protection circuit (6) and the under-voltage protection circuit (7) respectively generate an over-current protection signal OCP, an over-temperature protection signal OTP and an under-voltage protection signal UVLO according to the reference voltage Vref; the over-current protection signal OCP, the over-temperature protection signal OTP, the under-voltage protection signal UVLO and the modulation pulse signal DX are all connected to the control logic (10) and are processed to obtain an output control pulse Din; the output control pulse Din is connected to the high-efficiency output driving circuit (4), and an output driving signal obtained through buffer driving of the high-efficiency output driving circuit (4) is connected with the output driving switch Guan Yinjiao VO;

After a chip power supply pin VDD meets the power-on requirement, the high-voltage band gap reference (2) works normally first and provides a reference voltage Vref of 1.2V; an input receiving circuit (1) receives an external input pulse and converts the external input pulse into a logic level VIN with a high level of VCC, and then the logic level VIN and an oscillation clock generated by an oscillator (8) are modulated to obtain a modulation pulse signal DX; the error amplifier (11) amplifies the external sampling current to obtain a current input signal CSIN, and the current input signal CSIN enters the overcurrent protection circuit (5) to obtain an overcurrent protection signal OCP through comparison; the control logic (10) carries out logic processing on the over-current protection signal OCP, the over-temperature protection signal OTP, the under-voltage protection signal UVLO and the modulation pulse signal DX, and outputs an output control pulse Din for output driving; the output control pulse Din is buffered and driven by a high-efficiency output driving circuit (4) to obtain an output driving signal, and the output driving signal is output through an output driving switch pin VO.

2. A high efficiency gate drive circuit according to claim 1, wherein the over-temperature protection circuit (6) comprises: NPN triode Q61, NPN triode Q60, resistor R61, resistor R62, PMOS tube P60, inverter Inv60, capacitor C60 and Schmitt trigger Schmitt; the collector of the NPN triode Q61 is connected to an internal power supply voltage VCC, the emitter of the NPN triode Q61 is connected with the upper end of a resistor R61, and the base of the NPN triode Q61 is connected with a reference voltage Vref; the lower end of the resistor R61 is connected with the upper end of the resistor R61 and the base electrode of the NPN triode Q60, and the collector electrode of the NPN triode Q60 is connected with the upper end of the capacitor C60, the output end of the inverter Inv60, the drain electrode of the PMOS tube P60 and the input end of the Schmitt trigger Schmitt; the source electrode of the PMOS tube P60 is connected to the internal power supply voltage VCC, and the grid electrode of the PMOS tube P60 is connected to the bias voltage Vb6; the signal Ctrl connected to the input of the inverter Inv60 is a chip global control signal; the output end of the Schmitt trigger Schmitt outputs an over-temperature protection signal OTP; the lower end of the resistor R62, the lower end of the capacitor C60 and the emitter of the NPN triode Q60 are all connected to the ground voltage GND.

3. A high efficiency gate drive circuit according to claim 1, wherein the high efficiency output drive circuit (4) comprises: the P end output adjustable buffer driving circuit (41), the N end output adjustable buffer driving circuit (42), the sampling switch SW, the working time sequence generating circuit (43), the load comparison and quantization circuit (44) and the driving current selecting circuit (45);

the output control pulse Din is simultaneously connected to the data input ends of the P-end output adjustable buffer driving circuit (41), the N-end output adjustable buffer driving circuit (42) and the working time sequence generating circuit (43); the P end output adjustable buffer driving circuit (41) is connected with the driving signal output end of the N end output adjustable buffer driving circuit (42), is used as an output end for outputting driving signals, and is connected to the input end of the load comparison quantization circuit (44) through the sampling switch SW; the working time sequence generating circuit (43) carries out tracking judgment on the frequency of the output control pulse Din to obtain a frequency judgment code Dfin and generates a control clock Ck1 and a control clock Ck2 which are not overlapped with high level; wherein the frequency discrimination code Dfin is connected to the load comparison quantization circuit (44), the control clock Ck1 is connected to the load comparison quantization circuit (44) and the drive current selection circuit (45), and the control clock Ck2 is connected to the drive current selection circuit (45); the output driving signal enters a load comparison quantization circuit (44) after being sampled by a sampling switch SW, and a load quantization code Dlot is obtained under the control of a reference voltage Vr, a control clock Ck1 and a frequency discrimination code Dfin and is connected to a driving current selection circuit (45); the load quantization code Dlot, the control clock Ck1 and the control clock Ck2 enter a driving current selection circuit (45) at the same time to obtain n switch control signals Kp 1-Kpn and n switch control signals Kn 1-Knn; wherein, the switch control signals Kp 1-Kpn are respectively connected to n switch signal input ends of the P end output adjustable buffer driving circuit (41), and the switch control signals Kn 1-Knn are respectively connected to n switch signal input ends of the P end output adjustable buffer driving circuit (41); n is any positive integer;

After the power supply voltage is electrified, the working time sequence generating circuit (43) tracks and judges the frequency of the output control pulse Din to obtain a frequency judging code Dfin and generates a control clock Ck1 and a control clock Ck2; when the Ck1 clock is valid, the load comparison quantization circuit (44) firstly generates a group of default load quantization codes Dlot_pre and enters the driving current selection circuit (45) according to the states of the output driving signals VO, the reference voltage Vr and the frequency discrimination codes Dfin sampled by the sampling switch SW, the driving current selection circuit (45) outputs a group of default switch control signals Kp1_pre-Kpn_pre and switch control signals Kn1_pre-Knn _pre, and the output driving signals drive external loads under the action of default driving currents and enable the voltage of the output driving signals to be gradually increased; when the Ck1 clock is finished, the load quantization code Dlot_pre is adjusted according to the size of the output driving signal at the moment, and the adjusted load quantization code Dlot_lock is obtained and kept unchanged; when the Ck2 clock is valid, the driving current selection circuit (45) outputs a group of new switch control signals Kp1_lock-Kpn_lock and switch control signals Kn1_lock-Knn _lock according to the load quantization code Dlot_lock, and the output driving signals drive an external load under the action of the new driving current and enable the voltage of the output driving signals to rise rapidly to the voltage VCC; when the Ck2 clock is finished, the load quantization code Dlot is cleared, the switch control signals Kp 1-Kpn output by the driving current selection circuit (45) are cleared synchronously, N P-end output inverter control switches in the P-end output adjustable buffer driving circuit (41) are turned off, meanwhile, the switch control signals Kn 1-Knn output by the driving current selection circuit (45) are valid, N N-end output inverter control switches in the N-end output adjustable buffer driving circuit (42) are turned on, and the output driving signals are pulled to the ground voltage GND from the voltage VCC rapidly, so that an external load power device is turned off.

4. A high efficiency gate driving circuit according to claim 3, wherein said P-terminal output adjustable buffer driving circuit (41) comprises: the input end of the inverter chain is connected with the output control pulse Din, the output end of the inverter chain is respectively connected with the input ends of n P-end output inverters through n P-end output inverter control switches, the output ends of the n P-end output inverters are respectively connected with the gate ends of n P-end output PMOS tubes, and the source ends of the n P-end output PMOS tubes are simultaneously connected to the internal power supply voltage VCC; the n P-end output inverter control switches are controlled by switch control signals Kp 1-Kpn respectively;

the N-terminal output adjustable buffer driving circuit (42) comprises: the input end of the inverter chain is connected with the output control pulse Din, the output end of the inverter chain is respectively connected with the input ends of N N-end output inverters through N N-end output inverter control switches, the output ends of the N N-end output inverters are respectively connected with the gate ends of N N-end output NMOS tubes, and the source ends of the N N-end output NMOS tubes are simultaneously connected to the ground voltage GND; the N N-terminal output inverter control switches are controlled by switch control signals Kn 1-Knn respectively;

the drain ends of the N P-end output PMOS tubes are connected with the drain ends of the N N-end output NMOS tubes, and are connected to the input end of the load comparison quantization circuit (44) through the sampling switch SW while also connected to the output drive switch pin VO.

5. A high-efficiency gate driving circuit according to claim 3, wherein the operation timing generation circuit (43) includes: an oscillator (121), a pulse width counter (122), a count period selection circuit (123), a comprehensive counter (124), a first clock waveform generation circuit (125), and a second clock waveform generation circuit (126); OSC signals generated by the oscillator (121) are connected to a pulse width counter (122) and a comprehensive counter (124), and output control pulses Din are simultaneously connected to the pulse width counter (122) and the comprehensive counter (124); the pulse width counter (122) counts the pulse time width of the output control pulse Din according to the OSC signal, and performs tracking judgment and comparison quantization output frequency judgment code Dfin on the pulse time width obtained by counting; the frequency discrimination code Dfin is connected to a count period selection circuit (123) to generate an integrated counter mode selection signal sel0; the integrated counter (124) generates a clock control signal ct1 and a clock control signal ct2 according to the mode selection signal sel0, the OSC signal and the output control pulse Din; finally, the clock control signal ct1 and the clock control signal ct2 are respectively connected to the first clock waveform generation circuit (125) and the second clock waveform generation circuit (126), and the first clock waveform generation circuit (125) and the second clock waveform generation circuit (126) respectively output the final control clock Ck1 and the control clock Ck2.

6. A high efficiency gate drive circuit according to claim 3, wherein the load comparison quantization circuit (44) comprises: a quantization voltage generation circuit (131), a high-low speed mode selection circuit (132), N comparators, an error filter circuit (133), a path selection circuit (134), a serial shift register (135), a serial-parallel conversion circuit (136) and an M-bit buffer output circuit (137); the input end of the quantized voltage generating circuit (131) is connected with the reference voltage Vr, the control clock Ck1 and a mode control signal mod output by the high-low speed mode selecting circuit (132), and the quantized voltage generating circuit (131) converts the reference voltage Vr into N quantized reference voltages Vr 1-VrN under the control of the control clock Ck1 and is respectively connected to the reference voltage input ends of N comparators; the detection voltage input ends of the N comparators are all connected with the output driving switch pin VO, and the N comparators respectively compare the output driving signals with N quantized reference voltages Vr 1-VrN and output N quantized values D1-DN; then the N-bit quantized values D1-DN enter an error filter circuit (133) to output N-bit quantized codes Dlo; the high-low speed mode selection circuit (132) outputs a mode control signal mod according to the magnitude of the frequency discrimination code Dfin so as to change the mode of the load comparison quantization circuit (44) to change the speed and the power consumption of the load comparison quantization circuit (44), and the mode control signal mod is respectively connected to the quantization voltage generation circuit (131), N comparators, the error filtering circuit (133) and the path selection circuit (134); the path selection circuit (134) selects a signal path of the N-bit quantized code Dlo under the control of a mode control signal mod; the high-speed path output port of the path selection circuit (134) is N-bit parallel data, the N-bit parallel data is directly output to the first data input port of the M-bit buffer output circuit (137), the low-speed path output port of the path selection circuit (134) is 1-bit serial data, the 1-bit serial data is firstly connected to the serial shift register (135), the serial shift register (135) outputs and then enters the serial-parallel conversion circuit (136) to obtain M-bit parallel quantized codes Dlp, and the M-bit parallel quantized codes are connected to the second data input port of the M-bit buffer output circuit (137); the M-bit buffer output circuit (137) outputs a final M-bit load quantization code Dlot under the control of the control clock Ck 1; wherein M and N are integers greater than 1.

7. The high efficiency gate drive circuit of claim 6, wherein the load comparison quantization circuit (44) comprises a high speed mode and a low speed mode;

the working mode of the high-speed mode is as follows: the quantization voltage generation circuit (131) outputs N quantization reference voltages under the control of the control clock Ck1, N comparators respectively compare the output driving signals with the N quantization reference voltages at the same time, output N quantization values D1-DN which are output in parallel, and then an N-bit quantization code Dlo is obtained through the error filtering circuit (133); at this time, the N-bit quantized code Dlo is N-bit parallel data, and the N-bit parallel data is directly output to the first data input port of the M-bit buffer output circuit (137) through the high-speed path output port of the path selection circuit (134), and the M-bit buffer output circuit (137) outputs the final M-bit load quantized code Dlot under the control of the control clock Ck 1;

the working mode of the low-speed mode is as follows: only a first comparator of the N comparators works, the rest N-1 comparators are dormant, the quantized voltage generating circuit (131) sequentially outputs N quantized reference voltages through an output port according to time sequence under the control of the control clock Ck1, the first comparator sequentially compares an output driving signal with the N quantized reference voltages according to time sequence, the output port of the first comparator sequentially outputs quantized values D1-DN of N bits of serial output according to time sequence, and then the N bits of quantized codes Dlo are obtained through the error filtering circuit (133); at this time, the N-bit quantized code Dlo is 1-bit serial data, the low-speed path output port passing through the path selection circuit (134) sequentially enters the serial shift register (135), the output of the serial shift register (135) enters the serial-parallel conversion circuit (136) again, the M-bit parallel quantized code Dlp is obtained and output to the second data input port of the M-bit buffer output circuit (137), and the M-bit buffer output circuit (137) obtains the final M-bit load quantized code Dlot under the control of the control clock Ck 1.

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