CN106816388B

CN106816388B - Semiconductor packaging structure and manufacturing method thereof

Info

Publication number: CN106816388B
Application number: CN201610104782.2A
Authority: CN
Inventors: 陈宪章
Original assignee: Chipmos Technologies Inc
Current assignee: Chipmos Technologies Inc
Priority date: 2015-12-02
Filing date: 2016-02-25
Publication date: 2019-04-30
Anticipated expiration: 2036-02-25
Also published as: TW201721815A; CN106816388A; TWI582921B

Abstract

The invention provides a semiconductor packaging structure and a manufacturing method thereof. The manufacturing method comprises the following steps. A package substrate is provided. The package substrate includes a dielectric layer, a first metal layer and a second metal layer. And patterning the second metal layer to form a circuit layer. And forming a solder mask layer on the circuit layer and partially covering the circuit layer. And configuring a carrier plate on the circuit layer and the solder mask layer. The dielectric layer and the first metal layer are removed to expose the circuit layer. And removing part of the circuit layer between the first contact and the second contact to expose the trench on the solder mask layer. The chip is electrically connected to the circuit layer. And forming a packaging colloid on the circuit layer and the solder mask layer and coating the chip. And removing the carrier plate. The semiconductor packaging structure manufactured by the manufacturing method of the semiconductor packaging structure does not have a core layer, so that the whole thickness of the semiconductor packaging structure is reduced, and the development requirement of miniaturization is met.

Description

Semiconductor package and preparation method thereof

Technical field

The present invention relates to a kind of encapsulating structure and preparation method thereof more particularly to a kind of semiconductor package and its production Method.

Background technique

In semiconductor industry, the production of integrated circuit (IC) can be divided mainly into three phases: the design of integrated circuit, collection At the production of circuit and the encapsulation of integrated circuit.After the production of integrated circuits of wafer is completed, the active surface of wafer is configured There is multiple chip connecting pads (die pad).It is held finally, cutting resulting bare chip by wafer and can be electrically connected at by chip connecting pad It carries device (carrier).Typically, carrier can be lead frame (lead frame) or package substrate (package Substrate), and chip can engage (wire bonding) or chip bonding (flip chip bonding) etc. by routing Mode is connected on carrier, so that the contact of the chip connecting pad of chip and carrier is electrically connected, and then constitutes chip package Body.

The integral thickness of chip packing-body is, for example, the height of the thickness of packing colloid, the thickness of carrier and external terminal The summation of degree.To meet the growth requirement that (miniaturization) is miniaturized in chip packing-body, the common practice is to reduce to hold Carry the thickness of device.However, the reduction of the thickness of carrier is limited, and its structural strength can be impacted.Therefore, it develops then The carrier (such as substrate) of seedless central layer (coreless).

Summary of the invention

The present invention provides a kind of semiconductor package, and carrier does not have core layer, therefore integral thickness can be thinned.

The present invention provides a kind of production method of semiconductor package, and making resulting semiconductor package can have There is relatively thin thickness.

A kind of production method that the present invention proposes semiconductor package comprising following steps.Package substrate is provided.Envelope Dress substrate includes dielectric layer, connects the first metal layer of dielectric layer and connect the second metal layer of the first metal layer, wherein the One metal layer is between dielectric layer and second metal layer.Second metal layer is patterned, to form line layer, wherein line layer has There are the first contact and the second contact.Solder mask is formed on line layer, and makes solder mask partial mulching line layer.Configure support plate in On line layer and solder mask.Dielectric layer and the first metal layer are removed, to expose line layer.It removes and is located at the first contact and second Part line layer between contact, to expose the irrigation canals and ditches on solder mask.Keep chip electrical by the first contact and the second contact It is connected to line layer.Packing colloid is formed on line layer and solder mask, and makes packing colloid coating chip.Remove support plate.

The present invention proposes a kind of semiconductor package comprising line layer, solder mask, chip, packing colloid and more A external terminal.Line layer has the first contact and the second contact.Solder mask partial mulching line layer, wherein solder mask exposes First contact and the second contact, and there are the irrigation canals and ditches between the first contact and the second contact.Chip be configured at line layer with On solder mask, and line layer is electrically connected at by the first contact and the second contact.Chip crosses over the top of irrigation canals and ditches.Packing colloid It is configured on line layer and solder mask, and coating chip.These external terminals are respectively arranged at the line exposed by solder mask On the floor of road.

Based on above-mentioned, since the production method of semiconductor package through the invention makes resulting semiconductor packages Structure does not have core layer, therefore the integral thickness of semiconductor package is reduced, and then the development for meeting micromation needs It asks.

To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make Carefully it is described as follows.

Detailed description of the invention

Figure 1A to Fig. 1 L is the diagrammatic cross-section of the production process of the semiconductor package of one embodiment of the invention；

Fig. 1 M is to form external terminal in the diagrammatic cross-section of the semiconductor package of Fig. 1 L；

Fig. 2A to Fig. 2 F is the diagrammatic cross-section of the production process of the semiconductor package of another embodiment of the present invention；

Fig. 2 G is to form external terminal in the diagrammatic cross-section of the semiconductor package of Fig. 2 F.

Appended drawing reference:

10: line construction

100,100A: semiconductor package

110: package substrate

111: dielectric layer

112: the first metal layer

113: second metal layer

114: line layer

114a: the first contact

114b: the second contact

120: solder mask

121: surface

122: recess

123: irrigation canals and ditches

130,131: protecting layer

140: support plate

150: chip

151: active surface

152: soldered ball

160: packing colloid

170: external terminal

180: conductive column

190: bonding wire

Specific embodiment

Figure 1A to Fig. 1 L is the diagrammatic cross-section of the production process of the semiconductor package of one embodiment of the invention.It is first First, Figure 1A is please referred to, package substrate 110 is provided.Package substrate 110 includes dielectric layer 111, be formed on dielectric layer 111 the One metal layer 112 (or the first metal layer 112 of connection dielectric layer 111) and the second gold medal for being formed in the first metal layer 112 Belong to layer 113 (or second metal layer 113 of connection the first metal layer 112), wherein the first metal layer 112 is located at dielectric layer 111 Between second metal layer 113.In the present embodiment, the quantity of the first metal layer 112 and second metal layer 113 is two respectively It is a.Both of the aforesaid the first metal layer 112 is located at the opposite sides of dielectric layer 111, and the corresponding shape of each second metal layer 113 At on the first metal layer 112.The material of dielectric layer 111 can be with silica, silicon nitride, silicon carbide, silicon oxynitride, fire sand Or siloxicon or FR-4 (epoxy resin fiberglass) substrate, PI (polyimide resin) substrate or other similar material The substrate that matter is constituted.The material of the first metal layer 112 and second metal layer 113 can be copper, aluminium, gold, silver, nickel or aforementioned gold The alloy of category.As shown in Figure 1A, the thickness of the first metal layer 112 is, for example, the thickness for being less than second metal layer 113.

Then, Figure 1B is please referred to, such as patterns second metal layer 113 in a manner of exposure development to form line layer 114.In the present embodiment, line layer 114 still covers the first metal layer 112, and has the first contact 114a and the second contact 114b.In other embodiments, line layer can expose part the first metal layer, and the present invention is without restriction to this.Then, it asks Solder resist material is formed on line layer 114 with reference to Fig. 1 C, such as in a manner of coating, printing or spray printing etc..Then, such as with exposure The mode of development patterns solder resist material, to form solder mask 120, so that 120 partial mulching line layer 114 of solder mask, and it is sudden and violent Expose the first contact 114a and the second contact 114b.

It is existing to prevent the first contact 114a for being exposed to solder mask 120 and the second contact 114b from generating oxidation or vulcanization etc. As being further formed and protecting layer 130 on the first contact 114a and the second contact 114b, as shown in figure iD.In general, weldering is protected Layer 130 can be organic guarantor and weld film (OSP), or is made of not oxidizable metal material, such as the side for passing through plating Formula forms ni/au layers on the first contact 114a and the second contact 114b.On the other hand, line layer 114, solder mask 120 and guarantor Layer 130 may make up line construction 10, wherein each line construction 10 can be connected with corresponding the first metal layer 112.Then, Fig. 1 E is please referred to, respectively at configuration support plate 140 on each line construction 10.Specifically, each support plate 140 is configured at corresponding On line layer 114 and solder mask 120, and mutually support patch with corresponding solder mask 120, and not with corresponding line layer 114 Contact.Support plate 140 is, for example, hard substrate or flexible substrate, and can fit in welding resistance by release film (release film) Layer 120.When carrying out subsequent encapsulation step, support plate 140 can be used as temporary auxiliary support structure, corresponding to support Line construction 10.

Please continue to refer to Fig. 1 D and Fig. 1 E, the quantity of line construction 10 is, for example, two, wherein the two line constructions 10 It is located at the opposite sides of dielectric layer 111, and each line construction 10 can be matched with corresponding support plate 140.Then, please join Examine Fig. 1 F, removing dielectric layer 111 and the first metal layer 112 (or makes each line construction 10 and corresponding the first metal layer 112 Separation).At this point, the part being originally connected with the first metal layer 112 in line layer 114 can be exposed to outside.It is subsequent with wherein one The encapsulation procedure of a line construction 10 explains.Then, Fig. 1 G is please referred to, such as is removed in a manner of exposure development and is covered in resistance Part line layer 114 on layer 120, and line layer 114 is made to be slightly below the table not covered by support plate 140 in solder mask 120 Face 121, to define multiple recess 122.

Fig. 1 H is please referred to, such as is removed between the first contact 114a and the second contact 114b in a manner of exposure development Recess 122 in line layer 114, to expose the irrigation canals and ditches 123 of solder mask 120.Later, Fig. 1 I is please referred to, is formed and protects layer 131 in each recess 122, and to cover the line layer 114 for being exposed to solder mask 120, using prevents line layer 114 from generating oxidation Or phenomena such as vulcanization.Then, Fig. 1 J is please referred to, is electrically connected chip 150 by the first contact 114a and the second contact 114b In line layer 114.In the present embodiment, the active surface 151 of chip 150 and the surface 121 of solder mask 120 are facing with each other, with Make 150 chip bonding of chip in the first contact 114a and the second contact 114b, and chip 150 crosses over the top of irrigation canals and ditches 123.Generally For, make 150 chip bonding of chip can first convex on chip 150 before the first contact 114a and the second contact 114b Block attaches scaling powder.Then, the convex block for attaching fluxing agent is abutted into the first contact 114a and the second contact 114b.Later, it returns (reflow) convex block is welded, and is removed by scaling powder and protects layer 131, so that reflow convex block is formed by soldered ball 152 and connects securely Together in the first contact 114a and the second contact 114b.Since the first contact 114a and the second contact 114b is separated by irrigation canals and ditches 123 Come, therefore in reflow convex block, irrigation canals and ditches 123 can collect the solder of extra spilling, to prevent the solder overflow of melting and overlap Cheng Xiqiao (solder bridge), to avoid the phenomenon for generating short circuit.

Then, it please refers to Fig. 1 K, forms packing colloid 160 on the surface of solder mask 120 121, and make packing colloid 160 Coating chip 150 and soldered ball 152.On the other hand, packing colloid 160 can cover the first contact 114a of line layer 114, second connect Point 114b and guarantor's layer 131, and insert irrigation canals and ditches 123.Later, Fig. 1 L is please referred to, support plate 140 is removed, to expose guarantor's layer 130, wherein chip 150 and guarantor's layer 130 are located at the opposite sides of line layer 114.So far, semiconductor package 100 Production be substantially completed.Due to semiconductor package 100 do not have core layer, semiconductor package 100 it is whole Body thickness is reduced, and then meets the growth requirement of micromation.

Fig. 1 M is to form external terminal in the diagrammatic cross-section of the semiconductor package of Fig. 1 L.Fig. 1 M is please referred to, is being made After obtaining semiconductor package 100 as can be seen in 1L, can further progress plant ball step, to form multiple external terminals 170 in the line layer 114 (i.e. the first contact 114a and the second non-encapsulated colloid of contact 114b that are exposed by solder mask 120 160 sides covered) on.In general, before carrying out planting ball step, scaling powder can be first coated on guarantor's layer 130.It connects , tin ball is implanted on scaling powder.Later, solder ball is returned, and is removed by scaling powder and protects layer 130, so that by reflow tin Ball, which is formed by external terminal 170, can be firmly engaged at (i.e. the first contact of line layer 114 exposed by solder mask 120 The side that 114a and the non-encapsulated colloid 160 of the second contact 114b are covered) on.In the present embodiment, external terminal 170 is to adopt With the form of Ball Grid array (BGA), the invention is not limited thereto.In other embodiments, planar gate can be used in external terminal The forms such as lattice array (LGA) or needle-shaped grid array (PGA).

It is noted that the present embodiment is to weld film as layer 130 is protected using organic guarantor to explain, the present invention is not limited to This.In other embodiments, protect layer can be ni/au layers, in return solder ball when, scaling powder can be used to remove be built-up in nickel/ Impurity in layer gold.

Other embodiments will be enumerated below using as explanation.It should be noted that, following embodiments continue to use aforementioned reality herein The reference numerals and partial content of example are applied, wherein adopting the identical or approximate component that is denoted by the same reference numerals, and are omitted The explanation of same technique content.Explanation about clipped can refer to previous embodiment, and following embodiment will not be repeated herein.

Fig. 2A to Fig. 2 F is the diagrammatic cross-section of the production process of the semiconductor package of another embodiment of the present invention.It needs Illustrate, the part making step of the semiconductor package 100A (being shown in Fig. 2 F) of the present embodiment is substantially extremely schemed with Figure 1A Making step shown in 1F is same or similar, and in this, it is no longer repeated.Firstly, please referring to Fig. 2A, complete to make each route After structure 10 separates (as shown in fig. 1F) with corresponding the first metal layer 112, such as at least one is formed by way of plating Conductive column 180 (schematically showing two) is on line layer 114.These conductive columns 180 are located at the first contact 114a or second The side of contact 114b.In the present embodiment, the first contact 114a and the second contact 114b is, for example, to be located at these conductive columns 180 Between.In other embodiments, the quantity of conductive column may be greater than two, and surround the first contact and the second contact.

Then, Fig. 2 B is please referred to, such as removes the part line layer being covered on solder mask 120 in a manner of exposure development 114, and line layer 114 is made to be slightly below the surface 121 not covered by support plate 140 in solder mask 120, to define multiple recess 122.Then, Fig. 2 C is please referred to, is formed and protects layer 131 in each recess 122, the route of solder mask 120 is exposed to covering Layer 114 uses phenomena such as preventing line layer 114 from generating oxidation or vulcanization.Meanwhile it protecting layer 131 and also will form in conductive column 180 On, use phenomena such as preventing conductive column 180 from generating oxidation or vulcanization.In the present embodiment, it is located at the first contact 114a and second The line layer 114 in irrigation canals and ditches 123 between contact 114b is not removed.In other words, it will the line layer 114 of some is located at In irrigation canals and ditches 123.

Then, Fig. 2 D is please referred to, chip 150 is made to be electrically connected at route by the first contact 114a and the second contact 114b Layer 114.In the present embodiment, the active surface 151 of chip 150 is back on the surface of solder mask 120 121.In other words, chip 150 are configured on solder mask 120, and across the top of irrigation canals and ditches 123, with for example logical with the first contact 114a and the second contact 114b It crosses the mode of routing engagement and is electrically connected.Specifically, bonding wire 190 can be engaged in the active surface 151 and first of chip 150 Contact 114a, and be engaged in the active surface 151 of chip 150 with and the second contact 114b, to enable chip 150 and line layer 114 It is electrically connected.It in general, can be first using dilute before making bonding wire 190 be engaged in the first contact 114a and the second contact 114b Sour or plasma-based protects layer 131 to remove part, to expose the first contact 114a and the second contact 114b.

It is noted that the present embodiment is to weld film as layer 131 is protected using organic guarantor to explain, the present invention is not limited to This.In other embodiments, protecting layer can be ni/au layers, and diluted acid or plasma-based can be used to remove and be built-up in ni/au layers Impurity.In other words, the aforementioned removing step carried out using diluted acid or plasma-based need to be depending on protecting the type of layer, with selectively Remove the impurity that organic guarantor welds film or is built-up in ni/au layers.

It please refers to Fig. 2 E, forms packing colloid 160 on the surface of solder mask 120 121, and coat packing colloid 160 Chip 150 and bonding wire 190.On the other hand, packing colloid 160 can cover the first contact 114a and the second contact of line layer 114 114b, and can be exposed to except packing colloid 160 by the conductive column 180 that guarantor's layer 131 is coated.Later, Fig. 2 F is please referred to, is moved Except support plate 140, layer 130 is protected to expose, wherein chip 150 and guarantor's layer 130 are located at opposite the two of line layer 114 Side.So far, the production of semiconductor package 100A has been substantially completed.Since semiconductor package 100A does not have core Layer, therefore the integral thickness of semiconductor package 100A is reduced, and then meets the growth requirement of micromation.Another party Face, being exposed to the conductive column 180 except packing colloid 160 can be used to connect other chips, other semiconductor packages or electricity Sub-component.As shown in Figure 2 E, the height of conductive column 180 is, for example, the thickness for being less than packing colloid 160.In other embodiments, The height of conductive column may be greater than or equal to packing colloid thickness.

For example, semiconductor package 100A can carry out storehouse with another semiconductor package, wherein aforementioned another Semiconductor encapsulating structure is similar to semiconductor package 100A, and leading by conductive column and semiconductor package 100A Electric column 180 is electrically connected.At this point, the height of the conductive column of aforementioned another semiconductor packages knot is, for example, to be greater than the thickness of packing colloid Degree, in order to which the conductive column 180 of semiconductor package 100A matches.

Fig. 2 G is to form external terminal in the diagrammatic cross-section of the semiconductor package of Fig. 2 F.Fig. 2 G is please referred to, is being made After obtaining the semiconductor package 100A of Fig. 2 F, can further progress plant ball step, with formed multiple external terminals 170 in Line layer 114 (i.e. the first contact 114a and non-encapsulated 160 institute of colloid of the second contact 114b exposed by solder mask 120 The side of covering) on.In general, before carrying out planting ball step, scaling powder can be first coated on guarantor's layer 130.Then, will Tin ball, which is implanted in, to be protected on layer 130.Later, solder ball is returned, and is removed by scaling powder and protects layer 130, so that by returning solder ball (i.e. the first contact of line layer 114 exposed by solder mask 120 can be firmly engaged at by being formed by external terminal 170 The side that 114a and the non-encapsulated colloid 160 of the second contact 114b are covered) on.In the present embodiment, external terminal 170 is to adopt With the form of Ball Grid array (BGA), the invention is not limited thereto.In other embodiments, planar gate can be used in external terminal The forms such as lattice array (LGA) or needle-shaped grid array (PGA).

In conclusion the semiconductor packages knot as obtained by the production method of semiconductor package through the invention Structure does not have core layer, therefore the integral thickness of semiconductor package is reduced, and then meets the growth requirement of micromation.? In one embodiment, the part line layer between the first contact and the second contact can be removed, to expose solder mask Irrigation canals and ditches.Accordingly, when can prevent chip bonding, the solder overflow that is melted on the first contact and the second contact and be overlapped to form Xi Qiao, with Avoid generating the phenomenon of short circuit.In another embodiment, it can be formed positioned at the first contact and the line layer around the second contact There is conductive column, and aforesaid conductive column can be used to connect other chips, other semiconductor packages or electronic building brick.Another party Face, the semiconductor package for being again provided with conductive column can carry out opposite storehouse, and be electrically connected to each other by conductive column.

Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field Middle those of ordinary skill, it is without departing from the spirit and scope of the present invention, therefore of the invention when can make a little change and retouching Protection scope is subject to view appended claims confining spectrum.

Claims

1. a manufacturing method of a semiconductor packaging structure, is characterized in that, comprises:

A package substrate is provided, the package substrate includes a dielectric layer, a first metal layer connected to the dielectric layer, and a second metal layer connected to the first metal layer, wherein the first metal layer is located on the dielectric layer between the layer and the second metal layer;

patterning the second metal layer to form a circuit layer, the circuit layer fully covers the surface of the first metal layer relatively far from the dielectric layer, wherein the circuit layer has a first contact and a second contact;

forming a solder resist layer on the circuit layer, and making the solder resist layer partially cover the circuit layer;

disposing a carrier on the circuit layer and the solder resist layer;

removing the dielectric layer and the first metal layer to expose the circuit layer;

removing part of the circuit layer between the first contact and the second contact to expose the trench on the solder resist layer;

the chip is electrically connected to the circuit layer through the first contact and the second contact;

forming an encapsulant on the circuit layer and the solder resist layer, and making the encapsulant cover the chip; and

Remove the carrier plate.

2 . The method for fabricating a semiconductor package structure according to claim 1 , wherein the flip chip is bonded to the first contact and the second contact so as to be electrically connected to the circuit layer. 3 .

3. The method for manufacturing a semiconductor package structure according to claim 1, further comprising:

Before electrically connecting the chip and the circuit layer, at least one conductive column is formed on the circuit layer, wherein the conductive column is located on one side of the first contact or the second contact and is exposed to the outside the encapsulating colloid.

4. The method for fabricating a semiconductor package structure according to claim 3, further comprising:

Part of the circuit layer is removed, and a solder protection layer is formed on the circuit layer and the conductive post.

5 . The method for fabricating a semiconductor package structure according to claim 1 , wherein the chip is wire-bonded to the first contact and the second contact so as to be electrically connected to the circuit layer. 6 .

6. The method for manufacturing a semiconductor package structure according to claim 1, further comprising:

Before disposing the carrier on the circuit layer and the solder resist layer, a solder protection layer is formed on the circuit layer.

7. The method for fabricating a semiconductor package structure according to claim 1, further comprising:

Before electrically connecting the chip and the circuit layer, part of the circuit layer is removed, and a solder protection layer is formed on the circuit layer.

8 . The method for fabricating a semiconductor package structure according to claim 1 , wherein the number of the first metal layer and the number of the second metal layer is two respectively, and the two first metal layers are respectively located in the On opposite sides of the dielectric layer, each of the second metal layers is connected to the corresponding first metal layer.

9. The method for fabricating a semiconductor package structure according to claim 1, further comprising:

After removing the carrier board, a plurality of external terminals are formed on the circuit layer exposed by the solder resist layer.

10. A semiconductor packaging structure, comprising:

The circuit layer has a first contact and a second contact;

a solder resist layer partially covering the circuit layer, wherein the solder resist layer exposes the first contact point and the second contact point, and has a trench between the first contact point and the second contact point;

a chip, disposed on the circuit layer and the solder resist layer, and electrically connected to the circuit layer through the first contact and the second contact, wherein the chip spans over the trench;

an encapsulant, disposed on the circuit layer and the solder resist layer, and wrapping the chip; and

A plurality of external terminals are respectively disposed on the circuit layer exposed by the solder resist layer.

11. The semiconductor package structure of claim 10, further comprising:

At least one conductive column is disposed on the circuit layer, wherein the conductive column is located on one side of the first contact or the second contact, and is exposed to the outside of the encapsulant.