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BE903901A - Circuit de multiplication pour des echantillons pcm codes. - Google Patents

Circuit de multiplication pour des echantillons pcm codes.

Info

Publication number
BE903901A
BE903901A BE2/60885A BE2060885A BE903901A BE 903901 A BE903901 A BE 903901A BE 2/60885 A BE2/60885 A BE 2/60885A BE 2060885 A BE2060885 A BE 2060885A BE 903901 A BE903901 A BE 903901A
Authority
BE
Belgium
Prior art keywords
product
samples
multiplication circuit
circuit
pcm codes
Prior art date
Application number
BE2/60885A
Other languages
English (en)
Inventor
J P Mills
M S Macrander
Original Assignee
Gte Comm Systems Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gte Comm Systems Corp filed Critical Gte Comm Systems Corp
Publication of BE903901A publication Critical patent/BE903901A/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/487—Multiplying; Dividing
    • G06F7/4876—Multiplying
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/556—Logarithmic or exponential functions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49936—Normalisation mentioned as feature only

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Complex Calculations (AREA)
  • Analogue/Digital Conversion (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

Circuit de multiplication destiné à multiplier des échantillons PCM codés en D2, Un circuit d'addition d'exposants fournit la somme des exposants des deux nombres. Un circuit multiplicateur de mantisses détermine le produit des deux mantisses et un générateur de signe fournit une valeur de signe pour le produit des deux nombres. Un circuit de normalisation veille à ce que la mantisse du produit se trouve dans un domaine de valeurs déterminé.
BE2/60885A 1984-12-31 1985-12-20 Circuit de multiplication pour des echantillons pcm codes. BE903901A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/687,875 US4716539A (en) 1984-12-31 1984-12-31 Multiplier circuit for encoder PCM samples

Publications (1)

Publication Number Publication Date
BE903901A true BE903901A (fr) 1986-04-16

Family

ID=24762228

Family Applications (1)

Application Number Title Priority Date Filing Date
BE2/60885A BE903901A (fr) 1984-12-31 1985-12-20 Circuit de multiplication pour des echantillons pcm codes.

Country Status (4)

Country Link
US (1) US4716539A (fr)
BE (1) BE903901A (fr)
CA (1) CA1244954A (fr)
IT (1) IT1200903B (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7720901B1 (en) * 2006-05-26 2010-05-18 Altera Corporation Multiplier operable to perform a variety of operations

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3829673A (en) * 1972-06-20 1974-08-13 Floating Point Syst Inc Floating point arithmetic unit adapted for converting a computer to floating point arithmetic
GB2059123B (en) * 1979-09-22 1983-09-21 Kokusai Denshin Denwa Co Ltd Pcm signal calculator
US4484259A (en) * 1980-02-13 1984-11-20 Intel Corporation Fraction bus for use in a numeric data processor
US4488252A (en) * 1982-02-22 1984-12-11 Raytheon Company Floating point addition architecture
DE3232558A1 (de) * 1982-09-01 1984-03-01 Siemens AG, 1000 Berlin und 8000 München Digitaler dpcm-kodierer mit hoher verarbeitungsgeschwindigkeit
US4594679A (en) * 1983-07-21 1986-06-10 International Business Machines Corporation High speed hardware multiplier for fixed floating point operands

Also Published As

Publication number Publication date
IT1200903B (it) 1989-01-27
CA1244954A (fr) 1988-11-15
IT8523263A0 (it) 1985-12-18
US4716539A (en) 1987-12-29

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Legal Events

Date Code Title Description
RE Patent lapsed

Owner name: GTE COMMUNICATION SYSTEMS CORP.

Effective date: 19901231