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SE9203683L - Anordning för omvandling av ett binärt flyttal till en 2- logaritm i binär form eller omvänt - Google Patents

Anordning för omvandling av ett binärt flyttal till en 2- logaritm i binär form eller omvänt

Info

Publication number
SE9203683L
SE9203683L SE9203683A SE9203683A SE9203683L SE 9203683 L SE9203683 L SE 9203683L SE 9203683 A SE9203683 A SE 9203683A SE 9203683 A SE9203683 A SE 9203683A SE 9203683 L SE9203683 L SE 9203683L
Authority
SE
Sweden
Prior art keywords
logarithm
binary
floating
point number
adder
Prior art date
Application number
SE9203683A
Other languages
Unknown language ( )
English (en)
Other versions
SE470542B (sv
SE9203683D0 (sv
Inventor
Erik Hertz
Original Assignee
Foersvarets Forskningsanstalt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Foersvarets Forskningsanstalt filed Critical Foersvarets Forskningsanstalt
Priority to SE9203683A priority Critical patent/SE470542B/sv
Publication of SE9203683D0 publication Critical patent/SE9203683D0/sv
Priority to JP6514047A priority patent/JPH08504046A/ja
Priority to DE69328261T priority patent/DE69328261T2/de
Priority to PCT/SE1993/001039 priority patent/WO1994014245A1/en
Priority to EP94902160A priority patent/EP0673564B1/en
Publication of SE9203683L publication Critical patent/SE9203683L/sv
Publication of SE470542B publication Critical patent/SE470542B/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/556—Logarithmic or exponential functions
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/14—Conversion to or from non-weighted codes
    • H03M7/24—Conversion to or from floating-point codes

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Analogue/Digital Conversion (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
SE9203683A 1992-12-07 1992-12-07 Anordning för omvandling av ett binärt flyttal till en 2- logaritm i binär form eller omvänt SE470542B (sv)

Priority Applications (5)

Application Number Priority Date Filing Date Title
SE9203683A SE470542B (sv) 1992-12-07 1992-12-07 Anordning för omvandling av ett binärt flyttal till en 2- logaritm i binär form eller omvänt
JP6514047A JPH08504046A (ja) 1992-12-07 1993-12-02 浮動小数点２進数を２進形式における対数に変換しまたはその逆変換をするための装置
DE69328261T DE69328261T2 (de) 1992-12-07 1993-12-02 Vorrichtung zur konversion einer binären gleitkommazahl in einen binären logarithmus mit der basis 2 oder dessen umkehrung
PCT/SE1993/001039 WO1994014245A1 (en) 1992-12-07 1993-12-02 A device for conversion of a binary floating-point number into a binary 2-logarithm or the opposite
EP94902160A EP0673564B1 (en) 1992-12-07 1993-12-02 A device for conversion of a binary floating-point number into a binary 2-logarithm or the opposite

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9203683A SE470542B (sv) 1992-12-07 1992-12-07 Anordning för omvandling av ett binärt flyttal till en 2- logaritm i binär form eller omvänt

Publications (3)

Publication Number Publication Date
SE9203683D0 SE9203683D0 (sv) 1992-12-07
SE9203683L true SE9203683L (sv) 1994-06-08
SE470542B SE470542B (sv) 1994-07-25

Family

ID=20388052

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9203683A SE470542B (sv) 1992-12-07 1992-12-07 Anordning för omvandling av ett binärt flyttal till en 2- logaritm i binär form eller omvänt

Country Status (5)

Country Link
EP (1) EP0673564B1 (sv)
JP (1) JPH08504046A (sv)
DE (1) DE69328261T2 (sv)
SE (1) SE470542B (sv)
WO (1) WO1994014245A1 (sv)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE502892C2 (sv) * 1994-06-01 1996-02-12 Foersvarets Forskningsanstalt Anordning för omvandling av ett binärt flyttal till en 2-logaritm i binär form eller omvänt
US6289367B1 (en) * 1998-11-16 2001-09-11 Texas Instruments Incorporated Digital signal processing circuits, systems, and method implementing approximations for logarithm and inverse logarithm
US7284027B2 (en) 2000-05-15 2007-10-16 Qsigma, Inc. Method and apparatus for high speed calculation of non-linear functions and networks using non-linear function calculations for digital signal processing
CN100340940C (zh) * 2004-04-02 2007-10-03 明基电通股份有限公司 对数转换方法及其装置
US7421139B2 (en) 2004-10-07 2008-09-02 Infoprint Solutions Company, Llc Reducing errors in performance sensitive transformations
CN103455302A (zh) * 2012-05-31 2013-12-18 上海华虹集成电路有限责任公司 用硬件实现对数运算的电路
US11775805B2 (en) * 2018-06-29 2023-10-03 Intel Coroporation Deep neural network architecture using piecewise linear approximation

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1962725A1 (de) * 1969-12-15 1971-11-11 Foerster Inst Dr Friedrich Binaer kodierter,dekadisch einstellbarer logarithmischer Teiler
JP2589475B2 (ja) * 1986-08-19 1997-03-12 パイオニア株式会社 デイジタルレベル表示装置

Also Published As

Publication number Publication date
DE69328261D1 (de) 2000-05-04
SE470542B (sv) 1994-07-25
DE69328261T2 (de) 2000-11-30
SE9203683D0 (sv) 1992-12-07
EP0673564A1 (en) 1995-09-27
JPH08504046A (ja) 1996-04-30
EP0673564B1 (en) 2000-03-29
WO1994014245A1 (en) 1994-06-23

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