AU2002218137A1 - Memory configuration with i/o support - Google Patents

Memory configuration with i/o support

Info

Publication number: AU2002218137A1
Authority: AU; Australia
Prior art keywords: support; memory configuration; memory; configuration
Prior art date: 2000-10-13
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Abandoned

Application number

AU2002218137A

Inventor

Volker Aue

Wolfram Drescher

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

NXP Semiconductors Germany GmbH

Original Assignee

Systemonic AG

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2000-10-13

Filing date

2001-10-15

Publication date

2002-04-22

2001-10-15 Application filed by Systemonic AG filed Critical Systemonic AG

2002-04-22 Publication of AU2002218137A1 publication Critical patent/AU2002218137A1/en

Status Abandoned legal-status Critical Current

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

Engineering & Computer Science (AREA)
Theoretical Computer Science (AREA)
Physics & Mathematics (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Multi Processors (AREA)
Bus Control (AREA)

AU2002218137A 2000-10-13 2001-10-15 Memory configuration with i/o support Abandoned AU2002218137A1 (en)

Applications Claiming Priority (3)

Application Number	Priority Date	Filing Date	Title
DE10050980A DE10050980A1 (en)	2000-10-13	2000-10-13	Memory configuration with I / O support
DE10050980.0		2000-10-13
PCT/DE2001/003916 WO2002031658A2 (en)	2000-10-13	2001-10-15	Memory configuration with i/o support

Publications (1)

Publication Number	Publication Date
AU2002218137A1 true AU2002218137A1 (en)	2002-04-22

Family

ID=7659799

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
AU2002218137A Abandoned AU2002218137A1 (en)	2000-10-13	2001-10-15	Memory configuration with i/o support

Country Status (8)

Country	Link
US (1)	US7143211B2 (en)
EP (1)	EP1328862B1 (en)
JP (1)	JP2004511851A (en)
KR (1)	KR100777497B1 (en)
CN (1)	CN1256661C (en)
AU (1)	AU2002218137A1 (en)
DE (2)	DE10050980A1 (en)
WO (1)	WO2002031658A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
KR101275628B1 (en) *	2011-09-29	2013-06-17	전자부품연구원	Electronic chip using dual-port memory based TCM capable of variable area size
ES2906065T3 (en) *	2016-12-30	2022-04-13	Euromed Inc	Adhesive patch containing an enhanced release coating system

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4571671A (en) *	1983-05-13	1986-02-18	International Business Machines Corporation	Data processor having multiple-buffer adapter between a system channel and an input/output bus
JPS60129865A (en) *	1983-12-19	1985-07-11	Matsushita Electric Ind Co Ltd	Communication device
JPS61118847A (en) *	1984-11-15	1986-06-06	Nec Corp	Simultaneous access control system of memory
JPS6292050A (en) *	1985-10-18	1987-04-27	Canon Inc	input/output control device
US4949301A (en) *	1986-03-06	1990-08-14	Advanced Micro Devices, Inc.	Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM's address inputs
JPH0193846A (en) *	1987-10-05	1989-04-12	Fuji Xerox Co Ltd	Dual port memory controller
JPH0333952A (en) *	1989-06-29	1991-02-14	Shikoku Nippon Denki Software Kk	Image memory writer
US5224213A (en) *	1989-09-05	1993-06-29	International Business Machines Corporation	Ping-pong data buffer for transferring data from one data bus to another data bus
DE69031948T2 (en) *	1990-11-02	1998-04-23	St Microelectronics Srl	System for storing data on a FIFO basis
US5386532A (en) *	1991-12-30	1995-01-31	Sun Microsystems, Inc.	Method and apparatus for transferring data between a memory and a plurality of peripheral units through a plurality of data channels
JPH05334230A (en) *	1992-05-29	1993-12-17	Matsushita Electric Ind Co Ltd	Dual port memory access control circuit
EP0660954A1 (en) *	1992-09-21	1995-07-05	Unisys Corporation	Multiported buffer memory system for disk drive complex
FR2702322B1 (en) *	1993-03-01	1995-06-02	Texas Instruments France	Memory at interconnection points, in particular for the communication of telecommunication terminals operating at different frequencies.
JPH07182849A (en) *	1993-12-21	1995-07-21	Kawasaki Steel Corp	FIFO memory
US5487049A (en) *	1994-11-23	1996-01-23	Samsung Semiconductor, Inc.	Page-in, burst-out FIFO
JPH08328994A (en) *	1995-05-30	1996-12-13	Toshiba Corp	Information processing device
DE19526798C1 (en) *	1995-07-14	1997-05-15	Hartmann & Braun Ag	Arrangement for controlling bidirectional, asynchronous and serial transfer of data packets
JPH09319693A (en) *	1996-05-28	1997-12-12	Hitachi Ltd	Data transfer device and parallel computer system
DE19713178A1 (en) *	1997-03-27	1998-10-01	Siemens Ag	Circuit arrangement with a processor and a data memory
JPH10301839A (en) *	1997-04-25	1998-11-13	Matsushita Electric Ind Co Ltd	Memory control method and semiconductor device
US6067595A (en) *	1997-09-23	2000-05-23	Icore Technologies, Inc.	Method and apparatus for enabling high-performance intelligent I/O subsystems using multi-port memories
JP3263362B2 (en) *	1998-06-05	2002-03-04	三菱電機株式会社	Data processing device
US6166963A (en) *	1998-09-17	2000-12-26	National Semiconductor Corporation	Dual port memory with synchronized read and write pointers
JP3226886B2 (en) *	1999-01-29	2001-11-05	エヌイーシーマイクロシステム株式会社	Semiconductor memory device and control method thereof
JP2000268573A (en) *	1999-03-18	2000-09-29	Mitsubishi Electric Corp	Semiconductor storage device
US6907480B2 (en) *	2001-07-11	2005-06-14	Seiko Epson Corporation	Data processing apparatus and data input/output apparatus and data input/output method

2000
- 2000-10-13 DE DE10050980A patent/DE10050980A1/en not_active Ceased
2001
- 2001-10-15 US US10/399,073 patent/US7143211B2/en not_active Expired - Lifetime
- 2001-10-15 DE DE50106472T patent/DE50106472D1/en not_active Expired - Lifetime
- 2001-10-15 EP EP01986784A patent/EP1328862B1/en not_active Expired - Lifetime
- 2001-10-15 JP JP2002534979A patent/JP2004511851A/en active Pending
- 2001-10-15 KR KR1020037005204A patent/KR100777497B1/en not_active Expired - Fee Related
- 2001-10-15 AU AU2002218137A patent/AU2002218137A1/en not_active Abandoned
- 2001-10-15 WO PCT/DE2001/003916 patent/WO2002031658A2/en not_active Ceased
- 2001-10-15 CN CNB018173195A patent/CN1256661C/en not_active Expired - Fee Related

Also Published As

Publication number	Publication date
EP1328862A2 (en)	2003-07-23
CN1256661C (en)	2006-05-17
US7143211B2 (en)	2006-11-28
WO2002031658A2 (en)	2002-04-18
CN1470016A (en)	2004-01-21
DE10050980A1 (en)	2002-05-02
WO2002031658A3 (en)	2003-02-27
JP2004511851A (en)	2004-04-15
US20040054856A1 (en)	2004-03-18
EP1328862B1 (en)	2005-06-08
KR20030064405A (en)	2003-07-31
KR100777497B1 (en)	2007-11-20
DE50106472D1 (en)	2005-07-14

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AUPQ910500A0 (en)	2000-08-24	Support means
AU2002324462A1 (en)	2003-01-21	Tmart memory
AU2001244847A1 (en)	2001-10-03	Water-retaining structure
HUP0302087A3 (en)	2004-03-01	Support
AU4657001A (en)	2001-09-17	Displacing arrangement
AU2000261840A1 (en)	2002-02-13	Bis-beta-hydroxyethyl terephthalate
AU2001262855A1 (en)	2001-12-11	Support structure
AU2120200A (en)	2000-08-18	Cache memory
AU7304700A (en)	2001-04-24	Memory devices
AU2936800A (en)	2001-09-12	Memory with call out function
AU2659001A (en)	2001-07-16	Head support
AU2002218137A1 (en)	2002-04-22	Memory configuration with i/o support
AU2002239502A1 (en)	2002-06-03	Boundary addressable memory
PL360674A1 (en)	2004-09-20	Support
AU2001276979A1 (en)	2002-02-05	Magnetoresistive structure
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AU3816400A (en)	2001-10-15	Structure
AU2001262372A1 (en)	2001-12-03	Support arrangement
AU2001100415A4 (en)	2001-11-01	Bait support
AUPR127200A0 (en)	2000-11-30	Support structure