MXPA97009060A - An ani collecting bar data transfer system - Google Patents

Abstract

The present invention relates to a bus system for data transmission, which includes a plurality of nodes coupled together by a ring bus. The ring bus transmits in successive busbar cycles, each busbar cycle containing a plurality of busbar words. One of the bus bar words in the bus bar cycle is a bar cycle synchronization word, and the rest of which is data words. A plurality of data words are assigned to a plurality of data channels.

Description

ÜN RING COLLECTOR BARRIER DATA TRANSFER SYSTEM The present invention relates to data busbar systems, and in particular, to a ring bus data transfer system useful for interconnecting consumer electronic equipment. Systems, such as digital video signal processing systems, process data at high data rates, correspondingly require busbar systems with a high bandwidth for data communication. For example, digital video data in MPEG format exhibits data rates of 4 to 8 Mbits per second. A busbar system based on packet data can provide enough bandwidth. However, the hardware and software to implement packaged systems can be expensive, making them impractical for the consumer's electronic equipment. In addition, a packet bus may require excessive "surplus," such as packet processing delays, which preclude the provision of the high data rates required for MPEG data transfer. Also, MPEG decoders in video signal processing systems rely on data arriving at a relatively constant speed (ie, they have a relatively constant transmission delay). In other words, the data jump should be relatively low. A bus system, such as a packet system, may also have too much variation in the delay of data transmission between packets to operate properly with the MPEG decoders. A high-speed data transfer busbar, which can be built with relatively low cost hardware and software, that does not require a high data surplus, and has a relatively constant transmission delay, is desirable to interconnect the electronic equipment of the consumer, in particular the video signal processing equipment. In accordance with the principles of the present invention, a data transmission busbar system includes a plurality of nodes coupled together by a ring bus. The ring bus transmits the data in successive busbar cycles, each busbar cycle containing a plurality of busbar words. One of the bus bar words in the bus bar cycle is a bar cycle synchronization word, and the rest are data words. The plurality of data words are assigned to a plurality of data channels. The principles of the invention are incorporated in the BeeBus (BBUS), which is a high-speed data bus bar system, which can be used to transfer digital video data. The BBUS system is a time division multiplexed busbar (TDM) with a total capacity of 88 Mbits / second. The BBUS is designed to transfer data in a transparent manner from a source node to a destination node on the bus. The BBUS operates by serial transmission of nine-bit words from node to node on the ring. The synchronization is maintained between the nodes by means of the transmission of 88-word busbar cycles of nine bits, the starting word of each busbar cycle being a synchronization word of the busbar cycle. Because it may be desired to connect with electronic consumer equipment that has been designed to join an electronic busbar of the prior art consumer, called CEBUS, the BBUS system includes a control channel compatible with CEBUS. A bit of the synchronization word of the busbar cycle carries the data for the control channel compatible with CEBUS. The BBUS is designed to carry eight data channels, which can be grouped into blocks to provide the necessary capacity for any combination of channel number and channel capacity, provided that the total number of channels is eight or less, and that the total assigned capacity is 88 Mbs or less.

The control busbar compatible with CEBUS included in the BBUS system, has a message structure that does not involve arbitration on the transmission. Each device has a pre-assigned control channel slot with a capacity well in excess of 10 kbs. Each device has the capacity of channels to receive messages from another 31 devices simultaneously. However, it is envisioned that the receiving device processes only one message at a time. Accordingly, the receiving office will make arbitration, and not the transmitting device. The receiving device will process the messages in a cyclic way, one message at a time. Because the length of the message is approximately 32 bytes, all messages on the control channel will be sent with this fixed length, and all messages will start with the same time slot of the control cycle. This slot is the basic synchronization of the operating system. It is presented every 32 slots of the control device by 32 message slots, which is approximately 8 milliseconds, as explained below. Therefore, a control channel message can be sent every 8 milliseconds. (16 device-to-device messages could be sent simultaneously.) This compares to approximately 25 milliseconds for a CEBUS control message.

Figure 1 is a diagram of a data bus system in accordance with the principles of the present invention. Figure 2 is a diagram illustrating the format of the data transmitted around the ring of nodes illustrated in Figure 1. Figure 3 is a block diagram of a prior art configuration for interconnecting nodes in a ring structure. Figure 4 is a block diagram of a method for interconnecting nodes in a ring structure embodying the present invention. Figure 5 is a block diagram of the circuits necessary to connect a node with the input and output cables. Figure 6 is a flow diagram illustrating the operation of a data bus system according to the invention. Figure 1 is a block diagram of a data bus system in accordance with the principles of the present invention. Five nodes are interconnected, node A, node B, node C, node D and node E, by means of a busbar with a ring structure as shown in Figure 1. Data is transferred from a node to the next in the ring, in a format illustrated in Figure 2. In Figure 2, the data words are represented by a series of rectangles in the upper part of the figure. The basic data word in the system contains nine bits. Eight bits (one byte) are the payload, and one bit is used to control the level of the link. There are 88 words of nine-bit data transmitted in a bus cycle. With a 100 MHz bit-rate clock (that is, a period of 10 nanoseconds), each 9-bit word is 90 nanoseconds long. Therefore, the fundamental bus cycle in the system is 7,920 nanoseconds, or 88 counts of nine 10 nanosecond clock cycles. A synchronization word is transmitted through the bus master cycle every 7,920 nanoseconds. This provides a payload of 87 data words every 7,920 nanoseconds, or 10,984,848 bytes / second. The maximum data rate of the BBUS, is, therefore, of 87,878,787.88 Mbits / second. The data words in the data stream are assigned among 8 channels. Each data channel receives a slot, and transmits a word every 90 nanoseconds x 8 channels = .720 microseconds. Consequently, the data channels are independent channels of the protocol with a constant delay and with a jump of less than 1 microsecond per 11 Mbps capacity. Referring to Figure 2, the first nine-bit data word of a bus cycle is a synchronization word (SINC). This is followed by a data word that carries data for channel 1 (CH1). This is followed by data words that carry data for channels 2 to 8 (CH2 to CH8). This cycle of data words for the respective channels is repeated for the 87 time slots remaining in the bus cycle. As will be described in more detail later, a bit of the synchronization word is assigned to the control channel compatible with CEBUS. Accordingly, the control bus has a maximum data rate slightly higher than 126 kbits / second. The production of the control channel is slightly higher than 10 kbits, just like CEBUS, due to the CEBUS CSMA-CD arbitration method used to arbitrate access to the busbar by the devices coupled to the CEBUS. The basic physical and electrical connectivity of the BBUS is a chained daisy ring with one input and one output on each device or instrument. Figure 3 is a block diagram of a prior art configuration for interconnecting nodes in a ring structure. Each node of Figure 3 includes an input connector, illustrated on the lower left side of each node, and an output connector, illustrated on the lower right side of each node. A first cable is connected between the output connector of node A to the input connector of node B. In a similar manner, a cable is connected between the output connector of node B and the input connector of node C (not shown) ), and in general from the output connector of a node to the input connector of the next node. The last node illustrated in Figure 3 is node E. To complete the ring, a cable is connected from the output connector of node E to the input connector of node A. To avoid the need to make the final link in the daisy chain to connect the last node with the first node, the data of the return line can be multiplexed in time with the line forward. Alternatively, a set of wires may be included in each cable for the inverse line. The last approach is the preferred one, because the time multiplexing of lines in reverse and forward reduces the available capacity by half. Figure 4 is a block diagram of a method for interconnecting nodes in a ring structure embodying the present invention. In Figure 4, each cable includes the necessary wires for the forward line from one node to the succeeding node, and the wires for the return line from the output connector of the final node to the input connector of the first node. When wires from the line are included in reverse in the cable as in Figure 4, the BBUS cable of the illustrated mode requires eight wires, four in each direction. In addition, a ground / protection is included, and a bolt to indicate that a cable is connected to the port. This pin is wired to the ground / protector. Figure 5 is a block diagram of the circuits in a node required to connect a node with the input and output cables. In Figure 5, an input connector 20 receives a cable from a preceding node. This cable is terminated at a pin 10, and receives the wires forming the line forward from the preceding node to this node, and the wires forming the line in reverse from the end node to the first node. In addition, as described above, a pin of the plug is coupled to a source of a reference potential (ground). The data and clock wires from the forward line in the input connector 20, are coupled with a first input terminal of a first switching circuit 30. An output terminal of the first switching circuit 30, is coupled with a input terminal of a serial-to-parallel input change register 40, and an output terminal of the input register 40 is coupled to the node utilization circuits (not shown), of a known design. The utilization circuits (not shown) of the node are also coupled with an input terminal of a parallel-to-series 50 output change recorder. An output terminal of the output register 50 is coupled to a first input terminal of a second switching circuit 60, and with an input terminal of an output connector 70. The output connector 70 receives a cable from the next successive node. This cable is terminated in a pin 90. Pin 90 also includes wires that form the line forward to the next succeeding node, and wires that form the line in reverse from the last node to the first node. The output terminal of the output register 50 is coupled to the line forward through the output connector 70 and the pin 90. The wires of the reverse line are received in the pin 90, and are supplied to the output connector 70. The input wires from the reverse line are coupled with a second input terminal of the first switch 30, and with a second input terminal of the second switch 60. An output terminal of the second switch 60 is coupled with an output terminal for the reverse line in the input connector 20. The output terminal of the second switch 60 is then coupled with the line in reverse through the input connector 20 and the plug 10. The input connector 20 and the output connector 70 also have a wire connected to a logic circuit 80. The pin of the input connector coupled with the ground wire illustrated in the pin 10, and the pin of the output connector 70 coupled with the The ground wire illustrated on pin 90 is coupled with logic circuit 80. This wire will be driven to positive on input connector 20 and output connector 70, and will be driven to negative by the ground terminal on pin 10. or 90, respectively. The respective control output terminals of the logic circuit 80 are coupled with the corresponding control input terminals of the first and second switches 30 and 60. In operation, when a cable is inserted into the input connector 20 or the connector of output 70, logic circuit 80 will detect this by the ground potential at the input terminal corresponding to that input connector. This is used to direct the input signal from the appropriate connector (20 or 70) to the input register, and to direct the output register 50 to the appropriate connector 20 or 50. For example, the first node in the chain of Daisy will not have any cable connected to its input connector 20, but it will have a cable connected to its output connector 70. The logic circuit 80 detects this configuration. It conditions the first switch 30 to couple the input wires from the reverse line on the pin 90, with the input register 40. The output register 50 couples with the forward line of the output connector 70. This first device also is designated as the master busbar. In a similar manner, the last device of the daisy chain will have a cable connected to its input connector 20, but it will not have a cable connected to its output connector 70. The logic circuit 80 detects this configuration. It conditions the first switch 30 to couple the wires from the forward line of the input connector 20 to the input register 40. It also conditions the second switch 60 to couple the output register 50 with the wires of the line in reverse on the connector input 20. Devices in the middle of the daisy chain have wires connected to both the input connector 20 and the output connector 70. The logic circuit 80 detects this configuration. It conditions the first switch 30 to couple the wires from the line forward at the input connector 20 to the input register 40. The output register 50 couples with the line wires forward at the output connector 70. conditions the second switch 60 to couple the wires from the line in reverse at the output connector 70, to the wires of the line in reverse at the input connector 20. No processing connection is made with the wires of the line in reverse, and they simply connect through the instrument. This configuration reduces the need for software that controls the operation of the node to determine port connectivity. If the system considerations do not require a protector on the cable, an RJ45 connector can be used. In this case, the presence or absence of a cable in a connector will be determined by detecting clocks in the input wires, and measuring the current in the output wires. In this embodiment, these detection circuits will be connected between the input connector 20 and the logic circuit 80, and between the output connector 70 and the logic circuit 80, and will supply logic signals to the logic circuit 80 to indicate the presence or absence of a busbar connection, based on the results of that detection. The use of an RJ45 connector allows the use of a relatively inexpensive cable and a printed circuit board (PCB) connector, which may be desirable in consumer electronics systems. The protocol of the control channel in the BBUS is similar to that used for the CEBUS. The message structure and the coding are substantially the same as those of CEBUS. This results in a message approximately every 25 milliseconds. The control channel is described in more detail later. The synchronization of the BBUS is handled in the following manner. A problem with a daisy chain ring bus connected by means of a serial link, is that a node must initiate an initialization process to make all nodes operate in synchronization, and then handle other initialization operations, such as the node numbering. This process is greatly simplified, if a node can become the master without discussion of ring communication. This is done by defining the master bus as a node that has no cable directly connected to its input connector 20, which can be determined as described above. The master bus will initiate the following operations (described in more detail below): 1) Word synchronization 2) Cycle synchronization 3) Node numbering 4) Delay Compensation The format of data words in the BBUS is as follows. The node-to-node communication is performed by a serial transmission of bits, from a 9-bit word from one node to the next, as described above. The word is read in the node 40 input change register, transferred to the output change register 50 (as indicated in ghost in Figure 5), and then transmitted to the next node.

A bit of the word, for example, the most significant bit, is a control bit of the link level. An example of the definition of the control bit is: 1 = Synchronization information 0 = Payload For example, refer to Figure 2. The synchronization word (SINC) inserted in the data stream at the beginning of each cycle of the bar The collector, indicated by the thick rectangle, includes nine bits, as indicated by the expansion of bits below the representation of the data stream. The most significant bit, indicated by a thick rectangle in the bit expansion, is a logical bit. On the other hand, the nine-bit data word that carries the word 1 of the second channel in this cycle has a more significant bit, also indicated by a thick rectangle, which is a bit of logical '0', as indicated in the expansion of bits below the representation of the data stream. The initialization of the ring bar of the daisy chain, referred to above, begins with word synchronization. Word synchronization is achieved by the master node transmitting a synchronization code (described in more detail below) at its output connection 70, after energy is initially applied to the system. Then the master node begins to examine the data received in its input connection 20 for the return of the word synchronization code, by examining its input register 40 (which, in a preferred embodiment, is a 19-bit register) , until the word synchronization code is detected. The following description is based on the word synchronization code, which is a single nine-bit word. However, the word synchronization code may be a sequence of two or more code words. When the word synchronization code has been detected, word synchronization has been achieved. The delays in this ring of nodes can be a non-integer number of a nine-bit word, as a result, for example, of processing and delays related to the cable. To adjust the time delays of the non-integer word, the input change register 40 may contain a number of bits greater than that required to store a data word. As an example, a preferred embodiment of the input change register 40 contains 19 bits. To assert the delay, the data in the entry register 40 is examined in whole word times. The position of the nine-bit synchronization word in the 19-bit shift register indicates a delay in relation to a whole word time. The delay is used to adjust the time of the following words. For adjacent nodes, with the exception of the master mode, the clock accompanies the data, and, therefore, it is delayed just like the data, so that there is no apparent time delay for the node. Since the master node has a reference clock, the delay through the complete ring is apparent to the master node. The extension of the delay is limited by the length of the cable to less than one word, with the exception of the entire word delays at each node. The 19-bit input change register 40 of each non-master node can be used to provide the additional word delays that are necessary, in a manner that will be described in more detail below. The time signals in each node are provided as follows. Each node has two clocks. The input data from the input connector 20 to the input change register 40 is changed by the clock derived from the strobes from the immediately preceding node, as received at the input connection 20 (or at the output connection). 70 for master mode). Each node also has its own internal crystal clock that it uses to boost its output 50 shift register and its internal logic. Therefore, it is possible that the internal clock is faster or slower than the input clock by a small amount, and this must be corrected. In the event that the input clock is faster than the internal clock, the additional input clock cycle is absorbed allowing the input word to be changed an additional bit in the input change register 40. In the case of that the internal clock is faster than the input clock, the data entry time cycle, as defined by the internal clock, extends an extra clock cycle, while the input data is being changed to the recorder input change 40. The above has the cumulative effect of slowing the ring down to the internal clock speed of the slowest node. The bus cycle counters inside each node are synchronized by resetting all cycle counters when a cycle synchronization word (described below) is read into a node at the end of the input cycle. Consequently, each node passes through the same states as the previous node, delayed by a received word time plus the propagation delay of the cable. The time state of each node, with the exception of the master node, is synchronized by receiving the synchronization word of the cycle, to compensate for the delay. For example, if the total cable length is limited to 10 meters, then the total delay through the cable is of the order of 50 nanoseconds, or five clock cycles for a 100 MHz clock. Therefore, less than one word on the wire. The length of the cable can be significantly longer when the return line is included, and the added length should be considered when designing a cable impeller. Also, each node has a potential additional delay that is less than a clock cycle. The basic busbar cycle described above, and illustrated in Figure 2, is 88 nine-bit words, or 88 x 9 = 792 clock cycles of duration. The channel counter can be designed in such a way that, if any data channel needs more than 1 Mbps capacity, additional slots can be assigned inside the basic channel data counter, in such a way that jumps are minimized. To do this, when multiple nodes use data channels of arbitrary size, the capacity assignment task is assigned to the application level, and at the application level it is given the task of assigning time slots for each data channel . In an alternative way, an approach that reduces the surplus of the application, is to pre-assign 8 main channels with a capacity of 11 Mbs, each to ensure a lesser jump of 1 microsecond / channel, as illustrated in Figure 2. These 8 main channels can now be assigned simply, and the channel counter will be designed to extend these 8 main channels among the 88 slots of • channels, also as illustrated in Figure 2. Each of the 8 slots are independent of each other, in the determination of the jumps, and can be assigned independently by each node (but only one node can use each one) of the 8 channels). The control channel is assigned separately, and has a balance of 8 microseconds. With respect to node synchronization and node address, several features must be provided. These features include word synchronization and bus cycle synchronization (both described above, message synchronization, node address, and an indication that there is no data present in a data slot (all described below). For this purpose, several special synchronization and address words are provided, and are identified by having a logical 'l' as the most significant bit in the nine-bit data word.In the present embodiment, the system is limited to no. Therefore, only 5 bits of a byte (for example, bits 3 to 7 of a byte having the bits designated 0 to 7), are needed to identify a destination node address. a source node address is implied by the time slot, although that information can be sent in an additional byte if desired.The remaining 3 bits of a byte (for example, bits 0 through 2) are They use to identify eight special synchronization and direction codes, which define different functions, as shown in Table 1.

TABLE 1 The first row of Table 1 shows an OOH code (that is, 00 in hexadecimal) of the special synchronization word that is used to indicate that there is no data present for a particular time slot. This code is needed, because the time slots are always present in the data stream, and the destination receiver node will search the assigned channel in each time slot.

This word allows the source node to recognize that there was no data available for a particular time slot. The second row of Table 1 shows the word synchronization code, described above. In this code, bits 0 to 2 are equal to 111. The third row of Table 1 shows an address code word for specifying a destination address. This code is not needed when the CEBUS protocol is used to establish communication channels between the nodes. In that case, a destination address is already encoded in the control channel message, as described in the EIA IS-60 industry standard. In addition, the zero node address code is reserved for broadcast messages. The master node is node 1. Therefore, only 31 physical nodes are allowed in the system. When a message is broadcast, the sender assumes that it is received by all nodes. There is no recognition, and therefore, there is no certainty of reception. The fourth row of Table 1 shows a synchronization word of the busbar cycle, as illustrated in Figure 2. In the bus cycle cycle synchronization word, bits 0-2 are equal to 110. The least bit Significant of the bus cycle cycle synchronization word carries a bit for the control channel, and is indicated by an X in Table 1, to indicate a condition of "does not matter". When the 88 channel counter = 0, the control channel has a slot. If the node counter and the message length counter in the master are zero, the master sends the cycle synchronization code. When a sync word is received from the bus cycle, each node can reset its counters if it has lost synchronization. If a bus cycle cycle synchronization word is not detected within a reasonable time, the node can assume that the bus was broken. In a modality, the control channel can be assigned to the job of naming nodes. In this case, there is no need to assign names or numbers to the nodes. However, in a preferred embodiment, the master node provides node numbering as a part of the initialization process. After the word synchronization is performed as described above, the master sends the name command illustrated in the fifth row of Table 1, that is, with the bits 0-2 equal to 100, and with the address bits node (bits 3-7) set to 00001. The number in the node address bits of the transmitting node - the master node in this case. Each node that receives the name command increments the number represented by the node address bits, uses this number as its node address, and sends the name command with its own node address in the node address bits to the node. next node. The master stops the circulation of the command when it receives it after it has circulated around the cycle. If a node has a delay of two word times (described in more detail below), that node increments the number represented by the node address bits of the name word it receives by 2. Therefore, the node address of each node matches the delay time slot of that node. The sixth row of Table 1 represents a resource allocation request word of the link level. A link allocation resource request may be sent instead of a control channel message, setting bits 0-2 equal to 001. Each of bits 4 through 7 represents two adjacent data channels, for example , bit 7 represents slots 0 and 1 for a total capacity of 22 Mbs; bit 6 represents slots 2 and 3, and so on. It is envisaged that the resource allocation request word of the link level is used for simple nodes that do not have the capacity to use the control channel. When this node requires access to a busbar channel, it transmits to the busbar a resource assignment request with one of the bits corresponding to a desired pair of channels indicated in bits 4 to 7, instead of a word of destination message address.

When a successor node receives a resource assignment request, it passes the request unchanged to the next node if it has no conflict with the request. If the node is using the requested resources, it zeros the bit corresponding to the requested channel that is in use, and sends the modified word to the next node. The source node must then remove the ring request. There is no other fair rule or other arbitration. If the request returns without the channels being zeroed, the requesting node uses the channel. If the channel is not available, the requesting channel tests another of the four channel pairs. If there is no available channel, the process is stopped. The process could be resumed after a long random delay. This method of requesting the use of data channels is provided for nodes that intend to use the channel for long sessions, and for a few simple nodes without a control channel capability. The seventh row of Table 1 illustrates a word of ring delay adjustment, where bits 0-2 are equal to 011. In general, each node must remove the messages it puts on the ring. To do this, you must know the length of the delay on the ring in whole word times. This must be determined by the master node during the initialization process. The master node assumes that the delay is at least the number of nodes in the system. The master counts the number of clock cycles required for the return of the name command (described above). Then this count is rounded up to the next whole number of word cycles (of nine clock cycles), and is called the ring delay. As described above, each node, with the exception of the master node, is corrected in time for the cable length from the previous node, by receiving the word synchronization word. Therefore, even when the delay between the adjacent nodes (with the exception of the master node) can exceed a word length, for the receiving node, the delay appears to be zero. Therefore, in general, each node, with the exception of the master node, adds a delay of one word time. The master node sees the total delay of the cycle, and adjusts this delay to a multiple of eight word times, unless less than four nodes are connected in the cycle. If less than four nodes are connected, the delay is set to a multiple of four word times, and the system is configured to have four channels of 22 Mbs each. The ring delay is increased by using the ring delay adjustment word, until the total ring delay is corrected. The last row of Table 1 illustrates a payload data word. In a payload word, the most significant bit is a logical '0', and the rest of the eight bits carry data that is going to be transmitted from one node to another. The nodes do not remove the ring data (except as noted) during the initialization process, with the exception of the master node. The sync command of the bus cycle indicates the end of the initialization process. Each node removes its transmissions from the number of module 8 (or module 4) of words, after the command to synchronize the bus cycle. An alternative is an implementation of module 4, where each node must know that it is in a delay ring 4, or only the first four slots are allowed to be used. The latter is relatively easy to implement and reasonable, because, with only four nodes, the need for channel capacity in general is not that great. It is necessary to consider the ring delay when making the time slot assignments of the busbar. That is, the time slots of the bus must be a module of the total ring delay and the multiplexing frequency. One approach is to fix the module of the ring delay. Each node must have the ability to insert a delay of up to two 9-bit words into its entry change register 40, in the case that is the teacher. This delay can also be used to adjust the ring delay. Therefore, each node can be configured to enter a delay of one or two words. For a ring that includes only two or three nodes, the ring can be adjusted in this way to have a delay of four. In all other cases, the ring can be adjusted to have a delay that is a module of 8 word times. In any case, the ring delay setting is presented as follows. Next, the master node measures the total word delay around the ring. If it is not a module 8 (or 4), a word of ring delay adjustment is transmitted by the master to increase the delay. The first node that receives this word that has not already increased its delay (ie, its delay is still one word), is conditioned to receive its input word from the second nine bits of the entry 40 change register, instead of the first nine bits. In this way, this node introduces an extra word delay in the cycle, and now it has a delay of two words. This node then removes the word from the busbar. This process is repeated until the correct number of word delays has been added to the ring, and its word delay is module 8 (or module 4). An expert in this field will also note that the length of the ring cable should be limited to approximately 18 meters, to avoid the case of wiring by adding more than one word delay. With this system, it is relatively simple to add the 8-channel multiplexing limitation. The basic system (see Figure 2) is 11 cycles of 8 9-bit word slots. Every 88 slots, a slot is used for a synchronization word that contains one bit of control channel. The BBUS system includes a control channel compatible with CEBUS. As specified in the IS-60 industry standard, the CEBUS control channel provides a maximum bandwidth of lOk bits per second. Access to the control channel is arbitrated through the use of upper and lower states on the bus bar, much like an arbitration or wiring control channel. As described above and illustrated in Figure 2, the bus system includes a bus bar cycle of 7,920 microseconds, and a bar cycle synchronization word is sent each bar cycle. The arbitration information of the control channel and the data are placed in the control channel bit of the synchronization word of the cycle. This physical layer allows having a maximum data bit rate equal to the synchronization word rate of the bus cycle. The aspects of the protocol that correspond to the known Data Link, the Network and the Application Layers and the System Layer Manager of the CEBUS can be used to complete the control channel model. Also, the Dependent Sub-layer of the CEBUS Media can be used to encode and decode the data. In the following discussion, the values of bits 1 and 0 are used to indicate a higher or lower status signal in the control channel. For example, a higher status signal is when this field is set to a logic "1" signal, and the default lower status signal is a logical "0" signal. In a real implementation, this correspondence could be reversed. The CEBUS carrier multiple detection access protocol with the contention detection arbitration method (CSMA-CD), and access to the control channel, can be used to determine which node has access to the control channel. At some point in the CEBUS operation, it must be determined if arbitration is initiated for access to the control channel. There are many different known techniques to determine when to start an arbitration. For example, arbitration could be initiated whenever a node wants access to the control channel. In an alternative way, arbitration could be initiated whenever multiple nodes simultaneously wish to access the control channel. If arbitration is necessary, it can be triggered in a known manner, by monitoring the activity in the control channel, and arbitration is triggered when the bus bar has been inactive for more than some previously determined period of time.

When an arbitration is triggered, an eight-bit preamble is computed for each node that wants access to the control channel. In a preferred embodiment, this preamble is generated as a random number in each node, and is different for each arbitration. This will allow just access to the busbar. Alternatively, a preamble representing the relative priority of each node could be preassigned to each node. The preamble is used to arbitrate access to the control channel. The node that arbitrates successfully through the control channel is allowed to terminate the transmission of its message, and all other nodes must wait for the next available time interval (determined as described above) before attempting to arbitrate through the control channel . The preamble and the message are coded to be transmitted as an alternating sequence of upper and lower states. A symbol is represented by a state in the control bit of the cycle synchronization word, or a series of states in the successive cycle synchronization word control bits. The value of the symbol is transmitted for the amount of time until the next state transition. There are four basic symbols: logical '0', logical '1', End of Field (EOF) and End of Package (EOP). Other symbols are possible, such as Preamble Field End, and Symbol Field End, but are not used in the example system described below. A bus cycle (7,920 microseconds) is equal to a Unit Symbol Time (UST). The coding of symbols is as follows: 1 UST = 1 2 UST = 0 3 UST = EOF 4 UST = EOP Any of the symbols that carry information (1, 0, EOF, EOP) can be represented by either higher status signals or lower, or a series of consecutive upper or lower status signals. For example, a logical '1' signal is represented by a single higher status signal '1' or a single lower status signal '0'. A logical '0' signal is represented by two consecutive upper state signals '11', or two consecutive lower status signals '00', and so on. Accordingly, bits * 0101 'in the preamble can be represented by the control channel signals: 001001, ie two consecutive lower status signals, which represent a logical' 0 * signal, followed by a single signal upper state representing a logical »1 'signal, followed by two consecutive lower status signals representing a logical' 0 'signal, followed by a single higher status signal, representing a logical' l 'signal. In a similar manner, the same preamble bits (i.e., example '0101') can be represented by the control channel signals: 110110. It is the time lapse between the state transitions that determines the value of the symbol . The initial arbitration is presented by determining whether the control channel's idle time conditions are met. During periods of inactivity of the control channel, status signals are placed in the synchronization word of the cycle. Next we have the definitions of certain relevant terms. The "Control Bit Field" (CBF) is the bit in the synchronization word of the cycle that contains the information of the CEBUS control channel. A "Control Channel Cycle" begins when a node first places a higher state in the CBF, and ends when a "End of Package" symbol (defined above) is transmitted through the node that wins the arbitration, or there is a time outside the cycle. The "Writing Node" is the first node that places a higher state in the CBF during the first cycle of the control channel. This starts the arbitration cycle of the control channel. The "Competitive Nodes" are all the nodes that compete for the control channel located after the write node in the cycle. The "Late Nodes" are all the nodes that compete for the control channel that are located before the write node in the cycle, and arbitration begins during the next bus synchronization cycle. Referring again to Figure 1, assume that Node A is the master node for the bus, and assume that Node C is the "Writing Node". Nodes D and E can be competing nodes in the same busbar cycle. Nodes A and B can also be competing nodes, but they are referred to as "late nodes", because they initiate arbitration in the next bus synchronization cycle. The master node A receives the CBF from the node E, once some node has initiated a Control Bar Collection Cycle. Otherwise, it establishes the CBF in the lower state, 0. The arbitration rules are as follows: First, a node can compete for access to the CEBUS control channel, with the understanding that it has complied with all the requirements of idle time of the IS-60 control channel. These time requirements will start from the last highest state observed in the CBF. Second, the output of the CBF from a node must be a higher state if that node receives a CBF that has the upper state. The exceptions to this rule are given immediately. Nodes that are not contending for access to the control channel, pass the CBF received without changes to the next node. Third, if a node puts a CBF that has a lower state in the control channel, and receives back a CBF that has a higher state in the next synchronization word of the bus cycle, that node stops contending for the channel of control. Fourth, if a node is (still) competing for the control channel, and the status of the next CBF exit (based on the coded random preamble) is a higher state, this node will set the CBF in the upper state, even when it receives a higher state. Fifth, the first node that successfully completes the transmission of its coded preamble, and a "End of field" symbol (defined above), wins the arbitration of the control channel. The rules for changing the CBF are as follows. First, the first node asserting a higher status signal during the bus cycle after the control channel inactivity time requirements are met, is the write node. Second, the CBF value can not be changed from the higher state, except by the write node. Third, all competing nodes can change the CBF from a lower state to a higher state. Fourth, the designation of a node as the writing node can be inherited by any node that changes the CBF from the lower state to the upper state. That is, if a node is not initially the writing node, and that node receives a lower state CBF, but changes it to a higher state based on its coded preamble, that node becomes the writing node. Fifth, the state of the write node is lost by the node previously designated as the write node, if that node receives a CBF different from the one it asserted in the control channel during the previous bus cycle. In addition, that node ceases to contend for access to the control channel. The described operation can be better understood by referring to an example of an arbitration operation that is shown in the form of a flowchart in Figure 6. In Figure 6, arbitration begins in step 600. Step 605 determines whether a node is contending for access to the control channel, for example, if the node has to send a control message. For a node that is not contending for access to the control channel, step 605 is followed by steps 660 and 665, which pass each state of CBF received through the node unchanged until the end of the arbitration. When the arbitration is terminated ("YES" results in step 665), step 665 is followed by steps 635, where the arbitration ends, and step 640 where the node contending for access and winning the arbitration, has access to the control channel. For a node that is contending for access to the control channel, step 605 is followed by step 610, where a preamble is generated. A node that is contending for access to the control channel, and that receives a CBF exhibiting a lower state, becomes a write node, and initiates the transmission of its preamble by setting the CBF to a higher state in step 615 The next CBF is received in step 620. Step 620 is followed by step 625, which determines whether the state of the previous CBF was a lower state, while the received CBF is a higher state. If so ("YES" results in step 625), another node has changed the CBF to the higher state, ie, another node has become the writing node. Accordingly, step 625 is followed by step 660, where the present node ceases to contend for access to the control channel, and, as described above, does not change the following values of the CBF, i.e., passes the values of the CBF through the node. A result of "NO" in step 625 indicates that the present node continues to be a "write" node, resulting in the execution of step 630 after step 625. Step 630 determines whether the state of the previous CBF was both the last status of the preamble as the same state as the received CBF. A result of "YES" in step 630 indicates that the node has successfully finished sending its preamble, and therefore has won the arbitration. A result of "YES" in step 630 is followed by step 635, which terminates the arbitration and step 640, wherein the winning node has access to the control channel. A result of "NO" in step 630, indicates that all the preamble bits have not been sent, and step 650 is executed. In step 650, the next state of the CBF produced by the node is determined by the status of the next preamble, and by the rules stipulated above for change the status of the CBF. Step 650 is followed by step 620, where the next CBF state is received. As a further explanation of the arbitration operation, a description of the first three cycles of synchronization of the bus in an arbitration cycle follows. During the first cycle of the busbar available for arbitration, for example, meaning that there has been an absence of control channel activity for the required period of time, the master node sets the Control Bit Field (CBF) in the word Synchronization of the busbar cycle in a lower status signal • 0 '. Any node wishing to access the control channel begins to transmit its coded preamble in the CBF, changing the CBF to the higher state 1, and that node becomes the writing node. The following nodes that are not competing for access to the control channel (called non-competing nodes), take note of the highest status 1 of the received CBF, and pass it to the next node, without changes. Then, non-competing nodes must wait for the next time control channel inactivity times are found before they can compete for the control channel. From this point forward, in this arbitration cycle, non-competing nodes will pass the CBF sent to them to the next node without changes. Any node before the write node will not see the upper state 1 in the CBF during this first bus cycle in the arbitration cycle. The operation of these nodes will be described in more detail below. In the case where two or more nodes are competing for access to the control channel, the first node will begin to transmit its coded preamble, establishing the CBF in the upper state. This is denoted below as follows: CBF (cycle #) = state. In this case, this is cycle 1 of the arbitration cycle, and the value is a superior state signal, represented by a 1, and therefore: CBF (l) = 1. The first node that establishes the CBF in 1, knows that this is the writing node, because it received CBF (l) = 0. All subsequent arbitration nodes will be competing nodes, and will begin to transmit their coded preamble in the same way, passing the CBF (l) = 1 without changes. The CBF value may not change from the upper state until the cycle ends (ie, until it is received by the write node). As described above, all non-competing nodes pass the CBF as received, and no longer compete for access to the control channel during this cycle of the control channel. During the second bus cycle in the arbitration cycle, the master detects that it received the CBF (l) = 1, and establishes CBF (2) = 1 in the next synchronization word of the busbar cycle. There may be a node between the master node and the write node that wants access to the control channel, but which did not observe CBF (l) = 1 in the previous bus cycle. This node is called a late node. Also, it starts transmitting its coded preamble by passing the value CBF (2) = 1. However, it is competing with the previous write node. The value CBF (2) = 1 propagates through the ring until it reaches the write node. The write node can change the state of the CBF (2) to CBF (2) = 0, or continue with CBF (2) = 1, depending on the next state of its coded preamble. If the next state in the coded preamble of the write node is a higher state, then the write node sets CBF (2) = 1. On the other hand, if the next state of the coded preamble is a lower state, then the node of writing sets CBF (2) = 0. Subsequent nodes continue similarly trying to transmit their own coded preambles. The rules stipulated above govern whether a subsequent node can change the state of the CBF (2).

If the write node maintains the status of CBF (2) as a higher state, that is, CBF (2) = 1, then, as stipulated in the previous rules, each succeeding competitor node determines the next state of its coded preamble. . If the next state of its coded preamble is the upper state, then the node passes CBF (2) = 1, and remains connected for access to the control channel. If the next state is the lower state, then that node goes to CBF (2) = 1, but leaves contention for access to the control channel. From this moment forward in the arbitration cycle, this node passes the CBF to the next node without changes. If the write node changes the state of the CBF (2) to a lower state, ie CBF (2) = 0, then the subsequent nodes can assert a higher state 1 on this change by setting CBF (2) = 1. If the next state in the coded preamble of a subsequent node is a higher state 1, then that node transmits CBF (2) = 1. When this occurs, that node inherits the state of the write node. If the next state of the coded preamble of the next node is a lower state, then that node passes CBF (2) = 0, and remains in contention for access to the control channel. In the third bar cycle in the arbitration cycle, the master receives CBF (2) = 0, and establishes CBF (3) = 0, or receives CBF (2) = 1, and establishes CBF (3) = 1. A last node, in a manner similar to that described above for the contending nodes, determines the next state of its coded preamble, and then it can set the CBF (3) = 0, or CBF (3) = 1, or it can be exit the contention for access to the control channel, all in accordance with the rules described above. This happens for all late nodes. At some point, the writing node receives the CBF (3). If the write node had previously set the CBF (2) = 1, then it must receive back the CBF (3) = 1. Then the write node sets the CBF (3) in the next state in its coded preamble, as was done in cycle 2 of the control channel (described above) of the arbitration cycle. If the write node had previously established CBF (2) = 0, and receives CBF (3) = 0, then the write node is still the write node, it is still in contention for access to the control channel, and you can change the value of CBF (3) to the next state of your coded preamble. If the write node had previously established CBF (2) = 0, but received CBF (3) = 1, then it is no longer the write node, and is no longer in contention for access to the control channel. From this point forward in the arbitration cycle, this node passes the received CBF unchanged to the next node. The operation described above continues for the following busbar cycles. Each node that remains in contention for access to the control channel establishes the CBF in the next state in its coded preamble, or leaves contention for access to the busbar. After the preamble has been transmitted, each node that is still in contention, tries to transmit the states of an end-of-field symbol, which, as described above, is of three consecutive upper or lower state signals. The first node that transmits successfully and receives its coded preamble, followed by the end of field symbol, won the arbitration, and can begin to transmit its message in the CBF of the bus cycle cycle synchronization words. To summarize the previous description, at the end of the preamble and the end of field symbol, the node that is designated as the writing node has arbitrated successfully by accessing the node. The state of the write node is inherited by any node that changes the CBF from a lower state to a higher state. The state of the write node is lost when the node of writing changes back a CBF different from the one that placed in the control channel. Five examples of control bit field values follow. Each example is illustrated in a table. Each node is represented by a column in the table. The second row of the table shows the preambles generated randomly for the nodes that contend for access to the control channel. The third row of the table shows the preambles coded according to the rules given above. As described in the above, the first state to code the preambles, is the superior state. The remaining rows show the states of the CBF as it was produced by each node in the following busbar cycles. The fourth row is the zero cycle, and represents the last cycle of inactivity of the control channel before an arbitration cycle is initiated.

EXAMPLE I In Example 1, node A is the master node, node D initiates the arbitration cycle, and node B is a last node competing with node D for access to the control channel. The master node, node A, maintains a lower state 0 in the CBF in the period of time prior to the arbitration cycle, as illustrated in cycle 0, and the first portion of the bus cycle 1. In the cycle of bus 1, node D initiates the arbitration cycle asserting a higher state in the CBF as the first state of its coded preamble. Node E and node A are not competing nodes, and pass this signal to node B in busbar cycle 2. Node B is a last node, and the upper state passes to node C. Node C is also not a competitor node, and passes the superior state back to node D. The node D, when it receives back the CBF (2), in cycle 2, changes it to CBF (2) = 0, representing the next state in its preamble encoded. This is passed to node B in cycle 3 through nodes E and A. Node B receives a 0 in cycle 3, but changes it to a 1, as the next state of its coded preamble. Now node B becomes the writing node. The 1 is passed by node C to node D. Node D transmitted a 0 in cycle 2, but received a 1 in cycle 3. Consequently, node D leaves contention for access to the control channel. All nodes, except node B, now become passive, and pass the received CBF to the next node with no changes. Eventually, node B transmits successfully and receives its coded preamble, followed by an end-of-field symbol, and acquires access to the control channel.

EXAMPLE 2 In Example 2, node D initiates an arbitration cycle by setting CBF (l) = 1 as the first state of its coded preamble, and it is the write node. The node E is a competitor node, and passes the CBF (l) = 1 that it receives from the node D. The nodes A, B and C are non-competing nodes, and pass the received CBF values to the next node without changes. In cycle 2, node D receives CBF (2) = l from node C, and changes it to CBF (2) = 0 as the next state in its coded preamble. Node E receives CBF (2) = 0 in cycle 2. However, the next state in the coded preamble of node E is 1. Therefore, node E establishes CBF (2) = 1, and becomes the writing node. In cycle 2, node D establishes CBF (2) = 0, but in cycle 3, node D receives CBF (3) = 1. Therefore, node D knows that it has lost the arbitrage, and leaves contention for access to the control channel. At this point, all nodes, with the exception of node E, are out of contention for access to the control channel, and pass the received CBF value to the next node unchanged. The node E eventually transmits its complete coded preamble, and the next end-of-field symbol, and acquires access to the control channel.

EXAMPLE 3 In Example 3, node D initiates an arbitration cycle in cycle 1, establishing CBF (l) = 1. Node E is a contending node, and passes CBF (l) = 1 to node A The nodes A, B and C are non-contending nodes, which pass the received CBF values to the next node without changes. In cycle 2, node D receives from CBF (2) = 1. The next state of the preamble coded for node D is 0, so node D establishes CBF (2) = 0. Node E receives CBF (2) = 0.

The next state of the preamble of node E is also 0, so that node E remains in contention for access to the control channel, and sets CBF (2) = 0. In cycle 3, the same thing happens again. In cycle 4, node D receives CBF (4) = 0. The next state of its coded preamble is 1, such that node D establishes CBF (4) = 1. Node E receives CBF (4) ) = 1 from node D. As in cycle 1, then the next state of its preamble is 1, so that node E remains in contention, and sets CBF (4) = 1. In cycle 5, node D receives CBF (5) = 1. -The next state of its preamble is 1, such that node D establishes CBF (5) = 1. Node E receives CBF (5) = 1. However, the next state of its preamble is 0. Therefore, node E leaves contention for access to the control channel, and passes the received CBF to node A unchanged for the remainder of the arbitration cycle. Eventually, node D successfully sends its coded preamble, followed by an end-of-field symbol, and acquires access to the control channel.

EXAMPLE 4 In Example 4, both randomly generated preambles are equal. The node D starts an arbitration cycle in cycle 1, establishing CBF (l) = 1. The node E is a node that- contends, and receives the CBF (l) = 1. It also establishes CBF (l) = 1 The nodes A, B and C are nodes that do not contend, which pass the received CBF to the next node without changes. In cycle 2, node D receives CBF (2) = 1. The next state of its coded preamble is 0, so it sets CBF (2) = 0. Node E receives CBF (2) = 0. The next state of its preamble is 0, so it remains in contention, and sets CBF (2) = 0. Because the coded preambles are identical, this continues until cycle 9. In cycle 10, node D sets CBF (10) = 1 as the first state of the end of field symbol, defined above. In a similar way, as in the first nine cycles, node E is also sending an end-of-field symbol, and sets CBF (10) = 1. This continues until cycle 13. In cycle 13, node D receives returns the last state of the end of field symbol, and acquires access to the control channel. Whether the first bit of the message is a logical '1' (which would be transmitted as a single 0) or a logical '0' (which would be transmitted as two consecutive l 's), the first state placed on the control channel is 0 The node E receives CBF (13) = 0, but had transmitted CBF (12) = 1. Therefore, the contention is exited, and node D acquires access to the control channel.

EXAMPLE 5 Example 5 is similar to Example 4, with the exception that node B is a late node. The preambles of both nodes B and D are identical. The node D starts the cycle of "arbitration by setting CBF (l) = 1 in cycle 1. Nodes A, C and E are non-competing nodes, which pass the received CBF values to the next node without changes. 4, the coded preambles of both nodes B and D are identical, and each remains in contention for access to the control channel through cycle 10. In cycle 10, node D begins to send an end-of-field symbol In cycle 11, node B also starts sending an end of field symbol, again, both nodes remain in contention for access to the control channel until cycle 12. In cycle 13, node D receives CBF ( 13) = 1, which indicates a successful transmission of its coded preamble, and the next end-of-field symbol.Therefore, node B acquires access to the control channel.As with Example 4, node B starts the transmission of your message by setting CBF (13) = 0. Node D receives CBF (13) = 0, and leaves the content ion for access to the control channel.

Claims (17)

1. A data transmission busbar system, which comprises: a plurality of nodes; a ring bus which couples the plurality of nodes together; wherein: the ring bus transmits the successive bus bar cycles, each bus bar cycle containing a plurality of bus bar words, one of which is a bar cycle synchronization word, and the rest of the which are data words, wherein the plurality of data words are assigned to a plurality of data channels.

2. The busbar system of claim 1, wherein: each of the plurality of nodes includes an input connector and an output connector; and the ring bus comprises a plurality of cables, each including a forward data line, and a reverse data line, and a plug at each end of the cable, the respective cables being coupled between the input connector of the cable. a node and the output connector of a previous node in the ring bus, and between the output connector of the first node and the input connector of a successive node in the ring bus.

3. The busbar system of claim 2, wherein: the input and output connectors at each node, each include a forward line terminal, and a reverse line terminal; and each node also includes: an input register and an output register; a detector for determining when a plug is inserted into the input connector and the output connector; and a switch for coupling the reverse line terminal on the output connector with the input register, and the output register with the line terminal forward on the output connector, when the detector detects that a pin is inserted in the connector. the output connector, and no plug is inserted into the input connector, to couple the line terminal forward on the input connector with the input register, and the output register with the line terminal on reverse on the input connector, when the detector detects that a plug is inserted into the input connector, and no pin is inserted into the output connector, and to couple the line terminal forward on the input connector with the recorder input, the output logger with the forward line terminal in the output connector, and the reverse line terminal in the output connector with the line terminal in reverse in the input connector, when the detector detects that a plug is inserted into both the input connector and the output connector.

4. The busbar system of claim 2, which further includes a first node in the busbar system, which has a cable connected only to its output connector, and a last node in the busbar system that has a cable connected only to its input connector.

5. The busbar system of claim 4, wherein the first node in the busbar system is designated as the master node, and performs the initialization of the busbar system. The busbar system of claim 5, wherein: the master node allocates a mutually different identification number to each third node during the initialization of the busbar system, by sending a name command around the ring busbar , having the name command an identification field; where: the master node is assigned an identification number of 1, and transmits the name command that has the identification field set to 1; and each node that receives the name command, increments the identification field, assigns the identification number of the increased identification field, and transmits the name command to the next node with its identification number in the identification field. 7. The busbar system of claim 5, where: each node comprises an input register that contains enough bits to contain at least two words of data, it can direct a word from its input connector to its output connector with one of a delay of one word and a delay of two words, and initially directs a word from its input connector to its output connector with a delay of one word; the master node adjusts the word delay around the ring bus, to be the module of a previously determined number of words, by sending successive ring delay commands through the ring, each node receiving a ring delay command that responds by addressing a word from its input connector to its output connector with two word delays, and removing the ring delay command from the busbar. The busbar system of claim 7, wherein, if there are less than four nodes in the ring, the master node adjusts the word delay around the ring bus to be module 4, and if there are more of three nodes in the ring, the master node adjusts the word delay around the ring bus to be the module 8. 9. The bus bar system of claim 5, wherein: each node comprises a node clock; and the master node performs the synchronization of the word clocks in the plurality of nodes, by transmitting a word synchronization command through the ring bus and up to the plurality of nodes. 10. The busbar system of claim 9, wherein the master node comprises an input register that has at least enough bits to contain two words, and compensates for word delays that are not complete through the bus bar. ring, by detecting which bits in its input register contain the word synchronization command in a word time, and using that location in its input register to receive words from the bus bar. The busbar system of claim 1, which further comprises a control channel, wherein a bit of the control channel is carried in each synchronization word of the busbar cycle. The busbar system of claim 1, wherein each busbar word contains a synchronization bit, and a plurality of data bits. 13. The busbar system of claim 12, wherein the number of bits in the plurality of data bits is eight bits. The busbar system of claim 12, wherein the data words have the synchronization bit set to logical '0', and the command and synchronization words have the synchronization bit set to logical '1'. 15. The busbar system of claim 1, wherein the plurality of busbar words in each busbar cycle is 88 words. 1

6. The busbar system of claim 1, wherein the ring bus transmits a constant number of data channels, and the plurality of data words are divided into successive groups, each group containing a number of data words. equal to the constant number of data channels, and the data words of each group are assigned to a different data channel respectively. 1

7. The busbar system of claim 16, wherein the constant number of data channels is eight data channels.