HK1053393B - Communication system capable of preventing dropout of data block - Google Patents

Description

Communication system capable of preventing loss of data block

The present invention relates to a communication system for transmitting real-time data such as video data and audio data, which employs a communication control bus such as an IEEE-P1394 standard serial bus (hereinafter referred to as a P1394 serial bus).

A communication system is conceivable in which a plurality of electronic devices are connected to each other via a communication control bus such as a P1394 serial bus, and digital information signals and control signals are communicated between these electronic devices.

An example of such a system is shown in figure 3. The system includes electronic devices a, B and C interconnected by a P1394 serial bus. These electronic devices are, for example, a digital VTR (video tape recorder), a tuner, a monitor, etc. The corresponding electronic apparatus includes a circuit having a main function such as a recording/reproducing unit for a digital VTR, a display unit for a monitor, and a circuit for transmitting/receiving signals through a P1394 serial bus.

Data transmission is performed between the electronic devices "a" to "C" each associated with the P1394 serial bus in a predetermined communication cycle. As for the management of the communication cycle, it is such that an electronic device intended for managing the communication system, for example, the electronic device a transmits cycle start data indicating the start time of the communication cycle to other electronic devices via the P1394 bus, so that data transmission in the communication cycle is started.

The time information on the P1394 serial bus is managed by timer registers owned by each of these electronic devices. The timer register of each electronic device counts its own clock to generate time information. The time information is reset synchronously according to a period of every 125 microseconds (see fig. 4). The time information is then corrected based on the time information of the start data of the cycle.

The data format in one communication cycle is classified into two types, i.e., a synchronous type packet such as video data and audio data, and an asynchronous type packet such as a connection control command. The isochronous packet is then transmitted before the asynchronous packet. Fig. 4 shows only sync type packets.

In the communication system adopting this manner, when the communication cycle ideally repeats every 125 microseconds, the time period for which the timer employed in each electronic device is reset is made to coincide with the cycle of the cycle data. However, when the transmission time of the asynchronous type packet is extended, since the next communication cycle start proceeding time is delayed, the time of the cycle start data is delayed compared to the cycle synchronization.

Consider the case: in the above-described communication system, both video data and audio data (which will be referred to as "AV" data hereinafter) output by the digital VTR are transmitted to another video VTR.

Fig. 5 represents such a manner that AV data is transmitted in packets. AV data copied by the digital VTR is first arranged in an array of data blocks having a certain capacity as shown in fig. 5, and then reaches the transmitter circuit, and the processing of the data blocks is performed between the recording/copying unit of the digital VTR and the transmission line using the FIFO (first in first out) principle. The data blocks arriving at the transmitting circuit are code-numbered with serial data block numbers and packetized in units of data blocks, and then the packetized data blocks are sent out to a data bus. Meanwhile, the data packets that have arrived in the period synchronized from the previous period to the current period are packetized in the order of the block numbers from the low number to the high number, and the packetized data are transmitted after the period start data.

In fig. 5, since a data block arrives at the transmission line within an interval of about 50 microseconds, the number of data blocks transmitted by one packet may be equal to 2 or 3 when normal communication is performed.

Referring now to FIG. 8, another specific example of such a communication system is described, which is an AV apparatus equipped with a television set TV, video recorders VTR1, VTR2, and a camera encoder (hereinafter referred to as "CAM"). Thus, a P1394 serial bus capable of carrying mixed digital AV signals and control signals is used to connect CAM to TV, TV to VTR1, VTR1 to VTR 2. These devices all have the capability to forward control signals and digital AV signals over the P1394 serial bus.

Fig. 9 is a diagram for explaining a basic configuration of a VTR corresponding to an example of AV electronic equipment adopting the communication system in fig. 8. The VTR includes the following basic blocks: a deck unit 1, a tuning unit 2, an operation unit 3 serving as a user interface, a display unit 4, and a microcomputer 5 for controlling the overall operation of the VTR, generating packets (to be described later), and storing addresses. The VTR further includes a digital interface (which will be referred to as "digital I/F" hereinafter) for the P1394 serial bus, and a conversion box unit 7 for converting signals among the deck unit 1, the tuner unit 2, and the digital I/F6.

It should be noted that when a TV is used as the AV device, then the monitoring unit and the amplifier unit are used instead of the deck unit 1, without the display unit 4. In the case of CAM, the tuning element 2 is replaced by an image pick-up element.

As shown in fig. 10, in the communication system of fig. 8, data transmission is performed with a predetermined communication period (e.g., 123 microseconds). Thus, both synchronous and asynchronous communication can be achieved. In synchronous communication systems, data signals such as digital AV signals are transmitted at a fixed data rate continuously, whereas in asynchronous communication control signals such as connection control commands are transmitted irregularly if necessary.

A cycle start packet (SP appears at the beginning of a communication cycle, and subsequently, a time interval for transmitting synchronous communication packets is set, and channel numbers 1, 2, 3, … N are attached to packets for synchronous communication, so that a plurality of synchronous communications can be realized.

Now, assume that channel 1 is allocated for communication from (AM to VTR1, then the synchronous communication packet with channel number 1 is transmitted after the cycle start packet CSP, the data bus is monitored by VTR1, and then the synchronous communication packet with channel number 1 is acquired for communication, furthermore, when channel 1 is allocated for communication from VTR2 to TV, communication from CAM to VTR1 and from VTR2 to TV are both performed in parallel.

Then, the time interval from the transmission of the synchronous communication packet of the all-channels to the next cycle start packet CSP is used as asynchronous communication. In fig. 10, packets a and B correspond to asynchronous communication.

In a communication system employing a P1394 serial bus, when respective TV electronic apparatuses are interconnected through the serial bus, node IDs (physical addresses) are automatically assigned in accordance with the connection status. In the case of fig. 8, symbols #0 to #3 correspond to node IDs. The allocation order of the node IDs is explained briefly below in conjunction with fig. 11.

Fig. 11 shows a hierarchy of nodes, in which leaf nodes B and C are connected to a root node at a lower level, and leaf nodes D and E are connected to a branch node C at a lower level. In other words, node A corresponds to the parent node of node B, and node C corresponds to the parent nodes of nodes D and E. First, the order in which this layered structure is determined is described.

When the twisted pair cable of the P1394 serial bus is used to connect nodes a and B, nodes a and C, and nodes C and E, only the node having one input/output port connected to the other node transmits such a message to the node connected to its own node; the inverse node corresponds to the parent node.

In the scenario of fig. 11, the node B transmits such a message: this node B is equivalent to the parent node of port 1 of node a, and node D transmits such a message: this node D corresponds to the parent lattice of port 2 of node C, while node E transmits a message: this node corresponds to the parent node of port 3 of node C.

Thus, when node a confirms that its node has connected to its port 1, it announces to node B through port 1: it corresponds to the child node. In addition, node C is announced by port 2 node D: it behaves as a child node and announces to node E by port 3: it corresponds to a node.

Then, the nodes to which the plurality of input/output ports are connected with other nodes transmit the message of "the inverse node is equivalent to the parent node" to the nodes other than the node to which the message of "they are the parent node" has been transmitted.

In the scenario of fig. 11, node C announces a message "node a is equivalent to a parent node" to port 2, while node a announces such a message to port 1 of node C: node C corresponds to a parent node. At this time, since the respective inverse nodes will announce the message of "they are equivalent to the parent node" to each other between the node a and the node C, the node which has received the message of "the node is equivalent to the parent node" first becomes the parent node.

If the inverse nodes transmit a message that they are parent nodes at the same time, the inverse nodes declare that they are parent nodes after the nodes have entered a waiting time randomly set by the corresponding nodes. Fig. 11 illustrates a case where the node a becomes a parent node.

It should be noted that: in the above description, the nodes B, D, E, whose single input/output port is connected to other nodes, transmit such a message: the inverse node corresponds to the parent node corresponding to the connected node. Further, for example, when the timing at which the node B transmits the message "the node a corresponds to the parent node" is delayed and when the node B has previously transmitted the message "the node a corresponds to the parent node", the node B becomes the routing node.

The order in which the physical addresses are applied to the nodes is now described. In principle, the physical address is applied to the node in such a way that the parent node allows a physical address to be added to the child node. For example, a parent address would allow a physical address to be applied to a child node connected to a lower (smaller) port number.

In FIG. 1, node A allows a physical address to be given to node B after node B is connected to port 1 and node C is connected to port 2 of node A. The node B sends data indicating that the node ED #0 is added to the own node and the node ID #0 has been added to the own node to the bus.

Node a then allows the address to be determined for node C, which allows the address to be applied to node D, which is connected to port 1. Node D adds node ID #1 to its own node.

Node C then allows the physical address to be applied to node E, which is connected to port 2. Node E adds node ID #2 to node E. When node C has finished adding addresses to nodes D and E, node C adds node ED #4 to node C.

It should be noted that a detailed description of the P1394 serial bus relating to assigning the node ID sequence is disclosed in the ieee P1394 serial bus specification (published in 1993, 10, 14).

There are four prior patent applications:

(1) EPC publication No.0614297, EPC publication No,

(2) in the case of the japanese patent application No.5126682,

(3) in the case of the japanese patent application No.5200055,

(4) in the case of the japanese patent application No.6051246,

and corresponding U.S. patent applications are also under examination.

When AV data is transmitted in the manner as in fig. 6, if the cycle start is lost due to noise occurring on the bus and a reset operation of the bus, the data blocks 2 and 3 that should originally be transmitted in the communication cycle that starts to be performed after the cycle start data are lost. This is because the protocol for the P1394 serial bus determines: the data block is sent after the cycle start data has been detected.

Thus, as shown in fig. 7, in order that the data blocks are not lost even when the cycle start data is lost, the data blocks 2 and 3 that should originally be transmitted in the communication cycle starting from the loss of the cycle start data may be transmitted in the communication cycle starting from the next normal cycle start data. However, since the total number of data blocks transmitted as a single packet increases to 5, the operating band (bus occupation time) also increases. If more than two cycle starts are lost consecutively, the total number of data blocks transmitted as a single data packet will increase further, and thus the operating band increases further. As a result, the problem of band inefficient use is caused.

The present invention is intended to solve this problem, and therefore an object of the present invention is to provide a communication system capable of effectively using a frequency band. Further, another object of the present invention is to provide a communication system capable of preventing a data block from being lost and effectively utilizing a frequency band.

In order to solve the above problems, the present invention can determine the maximum number of data blocks transmittable within a predetermined time interval in a communication system for transmitting one or more data blocks arriving within each predetermined time interval as a packet following a communication initiation signal occurring in a time interval adjacent to the time interval in which the one or more data blocks have arrived.

The communication system of the present invention is arranged as follows:

when a communication start signal is lost, data blocks having a number lower than the maximum data block number are transmitted with a packet following the normal communication start signal from among data blocks which have arrived within a period of time determined from the start time of a predetermined time interval at which the normal communication start signal is again obtained after the communication start signal is lost to a predetermined time.

Further, the predetermined time is longer than twice the predetermined time interval. Thus, the communication system of the present invention is arranged such that:

when the number of data blocks which have arrived within a period of time from a start time of a predetermined cycle at which a normal communication signal is acquired again after a communication signal is lost to a predetermined time exceeds the maximum capacity of data blocks which can be transmitted within a predetermined time interval, the data block having the largest number of data blocks among the data blocks which have arrived previously is transmitted.

According to the invention, data blocks having a number lower than the maximum number of data blocks are transmitted as data block packets within a predetermined time interval. Therefore, since the operating band does not exceed the maximum number of data blocks, other data is transmitted through the remaining band, so that the band can be effectively used.

Further, according to the present invention, when a communication start signal is lost, data whose number is less than the maximum number of data numbers is transmitted through a packet after a normal communication start signal from data blocks which have arrived until a predetermined time from the start time of a predetermined time interval at which the normal communication start signal is obtained again after the communication start signal is lost. Thus, it is possible to prevent the data block from being lost even when the communication start signal is lost, while effectively utilizing the frequency band.

Thus, according to the present invention, when the number of data blocks which have arrived in a period of time from the start time of the time interval during which the communication start signal is recovered by the loss of the communication start signal to a predetermined time exceeds the maximum number of data blocks which can be transmitted in a predetermined time interval, the data block having the maximum number of data blocks is transmitted from among the previously arrived data blocks.

As has been described in detail above, according to the present invention, since the maximum number of data blocks that can be transmitted as a packet at a predetermined time is determined, the operating band can be effectively utilized.

Further, according to the present invention, since, when the communication start signal is lost, a data block lower than the maximum data number is transmitted by a packet following the obtained normal communication start signal among data blocks that arrive from the start time of the predetermined time to obtain the normal communication start signal again after the communication start signal is lost to a predetermined time, it is possible to prevent the data block from being lost and to efficiently use the frequency band.

For a better understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings.

Fig. 1 schematically shows a data transmission example of a communication system of an embodiment of the present invention;

fig. 2 schematically shows another example of transmission of blocks in the communication system of the invention after a loss of data from cycle on;

FIG. 3 schematically illustrates a communication system employing a P1394 serial bus;

fig. 4 schematically shows a configuration example of a communication system using a serial bus;

fig. 5 schematically shows the manner in which AV data is packetized to be transmitted in a communication system employing a P1394 serial bus;

fig. 6 schematically illustrates a situation in which a data block is lost when the cycle start data is lost in the communication system of fig. 5;

fig. 7 schematically shows a situation in which a data block is transmitted when the start of period number is lost in the communication system of fig. 5;

FIG. 8 schematically illustrates an example of an AV communication system employing a P1394 serial bus in accordance with an embodiment of the present invention;

fig. 9 is a diagram for explaining an example of a communication cycle employed in the AV communication system of fig. 8;

fig. 10 schematically illustrates an example of a communication cycle employed in the AV communication system of fig. 8; and

fig. 11 is an explanatory diagram for explaining a sequence of assigning the nodes IOS employed in the communication system using the P1394 serial bus.

A communication system according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

Fig. 1 schematically shows an example of transmission of one data block of an embodiment of the present invention.

Note that fig. 1(a) shows a block of data arriving at the transmitter circuit, fig. 1(b) shows a packet transmitted by the transmitter circuit, and fig. 1(c) shows the number of the last transmitted block of data.

In the present invention, the "maximum number of data numbers" and the "maximum delay" concept are introduced to express the relationship between data arriving at the transmission circuit and a data block within one packet transmitted from the transmission circuit.

The maximum number of data blocks corresponds to the maximum number of data blocks transmitted by a single packet. The maximum data block value is set by: which is greater than the maximum number of data blocks arriving at the transmitter circuit in 125 microseconds corresponding to the period sync. In fig. 1, the maximum number is set to 6 and the maximum data block number is 7 because the data blocks arrive at the transmitter circuit within an interval of approximately 24 microseconds.

The maximum delay corresponds to the maximum delay time determined after the data has reached the transmitter circuit until the data block is transmitted. In the case of fig. 1, the maximum delay is equal to 250 microseconds.

As for the data blocks transmitted in one communication cycle, those data blocks which have not been transmitted are combined into one single packet, and the single packet is transmitted in a packet which has been received synchronized from the cycle before the time when the cycle start data was received to the maximum delay. Since the number of the last transmitted data block is stored, it can be confirmed which data blocks are transferred.

In the case of fig. 1, data blocks up to data block "0" are transmitted in communication cycle m-2 and data blocks "1" to "6" are transmitted in communication cycle m-1, data blocks 7 to 11 are transmitted in communication cycle m, and data blocks 12 to 16 are transmitted in communication cycle m + 1.

Fig. 2 schematically illustrates an example of transmission of the present invention when cycle start data is lost. In fig. 2 it can be seen that the interval of data blocks arriving at the transmitter circuit, the maximum number of data blocks, and the maximum delay are the same as in fig. 1. Data blocks up to data block "0" are transmitted in communication period m-2 as in fig. 1, however, since period start data m-1 is lost in the present figure, data blocks 1 to 6 cannot be transmitted in communication period m-1.

These data blocks 1-6 are then transmitted from the communication cycle m starting with the cycle start data m. Since 7 data blocks can be transmitted as the largest single data packet in this implementation, data 1-6 and data block 7 are combined with each other to form one data packet to be transmitted. Similarly, during the next communication cycle m +1, data 8-14 is transmitted. Then, among the data blocks from the cycle synchronization immediately before the cycle start data is received until the maximum delay period arrives, those data blocks that have not been transmitted are combined with each other into one single data packet.

It should be appreciated that although in the above embodiments the maximum delay is set to be twice the sync signal time interval, the maximum delay may be longer than the sync period if it is not necessary to prevent data blocks from being lost when the period start data is lost. So that the maximum delay should be chosen to be three times larger than the synchronization period, if even two consecutive periods of missing start data do not result in missing data block data.

Further, it should be noted that although in the above-described embodiment, the maximum block number 7 is set to be larger than 1 than the maximum data block number 6 reached in one synchronization period, it may be set to be larger than 2.

In addition, in the above-described embodiment, the maximum value of the data block arriving at the transmitter circuit in one synchronization period is set to 6, but the present invention is also applicable to a system in which the maximum value of the data block arriving at the transmitter circuit in one synchronization period is greater than or equal to 1.

Claims (2)

1. A communication apparatus for transmitting a plurality of data blocks in a predetermined communication cycle, each of the data blocks having a predetermined size, the communication apparatus comprising:

a packet generator for generating a packet by numbering the plurality of data blocks and combining the plurality of data blocks that are not output into a packet;

output means for outputting, after receiving a communication cycle start signal, a packet combined from cycle synchronization until maximum delay before a time when the communication cycle start signal is received.

2. A communication device according to claim 1, characterized in that it is arranged to perform said steps

The maximum delay is twice the predetermined communication period.