Search Results for "fpga"
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Showing 3 open source projects for "fpga"
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MongoDB Atlas runs apps anywhereMongoDB Atlas gives you the freedom to build and run modern applications anywhere—across AWS, Azure, and Google Cloud. With global availability in over 115 regions, Atlas lets you deploy close to your users, meet compliance needs, and scale with confidence across any geography.
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The top-rated AI recruiting platform for faster, smarter hiring.Humanly is an AI-first recruiting platform that helps talent teams hire in days, not months—without adding headcount. Our intuitive CRM pairs with powerful agentic AI to engage and screen every candidate instantly, surfacing top talent fast. Built on insights from over 4 million candidate interactions, Humanly delivers speed, structure, and consistency at scale—engaging 100% of interested candidates and driving pipeline growth through targeted outreach and smart re-engagement. We integrate seamlessly with all major ATSs to reduce manual work, improve data flow, and enhance recruiter efficiency and candidate experience. Independent audits ensure our AI remains fair and bias-free, so you can hire confidently.
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Chipyard
An Agile RISC-V SoC Design Framework with in-order cores
Chipyard is a framework and generator for constructing custom RISC‑V SoC hardware. Built at UC Berkeley, it leverages Chisel/FIRRTL to generate full-stack systems—from CPU cores to peripherals—and includes simulators, FPGA deployment tools, and integration with Rocket Chip and other RISC‑V ecosystems. -
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Rocket Chip
Rocket Chip Generator
Rocket Chip is a parameterized RISC-V SoC generator written in Chisel that produces synthesizable RTL for a wide range of cores and configurations. At its heart is the Rocket core, a simple, in-order, five-stage RISC-V implementation, but the generator composes much more: coherent caches, MMUs, interrupt controllers, and buses via the TileLink interconnect. A diplomacy framework (LazyModules) lets designers wire components with negotiated parameters, enabling reuse and rapid exploration of... -
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AVRILOS
Simple AVR OS
...System is based on a super-loop architecture with check and skip (no-wait) flag event driver system. Supports: UART, SysTick Timer, ADC, SPI, EEPROM, PWM. Also supports: Xilinx FPGA configuration, FPGA SSI interface, smart card reader etc. Tested partially (different modules in each case) on ATMega163/16/32/323/8. Awards CodeProject 2010, Third Prize, Hardware and Device Programming Check the Wiki Page for more details.
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