Rocket Chip is a parameterized RISC-V SoC generator written in Chisel that produces synthesizable RTL for a wide range of cores and configurations. At its heart is the Rocket core, a simple, in-order, five-stage RISC-V implementation, but the generator composes much more: coherent caches, MMUs, interrupt controllers, and buses via the TileLink interconnect. A diplomacy framework (LazyModules) lets designers wire components with negotiated parameters, enabling reuse and rapid exploration of different cache sizes, port counts, and memory hierarchies. The generator supports custom accelerators through the RoCC interface, allowing domain-specific compute units to be plugged into the pipeline with shared cache and memory semantics. Tooling integrates with FIRRTL, Verilator, and commercial EDA flows, and the ecosystem around Rocket Chip (e.g., Chipyard) adds harnesses, peripherals, and verification infrastructure.
Features
- SoC generator using parameterizable RISC-V cores (Rocket in-order, optionally BOOM out-of-order etc)
- Support for configurable cache hierarchies, memory subsystems, tiles, coherent interconnects etc
- Simulations via Verilator, support for unit-level and cycle-accurate simulations etc
- Capability to target FPGA for prototyping boards as well as producing RTL for ASIC flows
- Use of modern toolchains / build tools: Chisel, Scala, Nix for build environment, integration with IDEs like IntelliJ/VSCode etc
- Parameterization allows customizing everything like number of cores, accelerators, tile layout, clock domain etc to match different requirements (power, performance, area)
Project Samples
