Search Results for "fpga"

Chipyard is a framework and generator for constructing custom RISC‑V SoC hardware. Built at UC Berkeley, it leverages Chisel/FIRRTL to generate full-stack systems—from CPU cores to peripherals—and includes simulators, FPGA deployment tools, and integration with Rocket Chip and other RISC‑V ecosystems.

...The compiler lowers DSLX into a rich intermediate representation, applies aggressive optimization and scheduling passes, and can either JIT the design for software simulation or emit Verilog for FPGA/ASIC flows. A key idea is “software-style” iteration: fast, deterministic simulation via the JIT encourages test-driven development and property checking before committing to RTL. XLS also provides tooling for pipelining, state insertion, and formal equivalence checks between different stages, giving developers confidence as designs evolve. ...

ALCHA aims to reduce FPGA project develop time by means of automation and abstraction, but without loosing the low-level control that HDLs, such as Verilog, provides. It will support an object oriented programming model, abstract data and signal types, and compile-time scripting.

Rocket Chip is a parameterized RISC-V SoC generator written in Chisel that produces synthesizable RTL for a wide range of cores and configurations. At its heart is the Rocket core, a simple, in-order, five-stage RISC-V implementation, but the generator composes much more: coherent caches, MMUs, interrupt controllers, and buses via the TileLink interconnect. A diplomacy framework (LazyModules) lets designers wire components with negotiated parameters, enabling reuse and rapid exploration of...

Software and HDL code for Elphel reconfigurable network cameras

...In addition to a strong core, WFCPK will also include modules emulating various processors (e.g., the MOS 6502 and the Zilog Z80) as well as the Video-Audio Interface (a custom VGA-compatible display and audio controller). The VAI is designed to fit within an FPGA to be integrated into real designs. This library is licensed under the GPLv3 but also includes the classpath exception so that proprietary software can be linked against it required.

Tools for FPGA development and IP cores. This project provides tools, cores and documentation to develope FPGA applications. The project focuses on VHDL.

The Sercos SoftMaster is intended for implementing a software-based Sercos Industrial Ethernet master on industrial automation controllers. It can be used with controllers that do not provide a dedicated Sercos III master hardware like the Sercos master IP core running on an FPGA. The SoftMaster may be used with a standard Ethernet hardware such as a standard PCI / PCI express Ethernet controller in order to implement a Sercos III master interface. The Sercos Softmaster Core is entirely programmed in plain C and independent of operating systems and hardware platforms.

An API for manipulating EDIF netlists in Java. We use this API to analyze netlists as a part of our FPGA reliability project. We intend to keep the API as general as possible to support other netlist analysis and manipulation activities. This material is based upon work supported by the National Science Foundation under Grant No. 0801876. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.

The design of an open platform devoted to allow students perform distance practices with a real FPGA device involves both hardware and software components.

...We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic circuits have been designed and captured and overcame many of the difficulties associated with the use of schematic editing tools. We believe the use of an HDL is also the way of the future when it comes to PCB design. The PHDL compiler automatically supports the output of PADS and Eagle netlists, and through extending a simple java class, users can generate a netlist in practically any format required by their choice of a layout tool.

ztex is a Firmware Kit with a corresponding Driver API for EZ-USB based hardware. The Firmware is written in C and assembled using a powerful macro processor. The Driver API allows the development of platform-independent device drivers.

MerakoGPS is a set of software for Merako-series board aiming at GPS receiver development. MerakoGPS runs on a flexible Merako-series hardware board which uses a CycloneIII FPGA to accomplish the correlator function. see http://www.hyrising.com.

Writing Testbenches for FPGA/ASIC design is always a very fastidious and boring task. This project helps any FPGA/ASIC designer by providing a full RTL test environment with C support.

OpenVGA is an free and open FPGA-based implementation of a VGA compatible graphics adapter, and utilising low-cost hardware. The project includes the PCB schematic and artwork, Verilog HDL, firmware assembly code, and driver source code.

UTBlazer is a multiprocessor platform simulator developed in Java based on the Xilinx MicroBlaze processor and FPGA design platform. This system simulator is a back-annotated cycle-accurate functional emulator in fact.

A MIF(Memory Initial File) joiner for FPGA/IC design engineer.