WO2025177853A1 - Heat treatment device and heat treatment method - Google Patents

Abstract

Some or all of a plurality of halogen lamps are connected in parallel to a power regulator. The power regulator controls power supply to the plurality of halogen lamps in accordance with an instruction value. A detection instruction value is given to the power regulator during a period from when a preceding processed semiconductor wafer is carried out of a chamber till when a subsequent unprocessed semiconductor wafer is carried into the chamber. The detection instruction value is a value larger than 50% of the maximum power that can be input to all the parallels connected to the power regulator. Power actually output by the power regulator is measured. If the measured output power is less than the detection instruction value, it is determined that a failure has occurred in any of the plurality of halogen lamps, and an alarm is issued.

Description

Heat treatment apparatus and heat treatment method

The present invention relates to a heat treatment apparatus that heats a substrate by irradiating the substrate with light. Substrates to be treated include, for example, semiconductor wafers, substrates for liquid crystal displays, substrates for flat panel displays (FPDs), substrates for optical disks, substrates for magnetic disks, and substrates for solar cells.

Conventionally, light irradiation-type heat treatment equipment (known as lamp annealing equipment) has been used to heat substrates such as semiconductor wafers by irradiating them with light from multiple lamps. In heat treatment using light irradiation, uniformity of the temperature distribution within the wafer surface during heating is important to improving the yield of semiconductor devices. If there are any areas within the semiconductor wafer surface that are higher or lower than the target value during heating, those areas will be processed poorly, resulting in a decrease in yield.

Light sources capable of localized irradiation, such as point light lamps, are effective for finely adjusting the temperature distribution within the wafer surface, but to irradiate the entire surface of a φ300mm semiconductor wafer, for example, a large number of point light lamps are required. To precisely control the temperature distribution within the wafer surface, it would be ideal to individually control the input power to each of the many point light lamps, but this would require a power regulator for each lamp, which is not realistic from the perspective of increasing costs and the footprint. For this reason, a large number of point light lamps are generally divided into several groups, and the multiple point light lamps in one group are controlled by a single power regulator.

One of the essential functions of a lamp annealing device equipped with multiple lamps is the ability to detect lamp breakage. If even one of the multiple point light source lamps is broken, the temperature distribution across the surface of the semiconductor wafer will decrease, which could result in defectively processed wafers, so open circuit detection is important. If one lamp is controlled by one power regulator, open circuit detection is easy, but even in cases where multiple point light source lamps are connected to one power regulator as mentioned above, open circuit detection must be reliable.

Patent Document 1 discloses a technique for detecting broken wires in multiple lamps connected in parallel. When multiple lamps are connected in series, a break in one of the lamps causes no current to flow, making it relatively easy to detect a break. The technology disclosed in Patent Document 1 involves providing one current detector for multiple lamps connected in parallel, and detecting a break by utilizing the fact that when a break occurs in one of the lamps, the current value detected by the current detector is lower than when there is no break.

Japanese Patent Application Laid-Open No. 2000-223434

However, the technology disclosed in Patent Document 1 requires the installation of a current detector solely for the purpose of detecting disconnections, raising concerns about an increase in the power supply footprint. Furthermore, the technology disclosed in Patent Document 1 detects a drop in current value by comparing the current values flowing through the two heating means, making detection difficult through simple comparison when series and parallel connections are mixed. Furthermore, the technology disclosed in Patent Document 1 detects disconnections while semiconductor wafers are being processed, meaning that if a disconnection is detected, the semiconductor wafer being processed will be defective.

The present invention was made in consideration of the above-mentioned problems, and aims to provide a heat treatment apparatus and heat treatment method that can reliably detect light source failures without increasing the footprint or cost.

In order to solve the above problem, a first aspect of the present invention is a heat treatment apparatus that heats a substrate by irradiating the substrate with light, the heat treatment apparatus comprising: a chamber that accommodates the substrate; a light irradiation unit that has multiple light sources and irradiates the substrate accommodated in the chamber with light; a power regulator that supplies power to the multiple light sources according to an instruction value; and a fault detection unit that detects a fault in any of the multiple light sources, wherein some or all of the multiple light sources are connected in parallel to the power regulator, and the number of parallel connections of the multiple light sources connected to the power regulator is N; and when an instruction value greater than the maximum power that can be input to (N-1) parallel connections is given to the power regulator, the fault detection unit determines that a fault has occurred in any of the multiple light sources if the output power is less than the instruction value.

In a second aspect, in the heat treatment apparatus according to the first aspect, the number of parallel connections of the plurality of light sources connected to the power regulator is two, and when an instruction value greater than 50% of the maximum power that can be input to all parallel connections is given to the power regulator, the failure detection unit determines that a failure has occurred in one of the plurality of light sources if the output power is less than the instruction value.

In a third aspect, in the heat treatment apparatus according to the first or second aspect, the failure detection unit provides the instruction value to the power regulator between the time when the heat treatment on the preceding substrate is completed and the preceding substrate is unloaded from the chamber and the time when the subsequent substrate is loaded into the chamber.

In a fourth aspect, in the heat treatment device according to any one of the first to third aspects, the power regulator adjusts the power to the multiple light sources by thyristor phase control.

In a fifth aspect, in the heat treatment device according to any one of the first to fourth aspects, the plurality of light sources is one selected from the group consisting of a halogen lamp, a light-emitting diode, a laser diode, and a vertical-cavity surface-emitting laser.

A sixth aspect is a heat treatment method for heating a substrate by irradiating the substrate with light, the method comprising: an irradiation step of irradiating light from multiple light sources onto a substrate accommodated in a chamber; and a fault detection step of detecting a fault in any of the multiple light sources, wherein some or all of the multiple light sources are connected in parallel to a power regulator that supplies power to the multiple light sources according to an instruction value; the number of parallel connections of the multiple light sources connected to the power regulator is N; and in the fault detection step, when an instruction value greater than the maximum power that can be input to (N-1) parallel connections is given to the power regulator, if the output power is less than the instruction value, it is determined that a fault has occurred in any of the multiple light sources.

In a seventh aspect, in the heat treatment method according to the sixth aspect, the number of parallel connections of the plurality of light sources connected to the power regulator is two, and in the fault detection process, when an instruction value greater than 50% of the maximum power that can be input to all parallel connections is given to the power regulator, if the output power is less than the instruction value, it is determined that a fault has occurred in one of the plurality of light sources.

Furthermore, in an eighth aspect, in the heat treatment method according to the sixth or seventh aspect, the failure detection step is performed between the time when the heat treatment on the preceding substrate is completed and the preceding substrate is unloaded from the chamber, and the time when the subsequent substrate is loaded into the chamber.

Furthermore, in a ninth aspect, in the heat treatment method according to any one of the sixth to eighth aspects, the power regulator adjusts the power to the multiple light sources by thyristor phase control.

Furthermore, a tenth aspect is a heat treatment method according to any one of the sixth to ninth aspects, wherein the plurality of light sources is one selected from the group consisting of a halogen lamp, a light-emitting diode, a laser diode, and a vertical-cavity surface-emitting laser.

In the heat treatment device according to the first to fifth aspects, when the number of parallel light sources connected to the power regulator is N and an instruction value greater than the maximum power that can be input to (N-1) parallel light sources is given to the power regulator, if the output power is less than the instruction value, it is determined that a fault has occurred in one of the multiple light sources. Therefore, the power regulator is an existing essential element, and light source faults can be reliably detected without increasing the footprint or cost.

In particular, with the heat treatment apparatus according to the third aspect, an instruction value is given to the power regulator between the time when the heating process for the preceding substrate is completed and the preceding substrate is unloaded from the chamber and the time when the subsequent substrate is loaded into the chamber. This means that fault detection is performed when no substrate is present in the chamber, and even when a fault is detected, the number of substrates that are not properly processed can be minimized.

In the heat treatment methods according to the sixth to tenth aspects, when the number of parallel light sources connected to the power regulator is N and an instruction value greater than the maximum power that can be input to (N-1) parallel light sources is given to the power regulator, if the output power is less than the instruction value, it is determined that a fault has occurred in one of the multiple light sources. Therefore, the power regulator is an existing essential element, and light source faults can be reliably detected without increasing the footprint or cost.

In particular, according to the heat treatment method of the eighth aspect, the fault detection process is performed after the preceding substrate has been heat treated and removed from the chamber, but before the subsequent substrate is loaded into the chamber. This means that fault detection is performed without any substrates being present in the chamber, and even when a fault is detected, the number of substrates that are processed improperly can be minimized.

FIG. 1 is a vertical cross-sectional view showing the configuration of a heat treatment apparatus according to the present invention. FIG. 2 is a perspective view showing the overall appearance of the holding portion. FIG. 3 is a plan view of the susceptor. FIG. 4 is a cross-sectional view of the susceptor. FIG. 5 is a plan view of the transfer mechanism. FIG. 6 is a side view of the transfer mechanism. FIG. 7 is a diagram showing a circuit in which a plurality of halogen lamps are connected in series to a power regulator. FIG. 8 is a diagram showing a circuit in which a plurality of halogen lamps are connected to a power regulator in a mixture of series and parallel connections. FIG. 9 is a block diagram showing the configuration of the control unit. FIG. 10 is a flowchart showing the procedure of the processing operation in the heat treatment apparatus of FIG. FIG. 11 is a flowchart showing the procedure for detecting a failure in a halogen lamp. FIG. 12 is a diagram showing a schematic diagram of the difference in output power depending on whether or not the halogen lamp is broken.

Embodiments of the present invention will be described in detail below with reference to the drawings. In the following, expressions indicating relative or absolute positional relationships (e.g., "in one direction," "along one direction," "parallel," "orthogonal," "center," "concentric," "coaxial," etc.) not only strictly indicate that positional relationship, but also indicate a state where there is a relative displacement in terms of angle or distance within a range where tolerances or equivalent functionality are obtained, unless otherwise specified. Furthermore, expressions indicating an equal state (e.g., "identical," "equal," "homogeneous," etc.) not only indicate a state where there is strict quantitative equivalence, but also indicate a state where there are differences where tolerances or equivalent functionality are obtained, unless otherwise specified. Furthermore, expressions indicating shape (e.g., "circular," "square," "cylindrical," etc.) not only indicate a strict geometrical shape, but also indicate a shape within a range where equivalent functionality is obtained, and may, for example, have irregularities or chamfers. Furthermore, expressions such as "comprise," "include," "have," "include," and "have" regarding components are not exclusive expressions that exclude the presence of other components. Furthermore, the expression "at least one of A, B, and C" includes "A only," "B only," "C only," "any two of A, B, and C," and "all of A, B, and C."

FIG. 1 is a vertical cross-sectional view showing the configuration of a heat treatment apparatus 1 according to the present invention. The heat treatment apparatus 1 in FIG. 1 is a flash lamp annealing apparatus that heats a disk-shaped semiconductor wafer W as a substrate by irradiating the semiconductor wafer W with flash light. The size of the semiconductor wafer W to be treated is not particularly limited, but may be, for example, φ300 mm or φ450 mm. Note that in FIG. 1 and the subsequent figures, the dimensions and number of various parts are exaggerated or simplified as necessary for ease of understanding.

The heat treatment apparatus 1 comprises a chamber 6 that houses a semiconductor wafer W, a flash heating unit 5 that houses multiple flash lamps FL, and an auxiliary heating unit 4 that houses multiple halogen lamps HL. The flash heating unit 5 is provided above the chamber 6, and the auxiliary heating unit 4 is provided below it. The heat treatment apparatus 1 also comprises, inside the chamber 6, a holding unit 7 that holds the semiconductor wafer W in a horizontal position, and a transfer mechanism 10 that transfers the semiconductor wafer W between the holding unit 7 and the outside of the apparatus. The heat treatment apparatus 1 also comprises a control unit 3 that controls the operating mechanisms provided in the auxiliary heating unit 4, flash heating unit 5, and chamber 6 to perform heat treatment on the semiconductor wafer W.

The chamber 6 is constructed by attaching quartz chamber windows to the top and bottom of a cylindrical chamber side portion 61. The chamber side portion 61 has a roughly cylindrical shape with openings at the top and bottom, with an upper chamber window 63 attached and closed at the upper opening, and a lower chamber window 64 attached and closed at the lower opening. The upper chamber window 63, which forms the ceiling of the chamber 6, is a disc-shaped member made of quartz, and functions as a quartz window that transmits flash light emitted from the flash heating unit 5 into the chamber 6. The lower chamber window 64, which forms the floor of the chamber 6, is also a disc-shaped member made of quartz, and functions as a quartz window that transmits light from the auxiliary heating unit 4 into the chamber 6.

Furthermore, a reflective ring 68 is attached to the upper part of the inner wall surface of the chamber side 61, and a reflective ring 69 is attached to the lower part. Both reflective rings 68, 69 are formed in an annular shape. The upper reflective ring 68 is attached by fitting it into the chamber side 61 from the top side. On the other hand, the lower reflective ring 69 is attached by fitting it into the chamber side 61 from the bottom side and fastening it with screws (not shown). In other words, both reflective rings 68, 69 are detachably attached to the chamber side 61. The internal space of chamber 6, i.e., the space surrounded by the upper chamber window 63, lower chamber window 64, chamber side 61, and reflective rings 68, 69, is defined as the heat treatment space 65.

By attaching the reflective rings 68, 69 to the chamber side 61, a recess 62 is formed on the inner wall surface of the chamber 6. That is, the recess 62 is formed by the central portion of the inner wall surface of the chamber side 61 where the reflective rings 68, 69 are not attached, the lower end surface of the reflective ring 68, and the upper end surface of the reflective ring 69. The recess 62 is formed in an annular shape along the horizontal direction on the inner wall surface of the chamber 6, and surrounds the holder 7 that holds the semiconductor wafer W. The chamber side 61 and the reflective rings 68, 69 are made of a metal material (e.g., stainless steel) that has excellent strength and heat resistance.

Furthermore, a transfer opening (furnace port) 66 is formed in the chamber side portion 61, through which semiconductor wafers W are loaded and unloaded into and from the chamber 6. The transfer opening 66 can be opened and closed by a gate valve 185. The transfer opening 66 is connected to the outer peripheral surface of the recess 62. Therefore, when the gate valve 185 opens the transfer opening 66, semiconductor wafers W can be loaded into and unloaded from the heat treatment space 65 through the transfer opening 66 and the recess 62. Furthermore, when the gate valve 185 closes the transfer opening 66, the heat treatment space 65 within the chamber 6 becomes an airtight space.

Furthermore, a through-hole 61a is drilled in the chamber side 61. A radiation thermometer 20 is attached to the portion of the outer wall surface of the chamber side 61 where the through-hole 61a is provided. The through-hole 61a is a cylindrical hole for guiding infrared light emitted from the underside of a semiconductor wafer W held on a susceptor 74 (described below) to the radiation thermometer 20. The through-hole 61a is provided at an angle relative to the horizontal direction so that its axis in the penetration direction intersects with the main surface of the semiconductor wafer W held on the susceptor 74. Therefore, the radiation thermometer 20 is provided diagonally below the susceptor 74. A transparent window 21 made of barium fluoride material that transmits infrared light in the wavelength range that can be measured by the radiation thermometer 20 is attached to the end of the through-hole 61a facing the heat treatment space 65.

Furthermore, gas supply holes 81 are formed in the upper part of the inner wall of the chamber 6 to supply processing gas to the heat treatment space 65. The gas supply holes 81 are formed at a position above the recess 62 and may be provided in the reflecting ring 68. The gas supply holes 81 are connected to a gas supply pipe 83 via a buffer space 82 formed in an annular shape inside the side wall of the chamber 6. The gas supply pipe 83 is connected to a processing gas supply source 85. A valve 84 is inserted in the gas supply pipe 83. When the valve 84 is opened, processing gas is supplied from the processing gas supply source 85 to the buffer space 82. The processing gas that has flowed into the buffer space 82 spreads within the buffer space 82, which has a lower fluid resistance than the gas supply holes 81, and is then supplied from the gas supply holes 81 into the heat treatment space 65. The processing gas may be, for example, an inert gas such as nitrogen (N ₂ ), or a reactive gas such as hydrogen (H ₂ ) or ammonia (NH ₃ ), or a mixed gas of these (nitrogen gas in this embodiment).

Meanwhile, a gas exhaust hole 86 is formed in the lower part of the inner wall of the chamber 6 to exhaust gas from the heat treatment space 65. The gas exhaust hole 86 is formed below the recess 62 and may be provided in the reflecting ring 69. The gas exhaust hole 86 is connected to a gas exhaust pipe 88 via a buffer space 87 formed in an annular shape inside the side wall of the chamber 6. The gas exhaust pipe 88 is connected to an exhaust unit 190. A valve 89 is inserted in the gas exhaust pipe 88. When the valve 89 is opened, gas from the heat treatment space 65 is exhausted from the gas exhaust hole 86 through the buffer space 87 to the gas exhaust pipe 88. The gas supply hole 81 and the gas exhaust hole 86 may be provided in multiple numbers around the circumference of the chamber 6, or may be slit-shaped. The process gas supply source 85 and the exhaust unit 190 may be mechanisms provided in the heat treatment apparatus 1 or may be utilities of the factory where the heat treatment apparatus 1 is installed.

Figure 2 is a perspective view showing the overall appearance of the holding unit 7. The holding unit 7 is composed of a base ring 71, a connecting unit 72, and a susceptor 74. The base ring 71, the connecting unit 72, and the susceptor 74 are all made of quartz. In other words, the entire holding unit 7 is made of quartz.

The base ring 71 is an arc-shaped quartz member with a portion missing from the annular shape. This missing portion is provided to prevent interference between the base ring 71 and the transfer arm 11 of the transfer mechanism 10, which will be described later. The base ring 71 is placed on the bottom surface of the recess 62, and is supported by the wall surface of the chamber 6 (see Figure 1). A number of connecting portions 72 (four in this embodiment) are erected on the top surface of the base ring 71 along the circumferential direction of the annular shape. The connecting portions 72 are also made of quartz, and are fixed to the base ring 71 by welding.

The susceptor 74 is supported by four connecting portions 72 provided on the base ring 71. Figure 3 is a plan view of the susceptor 74. Figure 4 is a cross-sectional view of the susceptor 74. The susceptor 74 comprises a holding plate 75, a guide ring 76, and a plurality of substrate support pins 77. The holding plate 75 is a substantially circular, flat member made of quartz. The diameter of the holding plate 75 is larger than the diameter of the semiconductor wafer W. In other words, the holding plate 75 has a larger planar size than the semiconductor wafer W.

A guide ring 76 is installed around the periphery of the upper surface of the holding plate 75. The guide ring 76 is an annular member with an inner diameter larger than the diameter of the semiconductor wafer W. For example, if the diameter of the semiconductor wafer W is φ300 mm, the inner diameter of the guide ring 76 is φ320 mm. The inner circumference of the guide ring 76 has a tapered surface that widens upward from the holding plate 75. The guide ring 76 is made of quartz, the same as the holding plate 75. The guide ring 76 may be welded to the upper surface of the holding plate 75, or may be fixed to the holding plate 75 with a separately machined pin or the like. Alternatively, the holding plate 75 and guide ring 76 may be machined as a single integrated member.

The area of the upper surface of the holding plate 75 that is inside the guide ring 76 is a flat holding surface 75a that holds the semiconductor wafer W. A plurality of substrate support pins 77 are erected on the holding surface 75a of the holding plate 75. In this embodiment, a total of 12 substrate support pins 77 are erected every 30° along a circumference concentric with the outer circumferential circle of the holding surface 75a (the inner circumferential circle of the guide ring 76). The diameter of the circle on which the 12 substrate support pins 77 are arranged (the distance between opposing substrate support pins 77) is smaller than the diameter of the semiconductor wafer W. If the diameter of the semiconductor wafer W is 300 mm, the diameter is 270 mm to 280 mm (270 mm in this embodiment). Each substrate support pin 77 is made of quartz. The plurality of substrate support pins 77 may be attached to the upper surface of the holding plate 75 by welding, or may be machined integrally with the holding plate 75.

Returning to Figure 2, the four connecting portions 72 erected on the base ring 71 are fixed to the peripheral edge of the holding plate 75 of the susceptor 74 by welding. In other words, the susceptor 74 and base ring 71 are fixedly connected by the connecting portions 72. The base ring 71 of such a holding portion 7 is supported on the wall surface of the chamber 6, thereby mounting the holding portion 7 to the chamber 6. When the holding portion 7 is mounted to the chamber 6, the holding plate 75 of the susceptor 74 is in a horizontal position (a position in which the normal line coincides with the vertical direction). In other words, the holding surface 75a of the holding plate 75 is a horizontal plane.

The semiconductor wafer W loaded into the chamber 6 is placed and held in a horizontal position on the susceptor 74 of the holder 7 attached to the chamber 6. At this time, the semiconductor wafer W is supported by 12 substrate support pins 77 erected on the holding plate 75 and held on the susceptor 74. More precisely, the upper ends of the 12 substrate support pins 77 contact the underside of the semiconductor wafer W to support the semiconductor wafer W. Because the heights of the 12 substrate support pins 77 (the distance from the upper ends of the substrate support pins 77 to the holding surface 75a of the holding plate 75) are uniform, the semiconductor wafer W can be supported in a horizontal position by the 12 substrate support pins 77.

Furthermore, the semiconductor wafer W is supported by a plurality of substrate support pins 77 at a predetermined distance from the holding surface 75a of the holding plate 75. The thickness of the guide ring 76 is greater than the height of the substrate support pins 77. Therefore, the guide ring 76 prevents horizontal displacement of the semiconductor wafer W supported by the plurality of substrate support pins 77.

Also, as shown in Figures 2 and 3, an opening 78 is formed in the holding plate 75 of the susceptor 74, penetrating vertically. The opening 78 is provided so that the radiation thermometer 20 can receive radiation (infrared light) emitted from the underside of the semiconductor wafer W. That is, the radiation thermometer 20 receives light emitted from the underside of the semiconductor wafer W through the opening 78 and a transparent window 21 attached to the through-hole 61a of the chamber side 61, and measures the temperature of the semiconductor wafer W. Furthermore, the holding plate 75 of the susceptor 74 is formed with four through-holes 79 through which lift pins 12 of the transfer mechanism 10, described below, pass to transfer the semiconductor wafer W.

Figure 5 is a plan view of the transfer mechanism 10. Figure 6 is a side view of the transfer mechanism 10. The transfer mechanism 10 has two transfer arms 11. The transfer arms 11 are arc-shaped so as to fit roughly along the annular recess 62. Two lift pins 12 are erected on each transfer arm 11. The transfer arms 11 and the lift pins 12 are made of quartz. Each transfer arm 11 is rotatable by a horizontal movement mechanism 13. The horizontal movement mechanism 13 moves the pair of transfer arms 11 horizontally between a transfer operation position (solid line position in Figure 5) where the semiconductor wafer W is transferred to the holder 7, and a retracted position (double-dashed line position in Figure 5) where the pair of transfer arms 11 do not overlap the semiconductor wafer W held by the holder 7 in a planar view. The horizontal movement mechanism 13 may be one that rotates each transfer arm 11 using an individual motor, or one that uses a link mechanism to rotate a pair of transfer arms 11 in unison using a single motor.

Furthermore, the pair of transfer arms 11 are raised and lowered together with the horizontal movement mechanism 13 by the lifting mechanism 14. When the lifting mechanism 14 raises the pair of transfer arms 11 to the transfer operation position, a total of four lift pins 12 pass through the through holes 79 (see Figures 2 and 3) drilled in the susceptor 74, and the upper ends of the lift pins 12 protrude from the upper surface of the susceptor 74. Meanwhile, when the lifting mechanism 14 lowers the pair of transfer arms 11 to the transfer operation position and removes the lift pins 12 from the through holes 79, and the horizontal movement mechanism 13 moves the pair of transfer arms 11 apart, each transfer arm 11 moves to a retracted position. The retracted position of the pair of transfer arms 11 is directly above the base ring 71 of the holder 7. Because the base ring 71 is placed on the bottom surface of the recess 62, the retracted position of the transfer arms 11 is inside the recess 62. In addition, an exhaust mechanism (not shown) is also provided near the location where the drive unit of the transfer mechanism 10 (horizontal movement mechanism 13 and lifting mechanism 14) is provided, and is configured to exhaust the atmosphere around the drive unit of the transfer mechanism 10 to the outside of the chamber 6.

Returning to Figure 1, the flash heating unit 5, located above the chamber 6, is configured with a light source consisting of multiple (30 in this embodiment) xenon flash lamps FL inside a housing 51, and a reflector 52 arranged to cover the light source from above. In addition, a lamp light emission window 53 is attached to the bottom of the housing 51 of the flash heating unit 5. The lamp light emission window 53, which forms the floor of the flash heating unit 5, is a plate-shaped quartz window made of quartz. By installing the flash heating unit 5 above the chamber 6, the lamp light emission window 53 faces the upper chamber window 63. The flash lamps FL irradiate flash light from above the chamber 6 into the heat treatment space 65 via the lamp light emission window 53 and the upper chamber window 63.

The multiple flash lamps FL are each a rod-shaped lamp with a long cylindrical shape, and are arranged in a plane so that their longitudinal directions are parallel to each other along the main surface of the semiconductor wafer W held by the holder 7 (i.e., along the horizontal direction). Therefore, the plane formed by the arrangement of the flash lamps FL is also a horizontal plane. The area in which the multiple flash lamps FL are arranged is larger than the planar size of the semiconductor wafer W.

A xenon flash lamp FL comprises a cylindrical glass tube (discharge tube) filled with xenon gas and fitted with an anode and cathode connected to a capacitor at both ends, and a trigger electrode attached to the outer surface of the glass tube. Because xenon gas is an electrical insulator, electricity does not flow within the glass tube under normal conditions, even if a charge is stored in the capacitor. However, when a high voltage is applied to the trigger electrode, breaking down the insulation, the electricity stored in the capacitor flows instantaneously within the glass tube, exciting the xenon atoms or molecules and emitting light. Such a xenon flash lamp FL converts electrostatic energy previously stored in the capacitor into extremely short light pulses of 0.1 to 100 milliseconds, enabling it to emit extremely intense light compared to continuous light sources such as halogen lamps. In other words, a flash lamp FL is a pulsed lamp that emits light instantaneously for an extremely short period of time, less than one second. The light emission time of the flash lamp FL can be adjusted by the coil constant of the lamp power supply that supplies power to the flash lamp FL.

The reflector 52 is also provided above the multiple flash lamps FL, covering them entirely. The basic function of the reflector 52 is to reflect the flash light emitted from the multiple flash lamps FL towards the heat treatment space 65. The reflector 52 is made of an aluminum alloy plate, and its surface (the surface facing the flash lamps FL) has been roughened by blasting.

The auxiliary heating unit 4, located below the chamber 6, has multiple (e.g., 184) halogen lamps HL built into the housing 41 as light sources. Each halogen lamp HL is a point light source lamp. Point light source lamps are easier to provide localized irradiation than rod-shaped lamps, and are suitable for adjusting the in-plane illuminance distribution of the semiconductor wafer W. The auxiliary heating unit 4 is a light irradiation unit that uses multiple halogen lamps HL to irradiate light from below the chamber 6 through the lower chamber window 64 into the heat treatment space 65, thereby heating the semiconductor wafer W within the chamber 6.

Inside the housing 41, multiple halogen lamps HL are arranged in a plane. The multiple halogen lamps HL may be arranged, for example, in a grid pattern, or in concentric circles of different diameters. Alternatively, the multiple halogen lamps HL may be arranged at different height positions.

Halogen lamps HL are filament-type light sources that emit light by passing electricity through a filament placed inside a glass tube, causing it to become incandescent. The glass tube is filled with an inert gas such as nitrogen or argon to which trace amounts of halogen elements (iodine, bromine, etc.) have been added. By adding halogen elements, it is possible to set the filament temperature to a high temperature while preventing filament breakage. Therefore, halogen lamps HL have the characteristics of having a longer lifespan than regular incandescent light bulbs and being able to continuously emit strong light. In other words, halogen lamps HL are continuously lit lamps that emit light for at least one second or more.

Power is supplied to the multiple halogen lamps HL of the auxiliary heating unit 4 from a power regulator 49. A single heat treatment apparatus 1 is provided with multiple (e.g., 40) power regulators 49, but this number is less than the number of halogen lamps HL. Therefore, multiple halogen lamps HL are connected to a single power regulator 49, and this power regulator 49 controls the power supply to the multiple halogen lamps HL. In this embodiment, there are two types of connection configurations for multiple halogen lamps HL to a single power regulator 49. In the first connection configuration, multiple halogen lamps HL are connected in series to a single power regulator 49. In the second connection configuration, multiple halogen lamps HL are connected to a single power regulator 49 in a mixture of series and parallel.

Figure 7 is a diagram showing a circuit in which multiple halogen lamps HL are connected in series to a power regulator 49. In this embodiment, for example, four halogen lamps HL are connected in series to one power regulator 49 (four in series). The rated voltage of each halogen lamp HL is, for example, 100V, and the rated current is, for example, 6A. In other words, the maximum power that can be input to one halogen lamp HL is 600W. In the first connection configuration shown in Figure 7, the power regulator 49 applies a voltage of 400V to the four halogen lamps HL connected in series. As a result, a voltage of 100V is applied to each halogen lamp HL.

On the other hand, Figure 8 shows a circuit in which multiple halogen lamps HL are connected to a power regulator 49 in a mixture of series and parallel connections. In this embodiment, for example, two of four halogen lamps HL connected in series are connected in parallel to one power regulator 49 (4 in series x 2 in parallel). In other words, a total of eight halogen lamps HL are connected to one power regulator 49. Each halogen lamp HL is the same as in the first connection configuration, and therefore the rated voltage and rated current of each halogen lamp HL are also the same as described above. In the second connection configuration shown in Figure 8, the power regulator 49 also applies a voltage of 400V. In the second connection configuration, since it is 4 in series x 2 in parallel, a voltage of 100V is applied to each halogen lamp HL, just like in the first connection configuration.

In both the first and second connection configurations, the applied voltage is 400V, but the maximum power that can be input is 2400W in the first connection configuration and 4800W in the second connection configuration. Therefore, the rated power of the power regulator 49 in this embodiment is 4800W. Note that although a rated power of 2400W is sufficient for the power regulator 49 in the first connection configuration, the rated power of the power regulator 49 in the first connection configuration is also set to 4800W in order to unify the specifications of all power regulators 49.

In this embodiment, the auxiliary heating unit 4 contains a mixture of multiple halogen lamps HL connected in the first connection configuration and multiple halogen lamps HL connected in the second connection configuration. That is, some of the multiple halogen lamps HL provided in the auxiliary heating unit 4 are connected in parallel to the power regulator 49. In the second connection configuration, the number of parallel connections of multiple halogen lamps HL connected to the power regulator 49 is two.

The control unit 3 controls the various operating mechanisms provided in the heat treatment device 1. Figure 9 is a block diagram showing the configuration of the control unit 3. The hardware configuration of the control unit 3 is similar to that of a typical computer. That is, the control unit 3 includes a CPU, which is a circuit that performs various arithmetic processing, ROM, which is read-only memory that stores basic programs, RAM, which is readable and writable memory that stores various information, and a storage unit 34 (e.g., a magnetic disk or SSD) that stores control software, data, etc. Processing in the heat treatment device 1 progresses as the CPU of the control unit 3 executes a predetermined processing program.

The memory unit 34 of the control unit 3 stores a processing recipe 35 that defines the procedures and conditions for processing the semiconductor wafer W. The processing recipe 35 is acquired by the heat processing apparatus 1, for example, by an operator of the apparatus inputting it via the input unit 32 (described below) and storing it in the memory unit 34. Alternatively, the processing recipe 35 may be transferred via communication from a host computer that manages multiple heat processing apparatuses 1 to the heat processing apparatus 1 and stored in the memory unit 34.

The control unit 3 also has a fault detection unit 38. The fault detection unit 38 is a functional processing unit that is realized when the CPU of the control unit 3 executes a predetermined processing program. The processing content of the fault detection unit 38 will be described in more detail below.

The control unit 3 is electrically connected to elements such as multiple power regulators 49. Each power regulator 49 is equipped with a thyristor 45, a voltage monitor 47, and a current monitor 48. The power regulator 49 controls the output power through thyristor phase control using the thyristor 45. Specifically, the power regulator 49 controls the output power by changing the conduction angle of the thyristor 45. The power regulator 49 also monitors the output power using the voltage monitor 47 and the current monitor 48. Specifically, the power regulator 49 measures the output power by multiplying the voltage measured by the voltage monitor 47 by the current measured by the current monitor 48.

The control unit 3 provides instruction values (power instruction values) to each power regulator 49, for example, according to the contents of the process recipe 35. The power regulator 49 monitors the output power using the voltage monitor 47 and current monitor 48, and controls the power so that the output power matches the instruction value. For example, if the output power is lower than the instruction value, the power regulator 49 increases the conduction angle of the thyristor 45 to increase the output power. Conversely, if the output power is higher than the instruction value, the power regulator 49 decreases the conduction angle of the thyristor 45 to decrease the output power. Furthermore, if the output power does not reach the instruction value even when the conduction angle of the thyristor 45 is increased to its maximum, the power regulator 49 signals an out-of-control state and issues an alarm.

Furthermore, a display unit 33 and an input unit 32 are connected to the control unit 3. The display unit 33 and the input unit 32 function as a user interface for the heat treatment device 1. The control unit 3 displays various information on the display unit 33. An operator of the heat treatment device 1 can input various commands and parameters from the input unit 32 while checking the information displayed on the display unit 33. The input unit 32 can be, for example, a keyboard or a mouse. The display unit 33 can be, for example, a liquid crystal display. In this embodiment, the display unit 33 and the input unit 32 are implemented as liquid crystal touch panels provided on the outer wall of the heat treatment device 1, providing both functions.

In addition to the above configuration, the heat treatment apparatus 1 is equipped with various cooling structures to prevent excessive temperature increases in the auxiliary heating unit 4, flash heating unit 5, and chamber 6 due to the thermal energy generated by the halogen lamps HL and flash lamps FL during heat treatment of the semiconductor wafer W. For example, a water-cooled pipe (not shown) is provided in the wall of the chamber 6. The auxiliary heating unit 4 and flash heating unit 5 also have an air-cooled structure that creates a gas flow inside to remove heat. Air is also supplied to the gap between the upper chamber window 63 and the lamp light emission window 53 to cool the flash heating unit 5 and upper chamber window 63.

Next, the processing operations in the heat treatment apparatus 1 will be described. Figure 10 is a flowchart showing the procedure for the processing operations in the heat treatment apparatus 1. The processing operations described below proceed as the control unit 3 controls each operating mechanism of the heat treatment apparatus 1.

First, prior to processing the semiconductor wafer W, the gas supply valve 84 is opened, and the exhaust valve 89 is also opened to begin supplying and exhausting air to and from the chamber 6. When the valve 84 is opened, nitrogen gas is supplied to the heat treatment space 65 through the gas supply hole 81. When the valve 89 is opened, the gas inside the chamber 6 is exhausted through the gas exhaust hole 86. As a result, the nitrogen gas supplied from the top of the heat treatment space 65 inside the chamber 6 flows downward and is exhausted from the bottom of the heat treatment space 65.

Next, gate valve 185 is opened to open the transport opening 66, and a transport robot external to the apparatus transports the preceding semiconductor wafer W to be processed into the heat treatment space 65 within chamber 6 through the transport opening 66 (step S1). At this time, there is a risk that the atmosphere outside the apparatus will be drawn in as the semiconductor wafer W is transported, but because nitrogen gas is continuously supplied to chamber 6, the nitrogen gas flows out through the transport opening 66, minimizing the drawing in of such external atmosphere.

The semiconductor wafer W carried in by the transport robot advances to a position directly above the holder 7 and stops there. Then, the pair of transfer arms 11 of the transfer mechanism 10 move horizontally from the retracted position to the transfer operation position and rise, causing the lift pins 12 to pass through the through holes 79 and protrude from the upper surface of the holding plate 75 of the susceptor 74 to receive the semiconductor wafer W. At this time, the lift pins 12 rise above the upper ends of the substrate support pins 77.

After the semiconductor wafer W is placed on the lift pins 12, the transport robot exits the heat treatment space 65, and the gate valve 185 closes the transport opening 66. The pair of transfer arms 11 then descend, transferring the semiconductor wafer W from the transfer mechanism 10 to the susceptor 74 of the holder 7, where it is held horizontally from below. The semiconductor wafer W is supported by multiple substrate support pins 77 erected on the holding plate 75 and held on the susceptor 74. The semiconductor wafer W is held on the holder 7 with its front surface to be processed facing upward. A predetermined gap is formed between the back surface (the main surface opposite the front surface) of the semiconductor wafer W supported by the multiple substrate support pins 77 and the holding surface 75a of the holding plate 75. The pair of transfer arms 11, which have descended below the susceptor 74, are then retracted to a retracted position, i.e., inside the recess 62, by the horizontal movement mechanism 13.

After the preceding semiconductor wafer W is held horizontally from below by the susceptor 74 of the holder 7, which is made of quartz, a heating process is performed on that semiconductor wafer W (step S2). First, preheating (assisted heating) begins with light being emitted from the multiple halogen lamps HL of the auxiliary heating unit 4. The light emitted from the multiple halogen lamps HL passes through the lower chamber window 64 and susceptor 74, both of which are made of quartz, and is irradiated onto the underside of the semiconductor wafer W. The semiconductor wafer W is preheated by being irradiated with light from the halogen lamps HL, causing its temperature to rise. Note that the transfer arm 11 of the transfer mechanism 10 is retracted inside the recess 62, so it does not interfere with heating by the halogen lamps HL.

The temperature of the semiconductor wafer W, which is heated by light irradiation from the halogen lamps HL, is measured by the radiation thermometer 20. The measured temperature of the semiconductor wafer W is transmitted to the control unit 3. The control unit 3 monitors whether the temperature of the semiconductor wafer W, which is heated by light irradiation from the halogen lamps HL, has reached the predetermined preheating temperature T1, and provides an instruction value to the power regulator 49 to adjust the output of the halogen lamps HL. In other words, the control unit 3 feedback-controls the output of the halogen lamps HL based on the value measured by the radiation thermometer 20 so that the temperature of the semiconductor wafer W reaches the preheating temperature T1.

After the temperature of the semiconductor wafer W reaches the preheating temperature T1, the control unit 3 maintains the semiconductor wafer W at that preheating temperature T1 for a while. Specifically, when the temperature of the semiconductor wafer W measured by the radiation thermometer 20 reaches the preheating temperature T1, the control unit 3 provides an appropriate instruction value to the power regulator 49 to adjust the output of the halogen lamp HL, thereby maintaining the temperature of the semiconductor wafer W at approximately the preheating temperature T1.

When a predetermined time has elapsed since the temperature of the semiconductor wafer W reached the preheating temperature T1, the flash lamps FL of the flash heating unit 5 irradiate the surface of the semiconductor wafer W held on the susceptor 74 with flash light. At this time, part of the flash light emitted from the flash lamps FL heads directly into the chamber 6, while the other part is reflected by the reflector 52 before heading into the chamber 6, and the semiconductor wafer W is flash-heated by the irradiation of these flash lights.

Flash heating is performed by irradiating a flash of light (flash of light) from the flash lamps FL, which allows the surface temperature of the semiconductor wafer W to rise in a short period of time. In other words, the flash of light irradiated from the flash lamps FL is an extremely short, intense flash of light with an irradiation time of approximately 0.1 milliseconds to 100 milliseconds, in which electrostatic energy previously stored in a capacitor is converted into an extremely short light pulse. The surface temperature of the semiconductor wafer W flash-heated by irradiating it with flash light from the flash lamps FL instantaneously rises to the processing temperature T2, after which the surface temperature drops rapidly. In this way, with flash heating, the surface temperature of the semiconductor wafer W rises and falls significantly in an extremely short period of time.

After the flash heating process is completed, light irradiation from the halogen lamps HL also stops after a predetermined time has elapsed. This causes the semiconductor wafer W to rapidly cool from the preheating temperature T1. The temperature of the semiconductor wafer W during cooling is measured by the radiation thermometer 20, and the measurement results are transmitted to the control unit 3. The control unit 3 monitors, based on the measurement results from the radiation thermometer 20, whether the temperature of the semiconductor wafer W has cooled to a predetermined temperature. After the temperature of the semiconductor wafer W has cooled to or below the predetermined temperature, the pair of transfer arms 11 of the transfer mechanism 10 again move horizontally from the retracted position to the transfer operation position and rise, causing the lift pins 12 to protrude from the top surface of the susceptor 74 and receive the post-heat-treatment semiconductor wafer W from the susceptor 74. Next, the transfer opening 66, which had been closed by the gate valve 185, is opened, and the preceding semiconductor wafer W placed on the lift pins 12 is removed from the chamber 6 by a transfer robot external to the apparatus, completing the heat treatment of the semiconductor wafer W (step S3).

After the preceding semiconductor wafer W, which has been subjected to the heating process, is removed from the chamber 6, a fault detection process for the halogen lamp HL is carried out (step S4). The details of this fault detection process will be described in detail later. After the fault detection process is completed, the succeeding semiconductor wafer W is carried into the chamber 6 using the same procedure as described above (step S5), and the subsequent semiconductor wafer W is subjected to the heating process. Thereafter, the same procedure is repeated.

FIG. 11 is a flowchart showing the procedure for detecting a fault in a halogen lamp HL. A typical fault in a halogen lamp HL is a broken filament. When a filament breaks, current stops flowing to that halogen lamp HL, and it is no longer able to emit light. In the first connection configuration shown in FIG. 7, if a break occurs in any of the four halogen lamps HL connected in series, no current will flow through the entire circuit. In addition to issuing an alarm in the event of an uncontrollable state as described above, the power regulator 49 also issues a break alarm if there is a large change in resistance. When a break occurs in any of the four halogen lamps HL connected in series and no current flows at all, the power regulator 49 detects the large change in resistance and issues a break alarm, making fault detection easy.

On the other hand, in the second connection configuration shown in FIG. 8, because a parallel connection is included, even if a break occurs in one of the halogen lamps HL, current will flow to the lamp row in which the break occurs. From the perspective of the power regulator 49, the load is the same in the first connection configuration shown in FIG. 7 where none of the halogen lamps HL are broken, and in the second connection configuration shown in FIG. 8 where one of the halogen lamps HL is broken, making it difficult to detect a break using the resistance value. For this reason, in the second connection configuration, a break in a halogen lamp HL is detected as follows.

First, after the preceding semiconductor wafer W is unloaded from the chamber 6, the fault detection unit 38 of the control unit 3 provides a detection instruction value to each power regulator 49 (step S11). In the second connection configuration, eight halogen lamps HL are connected in two parallel configurations to one power regulator 49, and the "detection instruction value" is an instruction value greater than 50% of the maximum power that can be applied to all parallel connections in the second connection configuration. Specifically, the maximum power that can be applied to all parallel connections in the second connection configuration is 4800 W, and the fault detection unit 38 provides a detection instruction value greater than 50% of that, or 2400 W, to the power regulator 49. The upper limit of the detection instruction value is 100% of the maximum power that can be applied to all parallel connections (i.e., 4800 W).

The power regulator 49, which receives the detection instruction value from the fault detection unit 38, controls the power so that the output power matches the detection instruction value. To do this, the power regulator 49 measures the output power in real time (step S12). That is, the power regulator 49 measures the output power by multiplying the voltage measured by the voltage monitor 47 by the current measured by the current monitor 48.

Next, the fault detection unit 38 compares the output power measured by the voltage monitor 47 and current monitor 48 with the detection instruction value (step S13). Figure 12 is a diagram schematically showing the difference in output power depending on whether or not a halogen lamp HL is broken. In the second connection configuration, if none of the eight halogen lamps HL is broken, current can flow through both of the two parallel connections, and the power regulator 49 adjusts the conduction angle of the thyristor 45, causing the output power to reach the detection instruction value (right side of Figure 12). For example, when the fault detection unit 38 inputs 3000 W as the detection instruction value to the power regulator 49, if none of the eight halogen lamps HL is broken, the output power will reach 3000 W.

On the other hand, if any of the eight halogen lamps HL is broken, current will flow through only one of the two parallel lamps, and the maximum power that can be applied to that lamp string will be the limit of the power that can be applied to the entire circuit. In the example of this embodiment, if any of the eight halogen lamps HL is broken, 50% of the maximum power that can be applied to all parallel lamps (i.e., 2400 W) will be the limit of the power that can be applied to the entire circuit. As described above, the detection instruction value is a value greater than 50% of the maximum power that can be applied to all parallel lamps. Therefore, if any of the eight halogen lamps HL is broken, the output power will not reach the detection instruction value even if the power regulator 49 maximizes the conduction angle of the thyristor 45 (left side of Figure 12). For example, if the fault detection unit 38 inputs 3000 W as the detection instruction value to the power regulator 49 as described above, the output power will only reach 2400 W, even if the power regulator 49 maximizes the conduction angle of the thyristor 45.

In other words, if the measured output power is equal to the detection indication value, it means that none of the eight halogen lamps HL has a broken wire. Therefore, in this case, the fault detection unit 38 determines that there is no fault, and the process proceeds from step S13 to step S15, where processing of the subsequent semiconductor wafer W begins.

On the other hand, if the measured output power does not reach the detection indication value, it means that a break has occurred in one of the eight halogen lamps HL. Therefore, in this case, the fault detection unit 38 determines that a fault has occurred and proceeds from step S13 to step S14, where the power regulator 49 issues an alarm indicating that a halogen lamp HL has broken. Furthermore, the loading of subsequent semiconductor wafers W into the chamber 6 is halted. Note that with the first connection configuration, the output power is zero regardless of the indication value given and does not reach the detection indication value, making it easy to determine whether a fault has occurred. Furthermore, if a break has occurred in a halogen lamp HL in both of the two parallel connections, no current will flow through the entire circuit, making it easy to detect a break, just as with the first connection configuration.

In this embodiment, when detecting a fault in a halogen lamp HL, a detection instruction value is given to the power regulator 49 to which the halogen lamps HL are connected in parallel. The detection instruction value is a value greater than 50% of the maximum power that can be input to all parallel lamps connected to the power regulator 49. If the measured output power is less than the detection instruction value, it is determined that a fault has occurred in one of the eight halogen lamps HL, and an alarm is issued.

The power regulator 49 is an essential mechanism for controlling the power supply to the halogen lamp HL of the auxiliary heating unit 4. In this embodiment, a fault in the halogen lamp HL is detected by the simple method of giving a relatively large instruction value (detection instruction value) to the power regulator 49, which is originally provided as an element for controlling the power supply. In other words, with this embodiment, fault detection is performed using only existing mechanisms without the need for a dedicated mechanism just for detecting faults in the halogen lamp HL, so faults in the halogen lamp HL can be reliably detected without increasing the footprint or cost.

Furthermore, in this embodiment, fault detection processing is performed between the time when the heating process for the preceding semiconductor wafer W is completed and the semiconductor wafer W is unloaded from the chamber 6 and the time when the subsequent semiconductor wafer W is loaded into the chamber 6. Fault detection is possible even during processing of a semiconductor wafer W if a command value greater than 2400 W is given to the power regulator 49. However, depending on the processing recipe 35, heating processing is often performed at a power of 2400 W or less, and in such cases fault detection is not possible. For this reason, in this embodiment, fault detection processing is performed by giving a detection command value greater than 2400 W to the power regulator 49 between the time when the preceding processed semiconductor wafer W is unloaded from the chamber 6 and the time when the subsequent unprocessed semiconductor wafer W is loaded into the chamber 6. This ensures reliable detection of faults in the halogen lamp HL, regardless of the content of the processing recipe 35. Furthermore, because no semiconductor wafers W are being processed in the chamber 6 when a broken wire in the halogen lamp HL is detected, the number of semiconductor wafers W that are subject to processing defects can be minimized.

The above describes an embodiment of the present invention, but various modifications other than those described above are possible without departing from the spirit of the present invention. For example, in the above embodiment, the number of parallel halogen lamps HL connected to the power regulator 49 was set to two, and the detection instruction value was set to a value greater than 50% of the maximum power that can be applied to all parallel lamps. However, this is not limited to this embodiment. For example, the number of parallel halogen lamps HL connected to the power regulator 49 may be three or more. When the number of parallel halogen lamps HL connected to the power regulator 49 is N (N is an integer greater than or equal to two), the detection instruction value is set to a value greater than the maximum power that can be applied to (N-1) parallel lamps. For example, if five parallel halogen lamps HL are connected to the power regulator 49, the detection instruction value is set to a value greater than the maximum power that can be applied to four parallel lamps. When the fault detection unit 38 provides the power regulator 49 with a detection instruction value greater than the maximum power that can be applied to (N-1) parallel lamps, the fault detection unit 38 determines that one of the multiple halogen lamps HL has failed if the output power is less than the detection instruction value. This approach also achieves the same effects as the above embodiment.

Furthermore, in the above embodiment, a filament-type halogen lamp HL was used as the light source provided in the auxiliary heating section 4, but this is not limited to this, and the light source may also be a light-emitting diode (LED: Light Emitting Diode), a laser diode (LD: Laser Diode), or a VCSEL (Vertical Cavity Surface Emitting Laser). Although there is no concept of a broken wire with these semiconductor element light sources, failure modes such as an open failure do exist, and failure detection can be performed in the same manner as in the above embodiment.

Furthermore, the auxiliary heating unit 4 may be provided with multiple types of light sources. For example, the auxiliary heating unit 4 may be provided with a VCSEL and a laser diode, and the laser diode may irradiate the entire surface of the semiconductor wafer W with light, while the VCSEL may irradiate the peripheral portion, where temperature drops are more likely to occur, with highly directional light. In other words, the light source provided in the auxiliary heating unit 4 may be one or more selected from the group consisting of a halogen lamp HL, a light-emitting diode, a laser diode, and a VCSEL.

Furthermore, in the above embodiment, the power regulator 49 controls the output power using thyristor phase control, but instead, the output power may be controlled using PWM (Pulse Width Modulation) control.

Furthermore, in the above embodiment, some of the multiple halogen lamps HL were connected in parallel to the power regulator 49, but all of the multiple halogen lamps HL may also be connected in parallel to the power regulator 49.

Furthermore, in the above embodiment, the flash heating unit 5 was equipped with 30 flash lamps FL, but this is not limited to this and the number of flash lamps FL can be any number. Furthermore, the flash lamps FL are not limited to xenon flash lamps and may be krypton flash lamps.

REFERENCE SIGNS LIST 1 Heat treatment apparatus 3 Control unit 4 Auxiliary heating unit 5 Flash heating unit 6 Chamber 7 Holding unit 10 Transfer mechanism 20 Radiation thermometer 38 Fault detection unit 45 Thyristor 47 Voltage monitor 48 Current monitor 49 Power regulator 65 Heat treatment space 74 Susceptor FL Flash lamp HL Halogen lamp W Semiconductor wafer

Claims (10)

A heat treatment apparatus that heats a substrate by irradiating the substrate with light,
a chamber for housing the substrate;
a light irradiation unit that includes a plurality of light sources and irradiates light onto the substrate accommodated in the chamber;
a power regulator for supplying power to the plurality of light sources according to an instruction value;
a failure detection unit that detects that a failure has occurred in any of the plurality of light sources;
Equipped with
some or all of the plurality of light sources are connected in parallel to the power regulator;
the number of parallel connections of the plurality of light sources connected to the power regulator is N;
The fault detection unit determines that a fault has occurred in one of the multiple light sources when an instruction value greater than the maximum power that can be input to the power regulator is given to the power regulator and the output power is less than the instruction value. 2. The heat treatment apparatus according to claim 1,
the number of parallel connections of the plurality of light sources connected to the power regulator is two,
A heat treatment device in which the fault detection unit determines that a fault has occurred in one of the multiple light sources when an instruction value greater than 50% of the maximum power that can be input to all parallel connections is given to the power regulator and the output power is less than the instruction value. 2. The heat treatment apparatus according to claim 1,
The failure detection unit provides the instruction value to the power regulator during the period from when the heating process on the preceding substrate is completed and the preceding substrate is unloaded from the chamber until when the subsequent substrate is loaded into the chamber. 2. The heat treatment apparatus according to claim 1,
The power regulator adjusts the power to the plurality of light sources by thyristor phase control. 5. The heat treatment apparatus according to claim 1,
The heat treatment apparatus, wherein the plurality of light sources are one selected from the group consisting of a halogen lamp, a light emitting diode, a laser diode, and a vertical cavity surface emitting laser. A heat treatment method for heating a substrate by irradiating the substrate with light, comprising:
an irradiation step of irradiating light from a plurality of light sources onto the substrate accommodated in the chamber;
a failure detection step of detecting that a failure has occurred in any of the plurality of light sources;
Equipped with
some or all of the plurality of light sources are connected in parallel to a power regulator that supplies power to the plurality of light sources according to an instruction value;
the number of parallel connections of the plurality of light sources connected to the power regulator is N;
In the fault detection process, when an instruction value greater than the maximum power that can be input to the (N-1) parallel light sources is given to the power regulator, if the output power is less than the instruction value, it is determined that a fault has occurred in one of the multiple light sources. The heat treatment method according to claim 6,
the number of parallel connections of the plurality of light sources connected to the power regulator is two,
A thermal processing method in which, in the fault detection process, when an instruction value greater than 50% of the maximum power that can be input to all parallel light sources is given to the power regulator, if the output power is less than the instruction value, it is determined that a fault has occurred in one of the multiple light sources. The heat treatment method according to claim 6,
The heat treatment method, wherein the failure detection step is performed during the period from when the heat treatment on the preceding substrate is completed and the preceding substrate is unloaded from the chamber until when the subsequent substrate is loaded into the chamber. The heat treatment method according to claim 6,
The power regulator adjusts the power to the plurality of light sources by thyristor phase control. The heat treatment method according to any one of claims 6 to 9,
The heat treatment method, wherein the plurality of light sources are one selected from the group consisting of a halogen lamp, a light emitting diode, a laser diode, and a vertical cavity surface emitting laser.