WO2024252815A1 - Substrate - Google Patents

Abstract

Provided is a substrate on which a digital isolator for electrically separating a first voltage region (R1) and a second voltage region (R2) in a plan view is mounted, the substrate comprising: a core layer (101); a first ground layer (121) and a second ground layer (122) on a first main surface of the core layer (101); a first power supply layer (131) and a second power supply layer (132) on a second main surface of the core layer (101); two planar patterns (123, 133) at least partially overlapping each other in the plan view; and a linear pattern (124). The resonance frequency of a resonance circuit including the two planar patterns (123, 133) and the linear pattern (124) has a value corresponding to signal transmission by the digital isolator.

Description

substrate

This disclosure relates to a substrate on which a digital isolator is mounted.

There is a technology for forming a laminated board by stacking multiple conductor patterns (see Patent Document 1). In such a laminated board, if there are parts that operate at high voltage and parts that operate at low voltage within the same board, or if there is a risk of high voltage and large current being applied to low-voltage equipment due to the usage environment, there is a risk of damage or electric shock due to the high voltage being applied to the low-voltage circuit. In addition, if a state occurs in which the GND potential is different between two points, a path is created through which current flows from one GND to the other GND. If current flows through this GND loop, it can cause the circuit or equipment to break down or break, and can be a factor in the generation and amplification of noise. To address these issues, it is necessary to electrically separate, or insulate, the two points in the electric circuit so that no current flows between them.

　Conventional insulating elements have mainly been optical isolators that combine a light-emitting element (e.g., an LED (Light Emitting Diode)) with a light-receiving element, but due to issues with product life and reliability, there is a shift towards digital isolators (see Patent Document 2).

Digital isolators are classified into magnetic coupling and capacitive coupling, depending on the method of signal transmission in the insulating area (see Patent Documents 3 and 4).

Patent No. 5768941 JP 2018-011173 A U.S. Pat. No. 6,054,780 Special Publication No. 2020-515192

The technologies described in each patent document may cause electromagnetic interference (EMI: Electro Magnetic Interference), known as emission.

A substrate according to one embodiment of the present disclosure has a first voltage region and a second voltage region in a plan view, and is a substrate on which a digital isolator is mounted to electrically isolate the first voltage region and the second voltage region, and includes a core layer, a first ground layer which is a conductor and is provided in the first voltage region on the first main surface of the core layer, a second ground layer which is a conductor and is provided in the second voltage region on the first main surface of the core layer, a first power supply layer which is provided in the first voltage region on the second main surface of the core layer, and a second ground layer which is a conductor and is provided in the second voltage region on the second main surface of the core layer. The digital isolator includes a power supply layer, a plurality of planar patterns including two planar patterns that are conductors and are arranged so that at least a portion of the planar patterns overlap each other in a planar view of the board, and a linear pattern that is linear in the planar view, the linear pattern is arranged on a path that connects one of the first ground layer and the first power supply layer and one of the second ground layer and the second power supply layer, the linear pattern is connected to one of the two planar patterns, and the resonant frequency of a resonant circuit including the two planar patterns and the linear pattern has a value corresponding to signal transmission by the digital isolator.

According to one aspect of the present disclosure, it is possible to realize a board on which a digital isolator is mounted that can suppress the occurrence of electromagnetic interference.

FIG. 1 is a schematic diagram showing a signal path of an isolation element. FIG. 2 is a cross-sectional view of a conventional multilayer board. FIG. 3 is a schematic perspective view showing a layer structure of the multilayer board according to the first embodiment. FIG. 4 is a diagram showing a configuration of a multilayer substrate according to the first embodiment. FIG. 5 is a diagram showing an example of propagation characteristics of a common mode current in the multilayer substrate according to the first embodiment. FIG. 6 is a diagram showing a configuration of a multilayer substrate according to the second embodiment. FIG. 7 is a diagram showing a configuration of a multilayer substrate according to the third embodiment. FIG. 8 is a diagram showing the configuration of a double-sided board according to the fourth embodiment.

(Background to this disclosure)
Prior to describing this disclosure, the background to the present disclosure will be described with reference to Figs. 1 and 2. Fig. 1 is a schematic diagram showing a signal path of an isolation element. Fig. 1(a) is a circuit image diagram when the isolation method is a magnetic method, and is illustrated for reference. Fig. 1(b) shows a signal path of an isolation element. Fig. 2 is a cross-sectional view of a multilayer substrate 1000 of a conventional example. Fig. 2(a) is a cross-sectional view of the multilayer substrate 1000, Fig. 2(b) is a plan view showing a second conductor layer 120, and Fig. 2(c) is a plan view showing a third conductor layer 130. The cross-sectional view of the second conductor layer 120 shown in FIG. 2(a) shows a cross-sectional view of the second conductor layer 120 cut along the cutting line IIa1-IIa1 shown in FIG. 2(b), and the cross-sectional view of the third conductor layer 130 shown in FIG. 2(a) shows a cross-sectional view of the third conductor layer 130 cut along the cutting line IIa2-IIa2 shown in FIG. 2(c). Note that the cutting lines IIa1-IIa1 and IIa2-IIa2 overlap in plan view. In addition, the relationship between the cross-sectional views of the second conductor layer 120 and the third conductor layer 130 shown in FIG. 4, FIG. 6 to FIG. 8 shown below and the cutting lines shown in FIG. 2(b) and FIG. 6(c) is the same as that shown in FIG. 2, so the description will be omitted.

The layer structure of the multilayer substrate 1000 will be explained in the embodiment.

As shown in FIG. 1B, a digital isolator basically exchanges signals using high-frequency digital signals on a differential transmission path formed by a transformer or capacitor between regions of different potentials (the first voltage region R1 shown in FIG. 2A, which is the region of V1, and the second voltage region R2 shown in FIG. 2A, which is the region of V2) sandwiching an insulating region R3 (see FIG. 2A). At this time, a common mode current is generated in addition to the normal mode signal on the differential transmission path. This common mode current becomes a leakage current (stray current), but since the digital isolator has an insulating region, there is a risk that the leakage current cannot return from the voltage region to which it is propagated to the voltage region from which the signal originates. The emission of a digital isolator is a phenomenon in which the leakage current that cannot be returned diffuses as radiated noise (emission) from the end of the insulating region. Note that the ground in the first voltage region R1 is GND1, and the ground in the second voltage region R2 is illustrated as GND2.

To reduce emissions caused by leakage current, it is necessary to provide a path for returning current across the barrier between different voltage domains.

One method is to connect a safe-rated capacitor across the barrier between different voltage domains, and the other is to form an overlapping capacitor by extending the ground plane and power plane of the internal layers of the laminate board to the insulating region R3 of the laminate board. The capacitor is formed by a planar pattern 1123 connected to the first ground layer 1121 and a planar pattern 1133 connected to the second power layer 1132. The capacitor may also be formed by a planar pattern connected to the second ground layer 1122 and a planar pattern connected to the first power layer 1131.

Of the two methods, the method of connecting a capacitor has problems such as difficulty in handling high-frequency carrier waves due to the influence of the parasitic inductance of the capacitor, and the loop area of the common mode current formed by the placement of the capacitor and the insulating element becoming larger. Generally, emissions are proportional to the magnitude and area of the current flowing through the loop, so the larger the loop area, the higher the emissions. In addition, when forming a capacitor in an internal layer, it is known that the capacitance of the formed capacitor depends on the thickness of the board, and that the corresponding insulation standard places restrictions on the board thickness. For example, the representative insulation standard IEC62368 (formerly IEC60950) specifies that the thickness of a single layer between conductors of different potentials must be 0.4 mm or more. This causes a problem that the signal passing characteristics (frequency characteristics) obtained by forming an internal layer capacitor do not match the frequency of the carrier wave used in the insulating element.

The inventors of the present application therefore conducted extensive research into a board (board structure) that can efficiently return the common mode current of digital isolation, as a board on which a digital isolator is mounted, to prevent the occurrence of electromagnetic interference, and came up with the board described below.

The following describes the embodiment in detail with reference to the drawings.

The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, components, component placement positions, and connection forms shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components that are not described in an independent claim are described as optional components.

In addition, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. In addition, in each figure, the same reference numerals are used for substantially the same configurations, and duplicate explanations are omitted or simplified.

In addition, in this specification and the drawings, the X-axis, Y-axis, and Z-axis represent the three axes of a right-handed three-dimensional Cartesian coordinate system. In each embodiment, the Z-axis direction is the stacking direction (thickness direction) of the multilayer board. In addition, in this specification, "planar view" means viewing the multilayer board along the stacking direction of the multilayer board.

In addition, in this specification, terms indicating the relationship between elements, such as parallel and coincident, terms indicating the shape of elements, such as linear and meandering, as well as numerical values and numerical ranges, are not expressions that express only the strict meaning, but are expressions that include a substantially equivalent range, for example, a difference of about a few percent (or about 10%).

In addition, in this specification, the terms "on XX (e.g., on the main surface)," "above," and "below" do not refer to the upward direction (vertically above) and downward direction (vertically below) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in the stacked configuration. Furthermore, the terms "on XX (e.g., on the main surface)," "above," and "below" apply not only to cases where two components are arranged with a gap between them and another component exists between the two components, but also to cases where two components are arranged in contact with each other.

In addition, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components, unless otherwise specified, but are used for the purpose of avoiding confusion between and distinguishing between components of the same type.

Furthermore, the "connection" of each component means an electrical connection, and includes not only cases where two components are directly connected, but also cases where two components are indirectly connected with another component inserted between them.

(Embodiment 1)
The multilayer substrate according to the present embodiment will be described below with reference to FIGS.

[1. Configuration of multi-layer board]
Fig. 3 is a schematic perspective view showing the layer configuration of the multilayer substrate 100 according to the present embodiment. Fig. 4 is a diagram showing the configuration of the multilayer substrate 100 according to the present embodiment. Fig. 4(a) is a cross-sectional view of the multilayer substrate 100, Fig. 4(b) is a plan view showing the second conductor layer 120, and Fig. 4(c) is a plan view showing the third conductor layer 130.

In FIG. 3, each conductor layer and the insulating device 107 are illustrated, and for convenience, other components are not illustrated. Also, in FIG. 3, the insulating device 107 is illustrated in a state where it is not mounted on the multilayer substrate 100, and in FIG. 4, the insulating device 107 is illustrated in a state where it is mounted on the multilayer substrate 100. Also, in this embodiment, an example in which a four-layer substrate is used as a representative multilayer substrate 100 will be described.

The multilayer board 100 on which the insulating device 107 is mounted is used in equipment that has a mixture of parts (circuits) that operate at high voltages and parts (circuits) that operate at low voltages, to prevent damage caused by the application of high voltage to parts that operate at low voltages. Examples of equipment include, but are not limited to, industrial equipment such as power supplies and motors, medical equipment, and in-vehicle equipment such as ECUs (Electronic Control Units) installed in hybrid automobiles.

As shown in Figures 3 and 4, the multilayer substrate 100 has a first voltage region R1 and a second voltage region R2 which are different voltage regions, and an insulating region R3 between the first voltage region R1 and the second voltage region R2. The region on the negative Y-axis side of the insulating region R3 (three-dimensional region) is the first voltage region R1 (three-dimensional region), and the region on the positive Y-axis side of the insulating region R3 is the second voltage region R2 (three-dimensional region).

The multilayer substrate 100 also includes a core layer 101, a first insulating layer 102, a second insulating layer 103, and an insulating device 107. The multilayer substrate 100 includes the second insulating layer 103, the core layer 101, and the first insulating layer 102 stacked in this order, and the insulating device 107 is mounted on the first insulating layer 102. The multilayer substrate 100 is an example of a substrate.

The core layer 101 is an insulating substrate provided in the multilayer substrate 100, and is, for example, a resin substrate. The core layer 101 may be formed, for example, from a material that corresponds to the substrate material FR-4 (Flame Retardant Type 4). The core layer 101 may be, for example, but is not limited to, a glass epoxy substrate. The core layer 101 is also a double-sided substrate with conductor layers (second conductor layer 120 and third conductor layer 130) provided on both sides.

The first insulating layer 102 is an insulating layer laminated on the upper surface (first main surface, the surface on the positive side of the Z axis) of the core layer 101. A first conductor layer 110 is provided on the upper surface of the first insulating layer 102.

The second insulating layer 103 is an insulating layer laminated on the lower surface (the second main surface, the surface on the negative side of the Z axis) of the core layer 101. A fourth conductor layer 140 is provided on the lower surface of the second insulating layer 103.

The first insulating layer 102 and the second insulating layer 103 are also called prepreg layers, and are made of, for example, but not limited to, epoxy resin. The first insulating layer 102 and the second insulating layer 103 may also contain carbon fiber, etc.

The first conductor layer 110 is provided on the upper surface (the surface on the positive side of the Z axis) of the first insulating layer 102, and is a layer made of a metal material (e.g., copper foil). The first conductor layer 110 is provided with, for example, wiring, signal lines, etc. for mounting devices (including, for example, the insulating device 107). For example, devices are mounted on the first conductor layer 110.

The first conductor layer 110 has a first conductor pattern 111 provided in the first voltage region R1 and a second conductor pattern 112 provided in the second voltage region R2. The first conductor pattern 111 is formed with a third terminal 111a (conductor pattern) to which the terminal (first terminal) of the insulating device 107 is connected, and the second conductor pattern 112 is formed with a fourth terminal 112a (conductor pattern) to which the terminal (second terminal) of the insulating device 107 is connected.

The first conductor pattern 111 and the second conductor pattern 112 are arranged, for example, at a distance D1 apart. The distance D1 is an insulation distance, which is a creepage distance determined by the potential difference between the first voltage region R1 and the second voltage region R2 and the corresponding insulation standard. In other words, the multilayer substrate 100 has an insulation region R3 of distance D1.

The second conductor layer 120 is provided between the core layer 101 and the first insulating layer 102, and is a layer made of a metal material (e.g., copper foil). The second conductor layer 120 may include, for example, a ground layer.

The second conductor layer 120 has a first ground layer 121 provided in the first voltage region R1 and a second ground layer 122 provided in the second voltage region R2.

The third conductor layer 130 is provided between the core layer 101 and the second insulating layer 103, and is a layer made of a metal material (e.g., copper foil). For example, a power supply layer is provided on the third conductor layer 130.

The third conductor layer 130 has a first power supply layer 131 provided in the first voltage region R1 and a second power supply layer 132 provided in the second voltage region R2.

The fourth conductor layer 140 is provided on the lower surface (the surface on the negative Z-axis side) of the second insulating layer 103, and is a layer made of a metal material (e.g., copper foil). The fourth conductor layer 140 is provided with, for example, wiring, signal lines, etc. for mounting devices. For example, devices are mounted on the fourth conductor layer 140.

The fourth conductor layer 140 has a first conductor pattern 141 provided in the first voltage region R1 and a second conductor pattern 142 provided in the second voltage region R2. The first conductor pattern 141 and the second conductor pattern 142 are provided, for example, at a distance D1 apart.

The isolation device 107 is an isolation amplifier provided between different voltage domains, and is a device that exchanges signals between different voltage domains using a carrier wave while electrically isolating the different voltage domains. The isolation device 107 is also called a digital isolator. The method of transmitting signals in the isolation domain R3 in the isolation device 107 may be a magnetic coupling method or a capacitive coupling method. The isolation device 107 is provided so as to straddle the isolation domain R3. The frequency of the carrier wave of the isolation device 107 is, for example, 480 MHz, but may be lower than 480 MHz, such as 180 MHz, or may be higher than 480 MHz.

Here, we will explain the return path of the common mode current, which is the main part of this application.

The multilayer substrate 100 according to this embodiment further includes a planar pattern 123 and a linear pattern 124 on the second conductor layer 120, and a planar pattern 133 on the third conductor layer 130 to form a return path for the common mode current.

The surface patterns 123 and 133 are arranged so as to overlap at least partially in a planar view. In the example of FIG. 4, the surface pattern 133 is arranged so as to cover the entire surface pattern 123 in a planar view.

The planar pattern 123 is provided, for example, in the insulating region R3 of the second conductor layer 120, spaced apart from the first ground layer 121 and the second ground layer 122 in a planar view. For example, the planar pattern 123 is provided, in the insulating region R3, at a distance D2 from the second ground layer 122 in a planar view. The planar pattern 123 is connected to the first ground layer 121 via the linear pattern 124.

The planar pattern 133 is provided, for example, in the insulating region R3 of the third conductor layer 130 in a plan view so as to protrude from the side surface of the second power layer 132 facing the first power layer 131 (the surface on the negative Y-axis side) toward the first power layer 131 in the plan view. For example, the planar pattern 133 is provided within the insulating region R3 in a plan view so as to be separated from the first power layer 131 by a distance D4. The distance D4 may be equal to the distance D3 or may be smaller than the distance D3. For example, the planar pattern 133 may at least partially overlap the linear pattern 124 in a plan view.

The linear pattern 124 is a conductor pattern for forming an inductor, and is provided on a path (return path) between one of the first ground layer 121 and the first power supply layer 131 and one of the second ground layer 122 and the second power supply layer 132. In the example of FIG. 4, the linear pattern 124 connects the first ground layer 121 and the planar pattern 123 on the path. The length of the linear pattern 124 in the Y-axis direction is, for example, a distance D3. In the example of FIG. 4, the linear pattern 124 has a meandering shape in a planar view, but the shape is not limited to this and may be, for example, a straight line. In addition, the linear pattern 124 may be, for example, a spiral shape formed in another layer via a through hole or the like, as long as it satisfies the regulations on the insulation distance.

In this embodiment, in order to further suppress the occurrence of electromagnetic interference, the planar patterns 123 and 133 and the linear pattern 124 are arranged in positions that overlap the insulating device 107 in a planar view, but are not limited to this.

Note that the above distances D1 to D4 are distances (insulation distances) parallel to the Y axis. Each of the distances D1 to D4 is set to a distance that satisfies the corresponding insulation standard or greater.

As described above, in this embodiment, an inductor is formed by the linear pattern 124, and capacitance is formed by the capacitor (parallel plate capacitor) formed by the planar patterns 123 and 133, forming an LC resonant circuit (LC series resonant circuit) between the first voltage region R1 and the second voltage region R2.

This allows the signal passband to be adjusted using an inductor and a capacitor, making it possible to adjust the frequency over a wider range than when the passband is adjusted using only a capacitor as shown in FIG. 2. This allows the common mode current to be fed back to the signal source more reliably, so the multilayer board 100 can reduce the possibility of causing electromagnetic interference.

The resonant frequency of the LC resonant circuit has a value corresponding to the signal transmission by the isolation device 107. For example, the resonant frequency of the LC resonant circuit is set to allow a signal of the carrier frequency used by the isolation device 107 to pass through. For example, the resonant frequency of the LC resonant circuit is set to match the carrier frequency used by the isolation device 107.

The configuration for forming the return path of the common mode current is not limited to the configuration shown in FIG. 4. For example, the conductor patterns of the second conductor layer 120 and the third conductor layer 130 in the insulating region R3 may be interchanged. For example, a planar surface pattern may be provided so as to protrude from the side surface (the surface on the negative Y-axis side) of the second ground layer 122 on the first ground layer 121 side to the first ground layer 121 side, and a surface pattern that overlaps with the planar pattern in a planar view may be formed on the third conductor layer 130, and the surface pattern of the third conductor layer 130 may be connected to the first power layer 131 by a linear pattern. Also, for example, the linear pattern 124 may connect the surface pattern 123 and the second ground layer 122, and a planar surface pattern may be provided so as to protrude from the side surface (the surface on the positive Y-axis side) of the first power layer 131 on the second power layer 132 side to the second power layer 132 side. Also, for example, the planar pattern 133 may be provided in the insulating region R3 of the third conductor layer 130, spaced apart from the first power layer 131 and the second power layer 132 in a plan view, and connected to the second power layer 132 via a linear pattern. In other words, the linear pattern may be provided on at least one of the second conductor layer 120 and the third conductor layer 130.

[2. Propagation characteristics of multilayer board]
The propagation characteristics of a common mode current in the multilayer substrate 100 configured as above will be described with reference to Fig. 5. Fig. 5 is a diagram showing an example of the propagation characteristics of a common mode current in the multilayer substrate 100 according to the present embodiment.

The multilayer board 100 is made of FR-4, a typical board material. The thickness (length in the Z-axis direction) of the core layer 101 of the multilayer board 100 is 0.6 mm, and the thicknesses of the first insulating layer 102 and the second insulating layer 103 are 0.3 mm.

As shown in FIG. 5, the multilayer board 100 configured in this manner has a transmission characteristic around 480 MHz, which is difficult to achieve with a capacitor alone. In other words, the multilayer board 100 has a propagation characteristic that allows a signal of 480 MHz, which is the carrier frequency of the insulating device 107, to pass through.

By adjusting the shapes of the planar patterns 123, 133 and the linear pattern 124 according to the frequency of the carrier wave to be passed, it is possible to create a path (a return path for the common mode current) through which a signal (e.g., a common mode current) can easily pass from one of the first voltage region R1 and the second voltage region R2 to the other in the band of the carrier wave of the insulating device 107.

In this way, by adjusting the series resonance frequency of the capacitor and inductor, the multilayer board 100 is able to pass high-frequency signals such as 480 MHz, which is difficult to achieve using only a capacitor.

The resonant frequency of the LC resonant circuit may be set, for example, to match the frequency of the carrier wave, or may be set so that the difference between the frequency of the carrier wave and the resonant frequency is equal to or less than a predetermined frequency. In this way, the resonant frequency of the LC resonant circuit has a value corresponding to signal transmission by digital isolation, and the capacitance value and inductor value are determined so as to realize this value.

(Embodiment 2)
The multilayer substrate according to the present embodiment will be described below with reference to Fig. 6. Note that the following description will focus on the differences from the first embodiment, and descriptions of the same or similar contents as the first embodiment will be omitted or simplified.

FIG. 6 is a diagram showing the configuration of a multilayer board 100a according to this embodiment. FIG. 6(a) is a cross-sectional view of the multilayer board 100a, FIG. 6(b) is a plan view showing the second conductor layer 120, and FIG. 6(c) is a plan view showing the third conductor layer 130. The multilayer board 100a according to this embodiment differs from the multilayer board 100 according to embodiment 1 mainly in that two capacitors are formed. The multilayer board 100a is an example of a board. In the following, it is assumed that the distance D7 is equal to or less than the distance D1.

As shown in FIG. 6, the second conductor layer 120 has planar patterns 125 and 126.

The planar pattern 125 is a planar conductor pattern formed so as to protrude from the surface of the first ground layer 121a facing the second ground layer 122a (the surface on the positive side of the Y axis) toward the second ground layer 122a. The planar pattern 126 is a planar conductor pattern formed so as to protrude from the surface of the second ground layer 122a facing the first ground layer 121a (the surface on the negative side of the Y axis) toward the first ground layer 121a. The planar patterns 125 and 126 are provided at positions separated by a distance D5 (insulation distance).

At least one of the planar patterns 125 and 126 may be connected to the conductor pattern via a linear pattern. For example, the planar pattern 125 may be connected to the first ground layer 121a via a linear pattern.

The third conductor layer 130 has planar patterns 134 and 135 and a linear pattern 136.

The planar patterns 134 and 135 are spaced apart from the first power layer 131a and the second power layer 132a in a plan view within the insulating region R3, and are connected by the linear pattern 136.

The planar pattern 134 is a conductor pattern for forming a capacitor using the planar pattern 125 and a portion of the first ground layer 121a. The first power supply layer 131a is formed with a U-shaped recess 131a1 recessed from the surface on the positive side of the Y axis in the negative direction of the Y axis, and at least a portion of the planar pattern 134 is provided in the recess 131a1 such that the distance from the first power supply layer 131a is distance D6. In other words, the planar pattern 134 is provided so as to overlap with a portion of the first ground layer 121a and the planar pattern 125 in a planar view. It is sufficient that the planar pattern 134 overlaps at least the planar pattern 125 in a planar view.

The planar pattern 135 is a conductor pattern for forming a capacitor using the planar pattern 126 and a portion of the second ground layer 122a. The second power supply layer 132a is formed with a U-shaped recess 132a1 recessed from the surface on the negative Y-axis side toward the positive Y-axis direction, and at least a portion of the planar pattern 135 is provided in the recess 132a1 such that the distance from the second power supply layer 132a is distance D6. In other words, the planar pattern 135 is provided so as to overlap with a portion of the second ground layer 122a and the planar pattern 126 in a planar view. It is sufficient that the planar pattern 135 overlaps at least the planar pattern 126 in a planar view.

Linear pattern 136 is a pattern for forming an inductor, and in the example of FIG. 6, is provided between planar patterns 134 and 135 in a plan view, connecting planar patterns 134 and 135. The length of linear pattern 136 in the Y-axis direction is, for example, distance D7. Distance D7 may be, for example, equal to distance D5.

In this way, the multilayer substrate 100a has a planar surface pattern 134 on the first voltage region R1 side of the third conductor layer 130 in the insulating region R3, and a planar surface pattern 135 on the second voltage region R2 side, with the surface patterns 134 and 135 electrically connected by a meandering linear pattern 136.

As a result, an LC resonant circuit can be formed between the first voltage region R1 and the second voltage region R2. By adjusting the shape of at least one of the planar patterns 125, 126, 134, 135 and the linear pattern 136, a path (a return path for a common mode current) through which a signal can easily pass between the first voltage region R1 and the second voltage region R2 according to the carrier band of the insulating device 107 can be created. In addition, since there are two capacitances in the leakage current passage path, it functions as double insulation and can improve the voltage resistance of the multilayer substrate 100a. Such a multilayer substrate 100a can be used in applications where high voltage resistance is required.

Note that the surface patterns 134 and 135 have the same area in a plan view, but may be different from each other, for example.

If the desired capacitance is obtained, the planar patterns 125 and 126 do not need to be provided.

The conductor patterns of the second conductor layer 120 and the third conductor layer 130 may be interchanged. For example, the planar patterns 134 and 135 and the linear pattern 136 may be formed on the second conductor layer 120, and the planar patterns 125 and 126 may be formed on the third conductor layer 130.

Note that the above distances D5 to D7 are distances (insulation distances) parallel to the Y-axis. Each of the distances D5 to D7 is set to a distance that satisfies the corresponding insulation standard or more. For example, the distance D6 is set to a distance that satisfies the corresponding insulation standard at a voltage that is half the rated voltage of the insulating device 107.

(Embodiment 3)
The multilayer substrate according to the present embodiment will be described below with reference to Fig. 7. The following description will focus on the differences from the first embodiment, and descriptions of the same or similar aspects as the first embodiment will be omitted or simplified.

FIG. 7 is a diagram showing the configuration of multilayer board 100b according to this embodiment. FIG. 7(a) is a cross-sectional view of multilayer board 100b, FIG. 7(b) is a plan view showing second conductor layer 120, and FIG. 7(c) is a plan view showing third conductor layer 130. Multilayer board 100b according to this embodiment differs from multilayer board 100 according to embodiment 1 in that a capacitor is formed by the conductor patterns (planar patterns 127 and 137) connected to the ground layer. Multilayer board 100b is an example of a board.

The multilayer substrate 100b according to this embodiment has a planar pattern 127 on the second conductor layer 120, and a planar pattern 137, a linear pattern 138, and a land 139 on the third conductor layer 130 to form a return path for the common mode current. The multilayer substrate 100b also has a through hole 150 that penetrates the core layer 101 in the second voltage region R2.

The surface patterns 127 and 137 are arranged so as to overlap at least partially in a planar view. In the example of FIG. 7, the surface pattern 127 is arranged so as to cover the entire surface pattern 137 in a planar view.

The planar pattern 127 is arranged, for example, in the insulating region R3 of the second conductor layer 120 so as to protrude from the side surface of the first ground layer 121b facing the second ground layer 122b (the surface on the positive Y-axis side) toward the second ground layer 122b. For example, the planar pattern 127 is arranged, in plan view, within the insulating region R3 and at a distance D8 from the second ground layer 122b. Furthermore, the planar pattern 127 may, for example, at least partially overlap the linear pattern 138 in plan view.

The planar pattern 137 is spaced apart from the first power supply layer 131b and the second power supply layer 132b in a planar view. For example, the planar pattern 137 is located within the insulating region R3 and is spaced a distance D9 from the first power supply layer 131b in a planar view. The planar pattern 137 is connected to the second ground layer 122b via the linear pattern 138, the land 139, and the through hole 150.

Linear pattern 138 is a pattern for forming an inductor, and in the example of FIG. 7, it connects planar pattern 137 and land 139. The length of linear pattern 138 in the Y-axis direction is, for example, distance D10.

The land 139 is a conductor pattern electrically connected to the through hole 150. A recess 132b1 is formed in the second power supply layer 132b, recessed in a U-shape from the surface on the negative side of the Y axis toward the positive direction of the Y axis, and at least a portion of the land 139 is provided in the recess 132b1 such that the distance from the second power supply layer 132b is distance D11. In other words, the land 139 is provided so as to overlap a portion of the second power supply layer 132b in a plan view.

The through hole 150 penetrates the core layer 101 of the multilayer board 100 in the stacking direction (Z-axis direction) and connects the land 139 to the second ground layer 122b. In other words, the through hole 150 connects the second ground layer 122b to the planar pattern 137. This makes the second ground layer 122b and the planar pattern 137 at the same potential.

Note that the above distances D8 to D11 are distances (insulation distances) parallel to the Y axis. Each of the distances D8 to D11 is set to a distance that satisfies the corresponding insulation standard or greater.

As described above, in this embodiment, an inductor is formed by the linear pattern 138, a capacitance is formed by the capacitor formed by the planar patterns 127 and 137, and an LC resonant circuit is formed between the first voltage region R1 and the second voltage region R2. By adjusting the shape of at least one of the planar patterns 127, 137 and the linear pattern 138, a path through which a signal can easily pass between the first voltage region R1 and the second voltage region R2 (a return path for a common mode current) according to the carrier band of the insulating device 107 can be created. In the example of FIG. 7, a path through which a signal can pass can be formed between the first ground layer 121b and the second ground layer 122b.

The conductor patterns of the second conductor layer 120 and the third conductor layer 130 in the insulating region R3 may be interchanged. For example, the planar pattern 137, the linear pattern 138, and the land 139 may be formed in the second conductor layer 120, and the planar pattern 127 may be formed in the third conductor layer 130. The land 139 and the through hole 150 are not limited to being provided in the second voltage region R2, and may be provided in the first voltage region R1. In this case, the planar pattern 127 is provided, for example, in the insulating region R3 of the second conductor layer 120 so as to protrude from the side surface of the second ground layer 122b on the first ground layer 121b side (the surface on the negative Y-axis side) to the first ground layer 121b side.

(Embodiment 4)
The double-sided board according to the present embodiment will be described below with reference to Fig. 8. Note that the following description will focus on the differences from the first embodiment, and descriptions of the same or similar aspects as the first embodiment will be omitted or simplified.

8 is a diagram showing the configuration of a double-sided board 100c according to this embodiment. FIG. 8(a) is a cross-sectional view of the double-sided board 100c, FIG. 8(b) is a plan view showing the second conductor layer 120, and FIG. 8(c) is a plan view showing the third conductor layer 130. The double-sided board 100c according to this embodiment differs from the multilayer board 100 according to the first embodiment in that it does not include the first insulating layer 102 and the second insulating layer 103. The double-sided board 100c is also called a two-layer board and is an example of a board. Note that FIG. 8(b) and (c) are substantially the same as FIG. 4(b) and (c), and therefore the description will be omitted. Also, in FIG. 8(b) and (c), the third terminal 121c and the fourth terminal 122c are omitted from illustration.

As shown in FIG. 8, the double-sided substrate 100c includes a core layer 101 and an insulating device 107.

The core layer 101 has a second conductor layer 120 on the first main surface (the surface on the positive side of the Z axis) and a third conductor layer 130 on the second main surface (the surface on the negative side of the Z axis).

The second conductor layer 120 has a first ground layer 121 provided in the first voltage region R1 and a second ground layer 122 provided in the second voltage region R2. A third terminal 121c (conductor pattern) to which the terminal (first terminal) of the isolation device 107 is connected is formed in the first ground layer 121, and a fourth terminal 122c (conductor pattern) to which the terminal (second terminal) of the isolation device 107 is connected is formed in the second ground layer 122. In addition, the second conductor layer 120 may be provided with a mixture of wiring, signal lines, ground layers, etc. for implementing a device (including, for example, the isolation device 107).

The third conductor layer 130 has a first power supply layer 131 provided in the first voltage region R1 and a second power supply layer 132 provided in the second voltage region R2. The third conductor layer 130 may be provided with a mixture of, for example, power supply lines, wiring for implementing devices, signal lines, etc.

Other Embodiments
Although the substrate according to one or more aspects has been described based on each embodiment, the present disclosure is not limited to these embodiments. As long as it does not deviate from the gist of the present disclosure, various modifications conceived by a person skilled in the art to the present embodiment and forms constructed by combining components in different embodiments may also be included in the present disclosure.

For example, the present disclosure may be realized as a method for designing a substrate on which a digital isolator is mounted. The design method includes a step of acquiring the frequency of a carrier wave used by the digital isolator mounted on the substrate, and a step of determining the shapes of the planar pattern and the linear pattern so that the acquired frequency of the carrier wave matches the resonant frequency of the LC series resonant circuit.

In addition, in each of the above embodiments, an example has been described in which the first voltage region R1 and the second voltage region R2 are regions with different voltages, but this is not limited thereto, and the first voltage region R1 and the second voltage region may be regions with the same potential.

Furthermore, the second conductor layer 120 and the third conductor layer 130 in the above-mentioned first embodiment may be interchanged. That is, the first ground layer 121 and the second ground layer 122 may be interchanged with the first power supply layer 131 and the second power supply layer 132. The first ground layer 121, the second ground layer 122, the first power supply layer 131 and the second power supply layer 132 are each a layer to which a DC potential is supplied. For example, whether the second conductor layer 120 functions as a ground layer or a power supply layer is determined after various circuits and the like are mounted on the multilayer board 100. The same applies to the other embodiments.

In the above embodiment 1, an example has been described in which the first ground layer 121 and the second ground layer 122 are provided on the second conductor layer 120, and the first power supply layer 131 and the second power supply layer 132 are provided on the third conductor layer 130, but this is not limited to the example. The first ground layer 121 and the second ground layer 122, and the first power supply layer 131 and the second power supply layer 132 may each be provided on any of the first conductor layer 110, the second conductor layer 120, the third conductor layer 130, and the fourth conductor layer 140.

In addition, in each of the above embodiments, an example has been described in which one or two planar patterns are provided on one main surface of the core layer 101, but the number of planar patterns is not limited to this, and for example, three or more planar patterns may be provided on the one main surface. Similarly, in the case of linear patterns, two or more linear patterns may be provided on the one main surface.

In addition, in each of the above embodiments, at least one part or all of the planar pattern and the linear pattern may be provided in a position that does not overlap with the insulating device 107 in a plan view.

In addition, in each of the above embodiments, the substrate is described as being a two-layer substrate or a four-layer substrate, but this is not limited thereto, and the substrate may be a three-layer substrate or a substrate having five or more layers.

In addition, the substrates in each of the above embodiments may be distributed without the insulating device 107 mounted thereon, or may be distributed with the insulating device 107 mounted thereon.

(Additional Note)
The above description of each embodiment discloses the following techniques.

(Technology 1) A substrate having a first voltage region and a second voltage region in a planar view, on which a digital isolator is mounted that electrically isolates the first voltage region and the second voltage region, the substrate comprising: a core layer; a first ground layer which is a conductor and is provided in the first voltage region on the first main surface of the core layer; a second ground layer which is a conductor and is provided in the second voltage region on the first main surface of the core layer; a first power supply layer which is provided in the first voltage region on the second main surface of the core layer; A board that is an electric body and includes a plurality of planar patterns including two planar patterns that are arranged so that at least a portion of the planar patterns overlap each other in a planar view of the board, and a linear pattern that is linear in the planar view, the linear pattern is arranged on a path that connects one of the first ground layer and the first power supply layer and one of the second ground layer and the second power supply layer, the linear pattern is connected to one of the two planar patterns, and the resonant frequency of a resonant circuit that includes the two planar patterns and the linear pattern has a value that corresponds to signal transmission by the digital isolator.

In this way, by adjusting the shapes of the planar pattern and linear pattern, a path (common mode current return path) can be created that allows a signal (e.g., a common mode current) to easily pass from one of the first voltage domain and the second voltage domain to the other in the carrier band of the digital isolator. For example, it is possible to adjust the pass band according to the carrier frequency more easily than when only a planar pattern is provided on the path (i.e., when only a capacitor is provided). Therefore, in the board on which the digital isolator is mounted, the common mode current is less likely to diffuse as radiated noise (emission), and the occurrence of electromagnetic interference can be suppressed.

(Technology 2) The substrate described in Technology 1, in which the two planar patterns among the plurality of planar patterns are a first planar pattern connected to the first ground layer and a second planar pattern connected to the second power supply layer.

In this way, the first ground layer is formed on the first main surface, and the second power supply layer is formed on the second main surface, so the capacitor can be constructed with a simple structure.

(Technology 3) The linear pattern connects between the first planar pattern and the first ground layer, or between the second planar pattern and the second power layer, in the substrate described in Technology 2.

This allows the resonant frequency of the LC series resonant circuit provided between the first ground layer and the second power layer to be adjusted, making it possible to adjust the passband according to the frequency of the carrier wave in that path, thereby preventing electromagnetic interference.

(Technology 4) A substrate as described in Technology 1, in which two of the plurality of planar patterns are a first planar pattern connected to the first ground layer and a second planar pattern connected to the second ground layer.

This makes it possible to form a return path for the common mode current via the path between the first ground layer and the second ground layer.

(Technology 5) The board described in Technology 4, in which the linear pattern connects between the first planar pattern and the first ground layer, or between the second planar pattern and the second ground layer.

This allows the resonant frequency of the LC series resonant circuit provided between the first ground layer and the second ground layer to be adjusted, making it possible to adjust the passband according to the frequency of the carrier wave in that path, thereby preventing electromagnetic interference.

(Technology 6) The core layer is provided with a through hole penetrating from the first main surface to the second main surface, the first planar pattern is formed on the second main surface, and the linear pattern connects the first planar pattern and the first ground layer via the through hole, in the board described in Technology 5.

As a result, a path can be formed between the first ground layer and the second ground layer by using a configuration with a through hole.

(Technology 7) The substrate described in Technology 1, in which the two planar patterns of the plurality of planar patterns are a first planar pattern connected to the first power supply layer and a second planar pattern connected to the second power supply layer.

This makes it possible to form a return path for the common mode current via the path between the first power supply layer and the second power supply layer.

(Technology 8) The substrate described in Technology 7, in which the linear pattern connects between the first planar pattern and the first power layer, or between the second planar pattern and the second power layer.

This allows the resonant frequency of the LC series resonant circuit provided between the first ground layer and the second power layer to be adjusted, making it possible to adjust the passband according to the frequency of the carrier wave in that path, thereby preventing electromagnetic interference.

(Technology 9) The substrate described in Technology 1, wherein the plurality of planar patterns further includes a third planar pattern and a fourth planar pattern, the two planar patterns among the plurality of planar patterns being a first planar pattern connected to one of the first ground layer and the first power layer, and a second planar pattern connected to one of the second ground layer and the second power layer, at least a portion of the third planar pattern being arranged to overlap the first planar pattern in the planar view, at least a portion of the fourth planar pattern being arranged to overlap the second planar pattern in the planar view, and the linear pattern connecting between the third planar pattern and the fourth planar pattern.

This allows two capacitors to be formed, improving the voltage resistance of the multilayer board.

(Technology 10) A substrate described in any one of techniques 1 to 9, in which the resonant frequency of the resonant circuit is set to allow signals of the carrier frequency used in the digital isolator to pass through.

As a result, the common mode current can be more reliably fed back to the voltage domain of the signal source by an LC resonant circuit with a passband corresponding to the carrier frequency, so that the occurrence of electromagnetic interference can be more reliably suppressed.

(Technology 11) A substrate according to any one of techniques 1 to 10, further comprising a first insulating layer laminated on the first main surface of the core layer and having a conductor layer in each of the first voltage region and the second voltage region, and a second insulating layer laminated on the second main surface of the core layer and having a conductor layer in each of the first voltage region and the second voltage region.

As a result, the two capacitors function as double insulation, improving the voltage resistance of the multilayer board.

(Technology 12) The substrate described in any one of Technology 1 to Technology 11, further comprising the digital isolator.

This makes it possible to prevent electromagnetic interference from occurring on the board on which the digital isolator is mounted.

This disclosure is useful for substrates on which digital isolators are mounted as insulating devices.

100, 100a, 100b multilayer substrate (substrate)
100c Double-sided board (board)
101 Core layer 102 First insulating layer 103 Second insulating layer 107 Isolation device (digital isolator)
110 First conductor layer 111, 141 First conductor pattern 111a, 121c Third terminal 112, 142 Second conductor pattern 112a, 122c Fourth terminal 120 Second conductor layer 121, 121a, 121b First ground layer 122, 122a, 122b Second ground layer 123, 125, 126, 127, 133, 134, 135, 137 Planar pattern 124, 136, 138 Linear pattern 130 Third conductor layer 131, 131a, 131b First power supply layer 131a1, 132a1, 132b1 Recess 132, 132a, 132b Second power supply layer 139 Land 140 Fourth conductor layer 150 Through hole D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11 Distance R1 First voltage region R2 Second voltage region R3 Insulation region

Claims (12)

A substrate having a first voltage region and a second voltage region in a plan view, the substrate having a digital isolator mounted thereon, the digital isolator electrically isolating the first voltage region and the second voltage region,
A core layer;
a first ground layer that is an electric conductor and is provided on a first main surface of the core layer in the first voltage region;
a second ground layer that is an electric conductor and is provided on the first main surface of the core layer in the second voltage region;
a first power supply layer provided in the first voltage region on the second main surface of the core layer;
a second power supply layer provided in the second voltage region on the second main surface of the core layer;
A plurality of planar patterns including two planar patterns that are conductors and are provided so as to at least partially overlap each other in a plan view of the substrate;
A linear pattern that is linear in a plan view;
Equipped with
the linear pattern is provided on a path connecting one of the first ground layer and the first power supply layer to one of the second ground layer and the second power supply layer,
the linear pattern is connected to one of the two planar patterns,
a resonant circuit including the two planar patterns and the linear pattern has a resonant frequency that corresponds to signal transmission by the digital isolator. The two planar patterns among the plurality of planar patterns are
a first planar pattern connected to the first ground layer;
a second planar pattern connected to the second power supply layer;
The substrate according to claim 1 . The linear pattern is
Between the first planar pattern and the first ground layer,
or
Between the second planar pattern and the second power supply layer,
Connect the
The substrate of claim 2. The two planar patterns among the plurality of planar patterns are
a first planar pattern connected to the first ground layer;
a second planar pattern connected to the second ground layer;
The substrate according to claim 1 . The linear pattern is
Between the first planar pattern and the first ground layer,
or
Between the second planar pattern and the second ground layer,
The substrate according to claim 4 , which is connected to the core layer is provided with a through hole penetrating from the first main surface to the second main surface,
the first planar pattern is formed on the second main surface,
The board according to claim 5 , wherein the linear pattern connects the first planar pattern and the first ground layer via the through hole. The two planar patterns among the plurality of planar patterns are
a first planar pattern connected to the first power supply layer;
a second planar pattern connected to the second power supply layer;
The substrate according to claim 1 . The linear pattern is
Between the first planar pattern and the first power supply layer,
or
Between the second planar pattern and the second power supply layer,
The substrate according to claim 7 . the plurality of planar patterns further include a third planar pattern and a fourth planar pattern,
The two planar patterns among the plurality of planar patterns are
a first planar pattern connected to one of the first ground layer and the first power supply layer;
a second planar pattern connected to one of the second ground layer and the second power supply layer;
and
In the plan view, at least a portion of the third planar pattern is provided to overlap with the first planar pattern,
In the plan view, at least a portion of the fourth planar pattern is provided to overlap with the second planar pattern,
The substrate according to claim 1 , wherein the linear pattern connects the third planar pattern and the fourth planar pattern. 10. The substrate according to claim 1, wherein the resonant frequency of the resonant circuit is set to allow a signal having a carrier frequency used in the digital isolator to pass therethrough. a first insulating layer laminated on the first main surface of the core layer, the first insulating layer having a conductor layer in each of the first voltage region and the second voltage region;
a second insulating layer laminated on the second main surface of the core layer, the second insulating layer having a conductor layer in each of the first voltage region and the second voltage region;
The substrate according to any one of claims 1 to 9, further comprising: The substrate according to claim 1 , further comprising the digital isolator.

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