WO2023174086A1 - Universal interface register system and rapid generation method - Google Patents

Abstract

Provided in the present application are a universal interface register system and a rapid generation method. The system comprises a protocol bridge module and a cache module, wherein the protocol bridge module is configured to parse, on the basis of a bus connected to a universal interface register system and a bus protocol, bus data on the bus into an instruction or the instruction and data which are used in the universal interface register system, and to send the instruction or the instruction and the data to a cache module; and the cache module is configured to receive the instruction or the instruction and the data, to read data from the cache module according to the instruction or the instruction and the data, and to send the read data to the protocol bridge module or to cache the read data to the cache module according to the instruction and the data. By means of the universal interface register system provided in the present application, a plurality of bus protocols are docked by means of a protocol bridge and data on a bus is parsed, and the data parsed from the bus is cached by means of modules in a cache module, such that a universal interface for internal logic of an ASIC chip or an SOC chip and the bus is realized.

Description

A universal interface register system and rapid generation method

Cross-references to related applications

This application claims priority to the Chinese patent application submitted to the China Patent Office on March 14, 2022, with application number 202210246442.9 and the application name "A universal interface register system and rapid generation method", the entire content of which is incorporated herein by reference. Applying.

Technical field

This application belongs to the field of computer chips, and specifically relates to a universal interface register system and a rapid generation method.

Background technique

In today's society, with the rapid development of high-tech technologies such as the Internet of Things, cloud computing, big data, artificial intelligence, and autonomous driving, the application and reliability requirements for ASIC chips are becoming higher and higher. The ASIC chip needs to configure the corresponding registers to make the various modules inside the ASIC chip work together. The reliability of the registers and their control logic plays a vital role in the normal operation of the ASIC chip. Therefore, it is necessary to provide registers and Its control logic provides a universal template. After filling in the corresponding parameters, you can get the corresponding register and its control logic. This is crucial for the normal operation of the ASIC (Application Specific Integrated Circuit) chip. effect.

Register interface generally refers to the hardware logic that controls the work of each module by reading and writing registers through the CPU (Central Processing Unit, Central Processing Unit). Chip functions are becoming more and more complex, and the number of required registers is increasing, and there are Different types of registers are required, and it would be very time-consuming and labor-intensive to rely solely on manpower, and errors are prone to occur and are difficult to find. In order to improve efficiency and avoid human errors, traditional technologies are basically aimed at manual implementation of registers and their control logic. Their versatility and completion efficiency are low. After completing these control logics, they still face a huge and complex integration work. , and these tasks are far more time-consuming and labor-intensive than the register control logic design itself.

Application content

In order to solve the above problems, this application proposes a universal interface register system, including a protocol bridge module and a cache module, in which:

The protocol bridge module is configured to parse the bus data on the bus based on the bus connected to the general interface register system into instructions or instructions and data used in the general interface register system based on the bus protocol; and send the instructions or instructions and data to the cache module;

The cache module is configured to receive instructions or instructions and data, and read data from the cache module according to the instructions or instructions and data. Send to the protocol bridge module or cache the data to the cache module according to instructions and data.

In some embodiments of this application, the cache module includes an address decoding module and a register module, where:

The register module includes a general register module and a custom register module. The register module is configured to cache data received by the general interface register system;

The address decoding module is configured to receive instructions or instructions and data from the protocol bridge module, decode the instruction addresses in the instructions or instructions and data, and send the decoded instructions or instructions and data to the corresponding type in the register module. register module; and

Send decoded instructions or instructions and data to memory.

In some embodiments of the present application, the general register module includes general register logic and general register information files, wherein:

The general register logic configuration is used to compare the instructions and/or data received by the general register module with all register information file addresses in the general register information file, select the general register that meets the comparison and write data to the general register or from the general register read data;

The general register information file configuration is used to save the information and addresses of all general registers of the general register module and to provide matching mapping for all registers in the general register module.

In some embodiments of this application, the custom register module includes custom register logic and custom register information files, where:

The custom register logic configuration is used to compare the instructions and/or data received by the custom register module with all register information file addresses in the custom register information file, and select the custom register that satisfies the comparison. And write data to the custom register or read data from the custom register;

The custom register information file is configured to save the information and addresses of all custom registers in the custom register module and provide matching mapping for all registers in the custom register module.

In some embodiments of this application, the cache module also includes:

RxFIFO module, the RxFIFO module is configured to receive data sent from the protocol bus through the protocol bridge module.

TxFIFO module, the TxFIFO module is configured to receive data sent from the protocol bus through the protocol bridge module.

In some embodiments of this application, the cache module also includes:

Interrupt module, the interrupt module is configured to monitor exceptions in the general interface register system in real time, and write the corresponding exceptions to the corresponding exception registers in the general register module, and based on the corresponding exception enable status registers in the general register module and The logical AND operation of the value of the exception register generates the corresponding interrupt signal.

In some embodiments of the present application, the cache module further includes a clock reset module, and the clock reset module includes a clock gating control module. module, asynchronous reset and synchronous release module, where:

The clock gating module is configured to control the clock of one or more general registers in the general register module;

The asynchronous reset synchronous release module is configured to release the general interface register system and the protocol bus synchronously after asynchronous reset.

In some embodiments of this application, the protocol bridge module includes a general protocol read and write state machine, an asynchronous read FIFO, an asynchronous instruction FIFO, an asynchronous write FIFO, and a cache module access state machine, where:

The general protocol read and write state machine is configured to parse the instructions or instructions and data on the protocol bus received by the protocol bridge module, send the instructions to the asynchronous instruction FIFO, and send the data to the asynchronous write FIFO or read the data from the asynchronous read FIFO Encapsulate the transmission data on the protocol bus and send it to the protocol bus;

The cache module access state machine is configured to read instructions from the asynchronous instruction FIFO or read instructions and data from the asynchronous instruction FIFO and from the asynchronous write FIFO and send instructions or instructions and data to the cache module and obtain from the cache module Data is sent to the asynchronous read FIFO.

Another aspect of this application also proposes a method for quickly generating the general interface register system in the above embodiment, including:

Configure function modules and register parameters according to the requirements of the corresponding interface;

Design the hardware circuit of the general interface register system into a template design file;

Activate the corresponding modules in the template design file and generate the final design file according to the functional module and register parameters as well as the configuration parameters of each module in the above-mentioned general interface register system in the configuration file.

In some implementations of this application, configuring functional modules and register parameters according to the requirements of the corresponding interface includes:

Select the corresponding general protocol to read and write state machine logic according to the bus protocol connected to the interface in the required configuration;

Configure the type and number of registers in the general register module and custom register module according to the register parameters.

Through a general interface register system proposed in this application, multiple bus protocols are connected through a protocol bridge and the data on the bus is parsed, and the data parsed from the bus is cached through each module in the cache module, thereby realizing ASIC chips or SOC (System on Chip, system on chip) is a universal interface for the internal logic and bus of the chip. At the same time, the above system is integrated into a universal template, and each module in the universal interface register system is marked. The universal template is cut according to the corresponding marked parameters in the configuration file and the corresponding register interface circuit design file is generated. The design of the interface circuit between each module can be quickly implemented in the SOC chip. You only need to write the bus type connected to the different modules in the SOC chip and the type and number of various registers required for the functional requirements into the configuration file. , which can be generated based on the general template.

Description of the drawings

In order to more clearly illustrate the technical solutions in some embodiments of the present application or in related technologies, the drawings needed to be used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings in the following description are only These are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a structural diagram of a general interface register system provided in some embodiments of the present application;

Figure 2 is a schematic diagram of the internal structure of a protocol bridge of a general interface register system provided in some embodiments of the present application;

Figure 3 is a functional schematic diagram of an address decoding module of a general interface register system provided in some embodiments of the present application;

Figure 4 is a schematic structural diagram of a general register module of a general interface register system provided in some embodiments of the present application;

Figure 5 is a schematic structural diagram of a custom register module of a universal interface register system provided in some embodiments of the present application;

Figure 6 is a schematic diagram of the RxFIFO structure of a general interface register system provided in some embodiments of the present application;

Figure 7 is a schematic structural diagram of an interrupt module of a general interface register system provided in some embodiments of the present application;

Figure 8 is a schematic structural diagram of a clock reset module of a universal interface register system provided in some embodiments of the present application;

Figure 9 is a quick generation method of a general interface register system provided in some embodiments of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application more clear, some embodiments of the present application will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

As shown in Figure 1, this application proposes a universal interface register system, including a protocol bridge module 1 and a cache module 2, where:

The protocol bridge module 1 is configured to parse the bus data on the bus based on the bus connected to the general interface register system into instructions or instructions and data used in the general interface register system based on the bus protocol; and send the instructions or instructions and data to Cache module 2;

The cache module 2 is configured to receive instructions or instructions and data, read data from the cache module and send it to the protocol bridge module according to the instructions or instructions and data, or cache data to the cache module 2 according to the instructions and data.

In some embodiments of the present application, as shown in Figure 1, the protocol bridge module is connected to the CPU (the CPU in the SOC chip or an independent CPU outside the SOC chip) through the connected bus and serves as a "slave", that is, the CPU ancillary equipment. Communicates with the CPU through the bus and receives instructions or data sent by the CPU through the bus. Protocol bridge module 1 sends the CPU through the bus Analyze the bus data sent, that is, according to the bus protocol, the address, chip select signal, read and write data, chip select signal, etc. sent by the CPU are output to the address decoding module for address decoding, thereby determining that the general register address is selected. segment, a custom register address segment, or a memory address segment. If it is a write operation, after selection, the corresponding chip select signal, address, write signal and write data will be given to cache module 2. Similarly, for a read operation, after selection, the corresponding The chip select signal, address, and read signal are given to the cache module 2, and then the returned read data is received and sent to the bus.

The cache module 2 serves as the data cache module of the general interface register system. It is used to receive the parsed write instructions (including chip select signals and addresses) from the protocol bridge module 1 and cache the write data, or to send the data to the protocol bridge according to the read instructions. Module 1 sends the data corresponding to the read command.

In some embodiments of the present application, the cache module 2 includes an address decoding module 3 and a register module 11, where:

The register module 11 includes a general register module 4 and a custom register module 5. The register module 11 is configured to cache data received by the general interface register system;

The address decoding module 3 is configured to receive instructions or instructions and data from the protocol bridge module 1 and decode the instruction addresses in the instructions or instructions and data, and send the decoded instructions or instructions and data to the register module. Corresponding type of register module 11; and

Send decoded instructions or instructions and data to memory.

In some embodiments of the present application, as shown in Figure 3, Figure 3 shows the internal structure diagram of the address decoding module 3, that is, the address decoding module 3 includes address decoding logic 12, and the function of the address decoding logic 12 is Analyze the chip select signal, byte enable signal, read/write enable signal, address, and/or write data parsed by the protocol bridge module 1, and then send the corresponding above-mentioned instructions or the above-mentioned instructions and data according to the analysis results. to general register module 4, custom register module 5, or memory interface 6. That is to say, the function of the address decoding module 3 is to decode the address output by the protocol bridge module and determine that the CPU wants to access the registers in the general register module 4, the registers in the custom register module 5 and Memory (referring to the memory interface). 6 The memory to be accessed directly needs to be accessed by the memory interface 6 in the register system; if it is a write operation, then the corresponding chip select signal, write enable signal, access address, write data and word The enable signal is output to the corresponding module; if it is a read operation, the corresponding chip select signal, read enable, and access address are then output to the corresponding module, and the corresponding read data is obtained.

Specifically, as shown in Figure 3, the address decoding logic 12 performs address decoding on the input read and write addresses to obtain the chip select signal (the chip select signal of the register corresponding to the general register module 4, the chip select signal of the custom register module 5 and Memory chip select signal), if the chip select signal of the general register module 4 is 1, the input chip select signal, byte valid signal, read/write enable signal, address, and read/write data line are output to the general register The chip select signal, byte valid signal, read/write enable signal, address, read/write data line connected to module 4; if the chip select signal of custom register module 5 is 1, Then the input chip select signal, byte valid signal, read/write enable signal, address, read/write data line are output to the chip select signal, byte valid signal, read/write enable connected to the custom register module 5 Signal, address, read/write data lines; if the Memory chip select signal is 1, output the input chip select signal, byte valid signal, read/write enable signal, address, read/write data line to the memory interface 6 Connected chip select signal, byte valid signal, read/write enable signal, address, read/write data line.

In some embodiments of the present application, the general register module 4 includes a general register logic 16 and a general register information file 17, wherein:

The general register logic 16 is configured to compare the instructions and/or data received by the general register module 4 with all register information file addresses in the general register information file 17, select the general register that satisfies the comparison and write data to the general register. Or read data from general register;

The general register information file 17 is configured to save the information and addresses of all general registers of the general register module and provide matching mapping for all registers in the general register module.

In some embodiments of the present application, the function of the general register module 4 is to set some registers necessary for the register interface, such as displaying the enable valid signal, enable clear signal, enable status, interrupt CPU clear signal, and interrupt in clock gating. CPU setting signals, interrupt status, masking signals and other related signals; if the general register module is selected after address decoding, the general register module 4 will write or read the register according to the chip select signal, read and write enable and address The value of When control signals such as read and write enable are valid, compare the internal addresses of all register information mentioned above to select the corresponding register, and then write the value to the register or read the value in the register.

Specifically, as shown in Figure 4, the general register module 4 includes a general register logic 16 and a general register information file 17, where the general register logic 16 receives the chip select signal, byte enable signal, and read signal sent by the general register module 4. /Write enable signals, addresses, and/or write data, and compare the addresses of the above signals with the addresses of all registers in the general register information file 17. If the comparison result is a match and a register is selected, add the register The restriction of the type is to write the written data into the general register through the register logic 16 and finally output it, or to read the input value or the value inside the register after double qualification of address comparison and register type.

In addition, the general register information file 17 contains information of the general interface register system proposed in this application.

In some embodiments of the present application, the custom register module 5 includes custom register logic 18 and a custom register information file 19, wherein:

The custom register logic 18 is configured to combine the instructions and/or data received by the custom register module 5 with the custom Compare all register information file addresses in the defined register information file 19, select the custom register that meets the comparison and write data to the general register or read data from the custom register;

The custom register information file is configured to save the information and addresses of all general registers of the general register module and to provide matching mapping for all custom registers in the custom register module 5 .

In some embodiments of this application, the function of the custom register module is to set some registers required by user hardware logic, such as the most common enable signals of user hardware logic. After address decoding, if the custom register module 5 is selected , the value will be written into the register according to the chip select signal, read and write enable and address, or the value in the register will be read out according to the relevant signal. The custom register module 5 contains a user-defined register containing all the information (address, register type, reset value, invalid bit, etc.), which contains information such as the address of the custom register, reset value, and custom register type. By combining the input address with the chip select signal, read When control signals such as write enable are valid, compare the internal address containing user-defined register information to select the corresponding register, and then write the value to the register or read the value in the register.

Specifically, as shown in Figure 5, the custom register logic 18 in the custom register module 5 selects a custom register by comparing the input address with the address in the custom register information file 19 generated by the script, and then adds The upper register type limit writes the written data to the register through the register logic and finally outputs it, or the value input by the user hardware logic or the value inside the register is read out after address comparison and register type limit.

In some embodiments of the present application, the cache module 2 also includes:

RxFIFO module, the RxFIFO module is configured to receive data sent from the protocol bus through the protocol bridge module.

TxFIFO module, the TxFIFO module is configured to receive data sent from the protocol bus through the protocol bridge module.

In some embodiments of the present application, the register module 11 also includes an RxFIFO module and a TxFIFO module.

The function of RxFIFO and TxFIFO is to add DMA related functions based on the synchronous FIFO function, and also supports Single transmission, Burst transmission and Packet transmission. First, you can choose whether to generate this module by configuring parameters. Secondly, you can choose whether the module is an ordinary synchronous FIFO function or a synchronous FIFO with DMA function by configuring parameters. The depth and data width of the FIFO are also configurable. ; In addition, some other logical functions related to FIFO or DMA can also be added to this module, and the new functions can also be flexibly configured to be turned off/on.

The RxFIFO module and TxFIFO have the same structure, as shown in Figure 6. Figure 6 shows the structure diagram of RxFIFO. The RxFIFO implements a DMA function control module that controls the synchronization FIFO accordingly. When setting the DMA function, you need to The register module 11 has an external DMA module. The DMA module can be integrated on the general interface register system proposed in this application, or can be a different chip module (other modules in Figure 1) outside the general interface register system. The DMA control module, Provide some flow control information to the DMA module, including Single, Burst, and Packet mode selections wait. When the DMA function is not set, TXFIFO and RXFIFO function as ordinary FIFOs.

In some embodiments of the present application, the cache module 2 also includes:

Interrupt module 7, the interrupt module 7 is configured to monitor exceptions in the general interface register system in real time, and write the corresponding exceptions to the corresponding exception registers in the general register module 4, and based on the use of the corresponding exceptions in the general register module 4 The logical AND operation of the values in the status register and exception register generates the corresponding interrupt signal.

In some embodiments of the present application, as shown in Figure 1, the interrupt module 7 is in the register module 11. As in the above embodiment, the interrupt module 7 reads the corresponding register value from the interrupt signal register in the general register module 4 and The corresponding enable status register value is performed, and a logical AND operation is performed, and then an interrupt signal is sent to the CPU based on the operation result, and the CPU handles the corresponding exception.

In a general interface register system provided by this application, the number of exception settings is configurable, and the number of exception ports matching the number of exceptions is configured according to the user's needs; of course, the number of interrupt enable signals is configured to match the number of exceptions. The number of settings is the same. After combining the interrupt settings and interrupt enable and performing a bitwise logical operation, the enabled exception status register can be obtained (needs to be configured in the general register module). This register is used to record the corresponding If it is abnormal, then the enabled exception status register itself will perform a bitwise OR operation to obtain a 1-bit interrupt signal and output it to the CPU. The CPU will then query the exception status register, the enable status register and the enabled exception status register. Get the cause of the exception; in addition, the interrupt module 7 also contains a fixed number of exception settings related to TX FIFO and RX FIFO. These exceptions can be generated according to the configuration of the parameters by choosing whether to generate RX FIFO and TX FIFO. , if the TX FIFO and RX FIFO modules are not generated, then the corresponding interrupts of these two modules will not be generated.

As shown in Figure 7, Figure 7 shows a schematic diagram in which the user configures eight-bit exception settings in the source file template. At the same time, an eight-bit enable status register will be generated. By combining the exception status register and the enable status After the register is bitwise ANDed, an eight-bit enabled exception status register is obtained, and then the eight-bit enabled exception status register itself is bitwise ORed to obtain a 1-bit interrupt signal output to the CPU, and then the CPU These three status registers are queried to obtain the abnormal cause of the interrupt; the interrupt principle inside the RX FIFO and TX FIFO is similar to this. In addition, the interrupt module also supports multi-level interrupt configuration, full interrupt output or single-bit interrupt output.

Specifically, the 8 spaces in the first column shown in Figure 7 represent the exception status register values of the 8 exceptions corresponding to exception #0 to exception #7, and the second column represents the value of the exception status register after being enabled. The three columns refer to the value of the enable status register. As before, when a corresponding exception occurs in the general interface register system, the corresponding exception status register in the first column will be assigned a value. For example, when exception #0 occurs, the first An exception status register will be assigned a value of 1; the value of the enable status register in the third column is specified by the CPU, that is, if you choose to ignore exception #0, the CPU will set this bit to 0 during initialization, and interrupt module 7 will detect After exception #0 is reached, the value 1 of the exception status register and the value of the enable status register will be logically AND operation, if the CPU does not choose to ignore the exception #0, the value of the corresponding enable status register is 1, then the AND result of 1 and 1 is 1, then the enabled exception status register is 1, and the interrupt module 7 sends an interrupt signal to the CPU.

It should be noted that the interrupt module 7 can be flexibly configured as needed. Figure 7 shows only 8 interrupts for abnormal conditions. According to functional needs, more or deeper interrupt exceptions can be flexibly configured based on the above mechanism.

In some embodiments of the present application, the cache module 2 also includes a clock reset module 10. The clock reset module 10 includes a clock gating module 20 and an asynchronous reset and synchronous release module 21, wherein:

The clock gating module 20 is configured to control the clock of one or more general registers in the general register module;

The asynchronous reset synchronous release module 21 is configured to release the general interface register system and the protocol bus synchronously after asynchronous reset.

As shown in Figure 8, the clock module 20 is used to perform a clock gating function (Clock-Gating) on the registers in the general register module 4. It has always been an important means to reduce the power consumption of microprocessors, mainly for registers. Dynamic power consumption caused by flipping, how to design clock gating more effectively is crucial to minimize power consumption while ensuring processor performance), the asynchronous reset synchronous release module 21 is a functional module for asynchronous reset synchronous release, through The configuration of parameters selects whether to generate the above-mentioned clock gating module 20 and asynchronous reset synchronous release module 21. If you choose to generate this module and it is fully functional, the custom register module in Figure 1 comes from the clock gated by the clock gating module 20. The clocks of other modules can also come from the clock gated by the clock module 20. It’s the clock sent in from the top;

In addition, the reset signal is released synchronously after an asynchronous reset; if the clock gating function is generated separately, the custom register module comes from the clock after gating, and the clocks of other modules can come from the clock after gating or can be The clock sent in from the top layer; the reset signal is passed directly from the top layer; if the asynchronous reset is generated separately and released synchronously, the clocks in the custom registers and other modules are passed directly from the top layer, and the reset signal is released synchronously through the asynchronous reset. of.

In some embodiments of the present application, the protocol bridge module 1 includes a general protocol read and write state machine, an asynchronous read FIFO, an asynchronous instruction FIFO, an asynchronous write FIFO, and a cache module access state machine 23, where:

The general protocol read and write state machine is configured to parse the instructions or instructions and data on the protocol bus received by the protocol bridge module, send the instructions to the asynchronous instruction FIFO, and send the data to the asynchronous write FIFO or read the data from the asynchronous read FIFO Encapsulate the transmission data on the protocol bus and send it to the protocol bus;

The cache module access state machine 23 is configured to read instructions from the asynchronous instruction FIFO or read instructions and data from the asynchronous instruction FIFO and from the asynchronous write FIFO, and send instructions or instructions and data to the cache module 2, and from the cache Module 2 obtains data and sends it to the asynchronous read FIFO.

In some embodiments of this application, the protocol bridge module 1 mainly has two functions: protocol conversion and cross-clock domain processing. Protocol conversion is to convert the general protocol interface into a storage SRAM (Static Random-Access Memory, SRAM, Static Random Memory) interface (that is, the bus protocol of the bus connected to the general interface register system and the data transmission interface of the logic circuit inside the general interface register system internal agreement). As the slave end of the bus protocol, the protocol bridge module 1 receives the address, chip select signal, byte enable signal, read and write data and other information sent by the CPU according to the unified standard protocol, and then converts these information contents into SRAM storage The protocol interface (the internal protocol interface of the data transmission interface of the logic circuit within the general interface register system) facilitates subsequent address decoding and storing data in the corresponding storage address segment. As shown in Figure 2, taking the asynchronous clock domain as an example, under the premise that the clocks of clock domain 1 and clock domain 2 are different, the read and write commands received by the general protocol interface (bus interface) are parsed through the general protocol read and write state machine 22 , chip select information and read and write data. Put the write data into the asynchronous write FIFO 25, write the read and write commands, chip select information and address information into the instruction FIFO, and read the read data from the asynchronous read FIFO 24 according to the empty and full status of the read FIFO 24. Finally, the cache access state machine 23 extracts information from the three FIFOs according to the SRAM interface requirements and its own clock domain. Finally, the transformation from a general protocol interface to a storage SRAM interface was completed.

The general interface register system proposed in this application supports synchronous processing and also supports asynchronous cross-clock domain processing. Synchronization means that one end of the general protocol and other modules, that is, user-defined functional modules, are in the same clock domain. That is, clock domain 1 and clock domain 2 in the figure are the same clock domain. At this time, the protocol bridge is a synchronous bridge, and the three FIFOs used are synchronous FIFOs. Asynchronous processing means that one end of the general protocol and other modules are in different clock domains (the clock frequencies of clock domain 1 and clock domain 2 are different). At this time, the protocol bridge is an asynchronous bridge, and the three FIFOs used are asynchronous FIFOs. Asynchronous bridges are compatible with synchronous circuits.

In some embodiments of this application, the protocol bridge module can be specifically divided into a general protocol read and write state machine 22, an asynchronous read FIFO 24, an asynchronous instruction FIFO 25, an asynchronous write FIFO 26, and a cache module access state machine 23. As shown in Figure 2, the general protocol read and write state machine is located in the time domain of the bus protocol. The asynchronous read FIFO 24, the asynchronous instruction FIFO 25, and the asynchronous write FIFO 26 are between the time domain of the bus protocol and the time domain of the general interface register system. The cache access state machine 23 is located in the time domain using the interface register system. In some cases, because the clock specified by the bus protocol and the clock frequency of the interface register system are different, clock domain 1 and clock domain 2 in Figure 2 are not the same in many cases.

Therefore, this application uses asynchronous FIFO as the data connection structure between the universal protocol read-write state machine and the cache access state machine to meet the versatility of the interface register system proposed in this application.

Another aspect of this application also proposes a method for quickly generating the universal interface register system in the above embodiment, as shown in Figure 9. The method includes:

Step S1: Configure functional modules and register parameters according to the requirements of the corresponding interface;

Step S2: Design the hardware circuit of the general interface register system into a template design file;

Step S3: Activate the corresponding modules in the template design file and generate the final design file according to the functional module and register parameters and the configuration parameters of each module in the general interface register system in the configuration file.

In some implementations of this application, configuring functional modules and register parameters according to the requirements of the corresponding interface includes:

Select the corresponding general protocol to read and write state machine logic according to the bus protocol connected to the interface in the required configuration;

Configure the type and number of registers in the general register module and custom register module according to the register parameters.

In some embodiments of this application, this application proposes the general interface register system as before, and designs the above system into a design template of RTL language, and marks each module in the above system, and sets the corresponding according to the mark. Configure parameters. If a corresponding module is required, set the parameter of the corresponding tag of the module to True or Yes.

In addition, for general register modules and custom register modules, the specifications of the register module and custom register module are determined according to the area of the above system in the SOC chip, and then tailored according to the specifications of the corresponding needs. For example, if certain general registers are not required, they can be directly Set the corresponding register mark position to No. If you do not need the interrupt module, you can set the corresponding configuration parameter to No.

It should be noted that in the above system, the presence or absence of any module can be configured through the configuration file. The number and specifications of the registers in the general register module and custom register module in the register module need to be specified in the configuration file. The depth and bit width of TxFIFO, RXFIFO, and asynchronous FIFO can be specified according to the actual needs of the interface.

In some embodiments of this application, the register type and its domain are defined by filling in parameters in the form (configuration file). (Since the internal integration has been completed, the user's own implemented module is combined with the tool-generated register module. Integration) and then call the script to extract the parameters in the table and fill them into the corresponding hardware logic template and register list template. During this process, the script will also check whether the parameters in the table are correctly defined. If an error occurs, it will not be correct. A register list and its corresponding register logic are generated and an error is reported at the same time. After the user corrects the errors in the form, the parameters in the form can be extracted through a script and filled in the register logic template and register list template to obtain the correct register. Interface logic and register list.

Secondly, some common modules can be integrated internally, which not only increases the reusability of the modules, but also avoids the problem of logical errors in the written code. You can choose whether to generate some of the common modules by configuring the corresponding parameters.

Through a general interface register system proposed in this application, multiple bus protocols are connected through a protocol bridge and the data on the bus is parsed, and the data parsed from the bus is cached through each module in the cache module to realize the internal logic of the ASIC chip or SOC chip. Universal interface to the bus. At the same time, the above system is integrated into a universal template, and each module in the universal interface register system is marked. The universal template is cut according to the corresponding marked parameters in the configuration file and the corresponding register interface circuit design file is generated. The design of the interface circuit between each module can be quickly realized in the SOC chip, just add the SOC The bus types connected to different modules in the chip and the types and numbers of various registers required for functional requirements are written into the configuration file and can be generated based on the general template.

The above are exemplary embodiments disclosed in the present application, but it should be noted that various changes and modifications can be made without departing from the scope disclosed in some embodiments of the present application as defined by the claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements disclosed in some embodiments of the present application may be described or claimed individually, they may also be understood as plural unless expressly limited to the singular.

It will be understood that, as used herein, the singular form "a" and "an" are intended to include the plural form as well, unless the context clearly supports an exception. It will also be understood that as used herein, "and/or" is meant to include any and all possible combinations of one or more of the associated listed items.

The embodiment numbers disclosed in some embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware, or can be completed by instructing the relevant hardware through a program. The program can be stored in a computer-readable storage medium. The above-mentioned The storage medium can be read-only memory, magnetic disk or optical disk, etc.

Those of ordinary skill in the art should understand that the above discussion of any embodiments is only illustrative and is not intended to imply that the scope (including the claims) disclosed in some embodiments of the present application is limited to these examples; in some embodiments of the present application, Under the idea, the above embodiments or technical features in different embodiments can also be combined, and there are many other changes in different aspects of some embodiments of the present application as mentioned above. For the sake of simplicity, they are not provided in details. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of some embodiments of this application shall be included in the protection scope of some embodiments of this application.

Claims (20)

A general interface register system, characterized by including a protocol bridge module and a cache module, wherein: The protocol bridge module is configured to parse the bus data on the bus into instructions or instructions and data used in the universal interface register system based on the bus protocol based on the bus connected to the universal interface register system; and send the instruction or the instruction and data to the cache module; The cache module is configured to receive the instruction or the instruction and data, read data from the cache module according to the instruction or the instruction and data and send it to the protocol bridge module or according to the instruction and data Cache the data to the cache module. The system according to claim 1, characterized in that the cache module includes an address decoding module and a register module, wherein: The register module includes a general register module and a custom register module, and the register module is configured to cache data received by the general interface register system; The address decoding module is configured to receive the instruction or the instruction and data from the protocol bridge module and decode the instruction address or the instruction address in the instruction and data, and convert the decoded The instruction or the instruction and data are sent to the register module of the corresponding type in the register module; and The decoded instructions or the instructions and data are sent to the memory. The system according to claim 2, wherein the address decoding module includes address decoding logic, and the address decoding logic is configured to perform address decoding on the input read and write address to obtain a chip select signal. The system according to claim 3, wherein the chip select signal includes a chip select signal of the general register module, a chip select signal of the custom register module and a Memory chip select signal. The system according to claim 4, characterized in that: When the chip select signal of the general register module is 1, the address decoding module is configured to send the decoded instruction or the instruction and data to the general register module in the register module; When the chip select signal of the custom register module is 1, the address decoding module is configured to send the decoded instruction or the instruction and data to the custom register in the register module module; When the Memory chip select signal is 1, the address decoding module is configured to send the decoded instruction or the instruction and data to the memory. The system according to claim 2, characterized in that the general register module includes general register logic and general register information files, wherein: The general register logic configuration is used to compare instructions and/or data received by the general register module with all register information file addresses in the general register information file, and select the general register that satisfies the comparison. register and write data to the general register or read data from the general register; The general register information file is configured to save the information and addresses of all general registers of the general register module and provide matching mapping for all registers in the general register module. The system according to claim 6, wherein the general register information at least includes a general register type and a reset value. The system according to claim 2, characterized in that the custom register module includes custom register logic and a custom register information file, wherein: The custom register logic configuration is used to compare the instructions and/or data received by the custom register module with all register information file addresses in the custom register information file, and select the custom register that satisfies the comparison. And write data to the custom register or read data from the general register; The custom register information file is configured to save the information and addresses of all custom registers in the custom register module and provide matching mapping for all registers in the custom register module. The system according to claim 8, characterized in that the information of the custom register at least includes a custom register type, a reset value and an invalid bit. The system according to claim 2, characterized in that the cache module further includes: RxFIFO module, the RxFIFO module is configured to receive data sent from the protocol bus through the protocol bridge module; TxFIFO module, the TxFIFO module is configured to receive data sent from the protocol bus through the protocol bridge module. The system according to claim 10, characterized in that both the RxFIFO module and the TxFIFO module have a DMA function. The system according to claim 10, characterized in that the RxFIFO module and the TxFIFO module support Single transmission, Burst transmission and Packet transmission. The system according to claim 2, characterized in that the cache module further includes: An interrupt module configured to monitor exceptions in the general interface register system in real time, and write corresponding exceptions to the corresponding exception registers in the general register module, and based on The logical AND operation of the enable status register corresponding to the exception and the value of the exception register generates a corresponding interrupt signal. The system according to claim 2, characterized in that the cache module further includes a clock reset module, the clock reset module includes a clock gating module and an asynchronous reset and synchronous release module, wherein: The clock gating module is configured to control the timing of one or more general registers in the general register module. clock for control; The asynchronous reset synchronous release module is configured to synchronously release the general interface register system and the protocol bus after asynchronous reset. The system according to claim 1, characterized in that the protocol bridge module includes a general protocol read and write state machine, an asynchronous read FIFO, an asynchronous instruction FIFO, an asynchronous write FIFO, and a cache module access state machine, wherein: The universal protocol read-write state machine is configured to parse instructions or instructions and data on the protocol bus received by the protocol bridge module, send the instructions to the asynchronous instruction FIFO, and send the data to the asynchronous Write FIFO or read data from the asynchronous read FIFO, encapsulate it into transmission data on the protocol bus and send it to the protocol bus; The cache module access state machine is configured to read the instruction from the asynchronous instruction FIFO or read the instruction and data from the asynchronous instruction FIFO and the asynchronous write FIFO, and store the instruction Or the instructions and data are sent to the cache module, and the data obtained from the cache module is sent to the asynchronous read FIFO. The system according to claim 1, characterized in that the protocol bridge module is connected to the CPU through a connected bus. The system according to claim 16, wherein the CPU is a CPU in a SOC chip or an independent CPU outside the SOC chip. The system according to claim 16, wherein the bus data at least includes an address, a chip select signal and read and write data sent by the CPU. A method for quickly generating a universal interface register system according to any one of the above claims 1-18, characterized in that it includes: Configure function modules and register parameters according to the requirements of the corresponding interface; Design the hardware circuit of the general interface register system into a template design file; Activate corresponding modules in the template design file and generate a final design file according to the functional modules and the register parameters as well as the configuration parameters in the configuration file regarding each module in the general interface register system. The method according to claim 19, characterized in that configuring functional modules and register parameters according to the requirements of the corresponding interface includes: Select the corresponding universal protocol to read and write state machine logic according to the bus protocol connected to the interface in the required configuration; Configure the type and number of registers in the general register module and the custom register module according to the register parameters.