CN111651384B - Register reading and writing method, chip, subsystem, register set and terminal - Google Patents

Abstract

The embodiment of the application discloses a register read-write method, a chip, a subsystem, a register set and a terminal, which belong to the technical field of register read-write, in the application, a central control module receives target identification information and corresponding target commands sent by a central processing unit in parallel, the central control module converts the information into serial data, the serial data is broadcast to at least two register sets which are controlled, the target commands are executed by the register set corresponding to the target identification information in the at least two register sets, the CPU is converted into serial data by adding the central control module, the register sets are connected to the central control module by signal wires when the register sets are added, the register sets and the signal wires are correspondingly removed when the register sets are reduced, the connection mode of all the register sets, a bus and the CPU does not need to be redesigned like before, and the design difficulty of the register sets is reduced.

Description

Register reading and writing method, chip, subsystem, register set and terminal

technical field

The embodiments of the present application relate to the technical field of register reading and writing, and in particular to a method for reading and writing registers, a chip, a subsystem, a register set, and a terminal.

Background technique

In the field of SoC (System on Chip, system-on-chip) design, in order to realize various specified functions, multiple subsystems are usually designed on one chip, and each subsystem usually includes several register groups. The central processing unit (CPU) accesses various internal subsystems through the bus (bus).

In the related art, when the central processing unit needs to access the subsystem, it sends data to the subsystem in parallel, and the subsystem decodes it through the bus. When the decoding of the bus is completed, the register group can identify the decoded information, so as to read and write the information.

Contents of the invention

Embodiments of the present application provide a method for reading and writing registers, a chip, a subsystem, a register set, and a terminal. Described technical scheme is as follows:

According to one aspect of the present application, a register reading and writing method is provided, which is applied in a chip, and the chip includes a central processing unit, a central control module and a subsystem, and the subsystem includes at least two register groups, the The central control module is arranged between the central processor and the subsystem, and the central control module is used to control the data interaction between the central processor and the subsystem, and the method includes:

The central control module receives target identification information and corresponding target commands sent by the central processor in parallel;

The central control module converts the target identification information and the corresponding target command into serial data, wherein in the serial data, the target identification information is located before the target command;

The central control module broadcasts target identification information and corresponding target commands to the register groups in the controlled subsystem in a serial manner;

The first register group in the subsystem executes the target command, the target command is used to instruct the register group to write the first data, or is used to instruct the register group to output the saved second data, the The first register group is a register group corresponding to the target identification information among the at least two register groups.

According to another aspect of the present application, a register reading and writing method is provided, which is applied in a subsystem, the subsystem includes at least two register groups, and the method includes:

The register group in the subsystem receives target identification information in a serial manner, and the target identification information is the identification of the register group broadcast by the central control module, and the central control module is arranged between the central processing unit and the register group time, and the central control module is used to control the data interaction between the central processing unit and the register;

The register group in the subsystem receives a target command in a serial manner, and the target command is used to instruct the register group to write the first data, or to instruct the register group to output the saved second data, In the serial data, the target identification information is located before the target command;

The first register group in the subsystem executes the target command, and the identifier of the first register group matches the target identification information;

The second register set in the subsystem does not respond to the target command, and the identification of the second register set does not match the target identification information.

According to another aspect of the present application, a method for reading and writing a register is provided, which is applied to a register set, and the method includes:

The target identification information is received in a serial manner, the target identification information is the identification of the register group broadcast by the central control module, the central control module is arranged between the central processing unit and the register group, and the central control module for controlling data interaction between the central processing unit and the register set;

receiving a target command in a serial manner, where the target command is used to instruct the register bank to write the first data, or to instruct the register bank to output the saved second data;

When the target identification information matches the register set identification, execute the target command.

According to another aspect of the present application, a chip is provided, the chip includes a central processing unit, a central control module, and a subsystem, the subsystem includes at least two register groups, and the central control module is set in the central between the processor and the subsystem, and the central control module is used to control the data interaction between the central processor and the subsystem,

The central control module is configured to receive the target identification information and the corresponding target command sent by the central processor in parallel;

The central control module is configured to convert the target identification information and the corresponding target command into serial data, wherein, in the serial data, the target identification information is located before the target command ;

The central control module is configured to serially broadcast target identification information and corresponding target commands to at least two controlled register groups;

The first register group in the subsystem executes the target command, the target command is used to instruct the register group to write the first data, or is used to instruct the register group to output the saved second data, the The first register group is a register group corresponding to the target identification information among the at least two register groups.

According to another aspect of the present application, a subsystem is provided, the chip includes at least two register groups:

The register group in the subsystem receives target identification information in a serial manner, and the target identification information is the identification of the register group broadcast by the central control module, and the central control module is arranged between the central processing unit and the register group time, and the central control module is used to control the data interaction between the central processing unit and the register set;

The register group in the subsystem receives a target command in a serial manner, and the target command is used to instruct the register group to write the first data, or to instruct the register group to output the saved second data, In the serial data, the target identification information is located before the target command;

The first register group in the subsystem is used to execute the target command, and the identifier of the first register group matches the target identification information;

The second register set in the subsystem does not respond to the target command, and the identification of the second register set does not match the target identification information.

According to another aspect of the present application, a register set is provided, the register set is used to receive target identification information in a serial manner, and the target identification information is the identification of the register set broadcast by the central control module, the The central control module is arranged between the central processor and the register set, and the central control module is used to control the data interaction between the central processor and the register set;

receiving a target command in a serial manner, where the target command is used to instruct the register bank to write the first data, or to instruct the register bank to output the saved second data;

When the target identification information matches the register set identification, execute the target command.

According to another aspect of the present application, a terminal is provided, and the terminal includes the chip provided in the embodiment of the present application.

According to another aspect of the present application, the embodiment of the present application also provides a computer program product, the computer program product stores at least one instruction, and the at least one instruction is loaded and executed by a processor to implement the program described in the embodiment of the present application. Read and write methods for the provided registers.

The register reading and writing method provided by this application is applied to the chip. The chip includes a central control module and a register group. The central control module receives the target identification information and the corresponding target command sent by the central processor in parallel, and the central control module converts the above information. It is serial data. In the serial data, the target identification information is located before the target command. The central control module broadcasts the above information in a serial manner to at least two controlled register groups. The corresponding target in at least two register groups The register group of identification information executes the target command, and realizes the information interaction between the register group and the central processing unit without the help of the bus system. By adding a central control module, the data sent by the CPU in parallel is converted into serial In the following way, when increasing the register group, the register group can be connected to the central control module through the signal line. When the register group is reduced, the register group and the signal line can be removed correspondingly. It is not necessary to redesign all the register groups and buses as in the past. , The connection mode of the CPU reduces the design difficulty of adding or reducing the register set in the chip design.

Description of drawings

In order to more clearly introduce the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments of the present application will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present application , for those skilled in the art, other drawings can also be obtained based on these drawings without creative work.

FIG. 1 is a structural block diagram of a terminal provided in an exemplary embodiment of the present application;

FIG. 2 is a schematic diagram of a register access architecture based on a standard bus;

FIG. 3 is a schematic diagram of a register access architecture provided by an exemplary embodiment of the present application;

FIG. 4 is a schematic diagram of a register access architecture provided by an exemplary embodiment of the present application;

FIG. 5 is a schematic diagram of a register access architecture provided by an exemplary embodiment of the present application;

FIG. 6 is a flow chart of a register reading and writing method provided by an exemplary embodiment of the present application;

FIG. 7 is a schematic diagram of a finite state machine of a register bank provided by an embodiment of the present application;

FIG. 8 is a flow chart of a register reading and writing method provided by an exemplary embodiment of the present application;

FIG. 9 is a schematic diagram of a finite state machine of a central control module provided by an embodiment of the present application;

FIG. 10 is a flow chart of a register reading and writing method provided by another exemplary embodiment of the present application;

FIG. 11 is a flow chart of a register reading and writing method provided by another exemplary embodiment of the present application;

FIG. 12 is a schematic diagram based on the timing sequence of a register bank write serial signal shown in FIG. 4;

FIG. 13 is a schematic diagram based on the timing sequence of serially reading data from the register set shown in FIG. 4 .

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the implementation manners of the present application will be further described in detail below in conjunction with the accompanying drawings.

When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with aspects of the present application as recited in the appended claims.

In the description of the present application, it should be understood that the terms "first", "second" and so on are used for descriptive purposes only, and should not be understood as indicating or implying relative importance. In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integrated Ground connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application in specific situations. In addition, in the description of the present application, unless otherwise specified, "plurality" means two or more. "And/or" describes the association relationship of associated objects, which means that there can be three kinds of relationships, for example, A and/or B, can mean: A exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the contextual objects are an "or" relationship.

In order to make the solutions shown in the embodiments of the present application easy to understand, several terms appearing in the embodiments of the present application are introduced below.

Serial way: In a signal line, data is transmitted from the central control module to the register group through a queue. For example, the data "010101" will be transferred one by one in the signal line from the central control module to the register bank.

Target identification information: this information is the identification of the register group broadcast by the central control module. In a possible implementation manner, the target identification information includes target keywords and identification data. For example, if the target information is "111+010", it means that the target keyword is "111" and the identification data is "010". In this application, target keywords with different values are used to represent different keywords. When the value of the target key is "111", it means that the target key is a target key, and the identifier of the register is "010".

Target command: includes two functions of reading data and writing data. When the target command is used to read data from the register bank, the command is used to instruct the register bank to output the saved second data. When the target command is used to write data into the register group, the command is used to instruct the first data to be written into the register group.

Optionally, the target command includes command keywords. Optionally, the command keywords include write keywords and read keywords. When the command keyword is the write keyword, the type of the target command is the write type. When the command keyword is a read keyword, the type of the target command is a read type.

Optionally, when the type of the target command is a write type, the target command includes a write keyword and the first data. The register set can determine the data to be stored in the register set itself according to the write keyword, that is, the first data, and then store the first data in the register set.

Optionally, when the type of the target command is a read type, the target command includes a read keyword and the second data. The register set can know that it needs to output the second data to the outside according to the read keyword, and then the register set will output the second data to the outside.

Exemplarily, the register reading and writing method shown in the embodiment of the present application can be applied in a terminal, the terminal includes the chip shown in the embodiment of the present application, and the chip shown in the embodiment of the present application includes a register group . Optionally, the terminals include mobile phones, tablet computers, laptop computers, desktop computers, all-in-one computers, servers, workstations, TVs, set-top boxes, smart glasses, smart watches, digital cameras, MP4 playback terminals, MP5 playback terminals, learning machines , point reader, electronic paper book, electronic dictionary, vehicle-mounted terminal, virtual reality (Virtual Reality, VR) playback terminal or augmented reality (Augmented Reality, AR) playback terminal, etc.

On the other hand, the embodiment of the present application can also be applied in a chip, and the chip can be applied in the above-mentioned terminal.

Please refer to FIG. 1. FIG. 1 is a structural block diagram of a terminal provided by an exemplary embodiment of the present application. As shown in FIG. The control module 180, at least one instruction is stored in the memory 140, and the instruction is loaded and executed by the processor 120 to implement the methods for reading and writing registers as described in various method embodiments of the present application. Optionally, processor 120 is a central processing unit. The chip 100 includes a central processor, a central control module 180 and a subsystem 160, the central control module 180 is arranged between the central processor and the subsystem 160, and the central control module 180 is used to control the data interaction between the central processor and the subsystem 160 .

Processor 120 can include one or more processing cores. The processor 120 uses various interfaces and lines to connect various parts of the entire terminal 100, and executes the terminal by running or executing instructions, programs, code sets or instruction sets stored in the memory 140, and calling data stored in the memory 140. 100's of various functions and processing data. Optionally, the processor 120 can use at least one of Digital Signal Processing (Digital Signal Processing, DSP), Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA), and Programmable Logic Array (Programmable LogicArray, PLA). implemented in the form of hardware. The processor 120 may integrate one or a combination of a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), a modem, and the like. Among them, the CPU mainly handles the operating system, user interface and application programs, etc.; the GPU is used to render and draw the content that needs to be displayed on the display screen; the modem is used to handle wireless communication. It can be understood that, the above-mentioned modem may also not be integrated into the processor 120, but may be realized by a single chip.

The memory 140 can include random access memory (Random Access Memory, RAM), and can also include read-only memory (Read-Only Memory, ROM). Optionally, the memory 140 includes a non-transitory computer-readable storage medium (non-transitory computer-readable storage medium). The memory 140 may be used to store instructions, programs, codes, sets of codes or sets of instructions. The memory 140 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), Instructions and the like for implementing the following method embodiments; the storage data area can store data and the like involved in the following method embodiments.

The subsystem 160 can be installed outside the processor. Optionally, the central control module 180 is arranged between the processor and the subsystems, and is used to control the data interaction between the central control module 180 and each subsystem, write data in the subsystems or read data from the subsystems. Schematically, the subsystem 160 may be implemented as a group of physical circuits. Subsystem 160 includes at least two register banks. For example, subsystem 160 includes register bank 161 and register bank 162 .

In this application, the chip 100 performs the following steps: the central control module receives the target identification information and the corresponding target command sent by the central processor in parallel; the central control module converts the target identification information and the corresponding target command into serial data, Among them, in the serial data, the target identification information is located before the target command; the central control module broadcasts the target identification information and the corresponding target command to at least two controlled register groups in a serial manner; the first register group executes the target The command, the target command is used to instruct the register group to write the first data, or to instruct the register group to output the saved second data, the first register group is the register group corresponding to the target identification information among the at least two register groups.

In this application, the subsystem 160 performs the following steps: the register group in the subsystem receives the target identification information in a serial manner, and the target identification information is the identification of the register group broadcast by the central control module; the subsystem The register group in the serial method receives the target command, the target command is used to instruct the register group to write the first data, or to instruct the register group to output the saved second data, in the serial In the data, the target identification information is located before the target command; the first register group is used to execute the target command, and the identification of the first register group matches the target identification information; the second register group does not respond to the target command the target command, the identifier of the second register set does not match the target identifier information.

In the present application, the register group 161 or the register group 162 performs the following steps: receive the target identification information in a serial manner, and the target identification information is the identification of the register group broadcast by the central control module, and the central control module is set in the central Between the processor and the register group, and the central control module is used to control the data interaction between the central processor and the register; receive a target command in a serial manner, and the target command is used to indicate The first data is written into the register group, or used to instruct the register group to output the stored second data; when the target identification information matches the identification of the register group, execute the target command.

Please refer to FIG. 2 , which is a schematic diagram of a register access architecture based on a standard bus. In FIG. 2 , the central processing unit 210 performs data interaction with various subsystems through the top-level bus 220 . In Fig. 2, there are 3 subsystems including subsystem 1, subsystem 2 and subsystem. Wherein, taking subsystem 1 as an example, the process of data interaction between the register set in subsystem 1 and the central processing unit is introduced.

When the central processing unit 210 needs to write data to the register group_2 in the subsystem 1, the central processing unit 210 adds the address of the register group_2 in the subsystem 1 to the head of the data to be written and sends it to the top layer The bus 220 and the top-level bus 220 transmit the data to the subsystem bus 231 , the subsystem bus 241 and the subsystem bus 251 respectively. Cooperate with each subsystem bus and standard bus to decode the data. When the decoded address of the register group_2 is the same as the address of the register group corresponding to the standard bus, the standard bus 2A writes data into the register group_2. Schematically, the number of cables of the standard bus is on the order of 10 ¹ , and the standard bus is relatively complicated. When a new subsystem or a new register group needs to be added to the chip, the workload of debugging the corresponding subsystem bus and standard bus increases, which makes the modular development of the chip more difficult. Optionally, the standard bus is AHB (Advanced High performance Bus, high performance cable), APB (Advanced Peripheral Bus, peripheral bus) or other cables capable of implementing bus functions.

In view of the limitations in the above-mentioned register reading and writing architecture, this application proposes a new register reading and writing architecture, also known as a register reading and writing control protocol, which is introduced as follows.

Please refer to FIG. 3 , which is a schematic diagram of a register access architecture provided by an exemplary embodiment of the present application. In FIG. 3 , the central processing unit 210 communicates with a central control module (center control) 310 through a bus 3A, and the central control module 310 communicates with subsystem 1 , subsystem 2 and subsystem k through a signal line 320 . It should be noted that the signal line 320 is a 1-bit cable. It should be noted that the arrows in FIG. 3 indicate the direction of data flow. In FIG. 3 , the central control module is arranged between the central processing unit and the register set, and the central control module is used to control data interaction between the central processing unit and the registers.

In another possible manner, the signal line 320 is a 2-bit cable. Please refer to FIG. 4, which is a schematic diagram of a register access architecture provided by an exemplary embodiment of the present application. Wherein, the 2-bit signal lines (lines) include a command (CMD) line 410 and a data (DAT) line 420 . Optionally, in FIG. 4, the command line 410 is bit [0], and the data line 420 is bit [1]. The structure shown in FIG. 4 is the read and write structure of the register group under the 2-bit serial control protocol. It should be noted that the arrows in FIG. 4 indicate the direction of data flow. Wherein, the data transmission direction of the command line 410 is one-way transmission from the central control module to the register bank. The data transmission direction of the data line 420 is bidirectional transmission between the central control module and the register set.

In another possible manner, the signal line 320 is a 3-bit cable. Please refer to FIG. 5, which is a schematic diagram of a register access architecture provided by an exemplary embodiment of the present application. Wherein, the 3-bit signal lines (lines) include a command (CMD) line 510 , a write data line 520 and an output data line 530 . It should be noted that the arrows in FIG. 5 indicate the direction of data flow. Wherein, the data transmission direction of the command line 510 is one-way transmission from the central control module to the register bank. The data transmission direction of the write data line 520 is one-way transmission from the central control module to the register bank. The data transmission direction of the output data line 530 is one-way transmission from the register set to the central control module.

Optionally, in the register sets shown in FIG. 3 to FIG. 5 , each register set shares the same reset and clock. That is, when the register sets need to be reset, all the register sets in any one of Figures 3 to 5 will be reset. At the same time, all register groups in any one of FIGS. 3 to 5 share the same clock.

Optionally, data interaction is performed between the register set and the central control module through a signal line, and the signal line is used for serially transmitting data.

Please refer to FIG. 6 . FIG. 6 is a flowchart of a method for reading and writing registers provided by an exemplary embodiment of the present application. The method for reading and writing the register can be applied to any of the chips shown in FIG. 1 , FIG. 3 to FIG. 5 . In Figure 6, the register reading and writing methods include:

Step 610, receiving target identification information in a serial manner, where the target identification information is the identification of the register set broadcast by the central control module.

In the embodiment of the present application, the register set can receive the target identification information in a serial manner. Wherein, the register group can obtain the target identification information broadcast by the central control module through any one of the architectures shown in FIG. 3 to FIG. 5 .

In the embodiment of the present application, the central control module is arranged between the central processing unit and the register set, and the central control module is used to control data interaction between the central processing unit and the registers.

Optionally, taking the architecture shown in FIG. 4 as an example, the register set will obtain the target key through the command line 410 and obtain the identification data through the data line 420 . Wherein, taking the register set as a slave as an example, the control protocol on the register set side is introduced.

It should be noted that, in the embodiment of the present application, the register set is designed as a component including N registers, and each register includes a storage space of M bits. In this application, the register set can read out all the N*M-bit data, or write the data to be written into the N*M-bit space. It should be noted that the values of N and M are positive integers, and both N and M are instantiation parameters, and the present application does not limit the specific values of N and M.

In Table 1, the data direction indicates the direction of data flow with the register bank as a reference point. For example, writing means writing data from the central control module to the register set, and reading means reading data from the register set. In the embodiment of the present application, when the data "111" appears in the command line, it means that the register identifier will be transmitted in the data line. At this time, the register set will read a k-bit long register set identifier from the data line. It should be noted that k is also an instantiation parameter.

Optionally, when the data "101" appears in the command line, it means that the data written in N*M bits will be transmitted in the data line.

Step 620: Receive a target command in a serial manner, the target command is used to instruct the register bank to write the first data, or is used to instruct the register bank to output the stored second data.

In the embodiment of the present application, the register group will receive the target command in a serial manner. Optionally, the register set includes a decoding module. The decoding module can receive the target identification information in a serial manner, and when the target identification information matches the identification of the register group, receive the target command.

Step 630, when the target identification information matches the register bank identification, execute the target command.

In the embodiment of the present application, optionally, the register group can write the data sent by the central control module into the entire register group when the target identification information matches the identification of the register group and the type of the target command is a write type. in storage space. Optionally, the register group can output all the data in the register group to the central control module when the target identification information matches the register group identification and the type of the target command is a read type.

Optionally, the method for reading and writing registers provided by the present application includes a finite state machine, which is introduced as follows.

Please refer to FIG. 7 . FIG. 7 is a schematic diagram of a finite state machine of a register bank provided by an embodiment of the present application. In FIG. 7 , the register group is in the idle state 710 and can receive k-bit long data from the data line after receiving the data “111” from the command line (that is, step 720 ). When the register group does not match (that is, ID_match='0') at the data of the k-bit length and the register group, continue to change to the idle state. When the k-bit-long data of the register group matches the register group's identifier (ie, ID_match='1'), execute receiving the target command (ie, step 730). Subsequently, when the data "101" is received from the command line, enter the write data state (that is, step 740), write N*M bit data into the register group, and then enter the idle state. On the other hand, when data "110" is received from the command line, it enters the read data state, takes out the N*M bit data in the register set (that is, step 750), and then enters the idle state.

To sum up, in the method for reading and writing registers provided by this embodiment, the register group receives target identification information in a serial manner, and the target identification information is the identification of the register group broadcast by the central control module, and receives target identification information in a serial manner. A command, the target command is used to instruct the register bank to write the first data, or is used to instruct the register bank to output the saved second data, and when the target identification information matches the register bank identification, the target command is executed. Since the application can make the register group receive the identifier broadcast by the central control module in a serial manner, and receive and execute the read and write commands in a serial manner when the identifier matches, and convert the data sent by the CPU in a parallel manner into a serial manner , when increasing the register group, the register group can be connected to the central control module through the signal line. Or reduce the design difficulty of the register set.

Optionally, since the present application provides a signal line as a connection between the central control module and the register bank, the embodiment of the present application can also effectively reduce the excessive bus bit width caused by data transmission through the bus in the related art, The problem of bringing space pressure to the wiring work of the register set and increasing the complexity of the wiring design effectively reduces the difficulty of routing from the central control module to the register set.

Please refer to FIG. 8 . FIG. 8 is a flowchart of a method for reading and writing registers provided by an exemplary embodiment of the present application. The method for reading and writing the registers can be applied to any of the chips shown in FIG. 1 , FIG. 3 to FIG. 5 , and the chip includes a central control module and a register set. In Figure 8, the register reading and writing methods include:

Step 810, the central control module receives in parallel the target identification information and the corresponding target command sent by the central processor.

In the embodiment of the present application, the central control module receives the data sent by the central processor in a parallel manner. Correspondingly, when the central processing unit needs to write data into or read data from the register group, the central processing unit will send the target identification information and the target command corresponding to the target identification information to the central control module in parallel.

Step 820, the central control module converts the target identification information and the corresponding target command into serial data, wherein in the serial data, the target identification information is located before the target command.

In the embodiment of the present application, the central control module has a data conversion function, and can convert data received in parallel into serial data. In the serial data converted by the central control module, the target identification information is located before the target command.

Step 830, the central control module serially broadcasts the target identification information and the corresponding target command to the register groups in the controlled subsystems.

Schematically, if the central control module controls m register groups, the central control module can broadcast target identification information and corresponding target commands to the above m register groups in a serial manner. It should be noted that the m register groups may respectively belong to several subsystems. Wherein, a subsystem includes at least two register groups.

Step 840, the first register group in the subsystem executes the target command, the target command is used to instruct the register group to write the first data, or is used to instruct the register group to output the saved second data, the first register group is at least two The register bank corresponding to the target identification information in the register bank.

Please refer to FIG. 9 . FIG. 9 is a schematic diagram of a finite state machine of a central control module provided by an embodiment of the present application. In Fig. 9, the central control module starts in the idle state 910, and broadcasts the target keyword to the controlled register group, that is, transmits data "111" from the command line (that is, executes step 920); subsequently, sends k from the data line bit-length data (that is, execute step 930); then broadcast the target command to the controlled register group (that is, execute step 940). When the data sent from the command line is "101", the central control module writes N*M bits of data into the register bank from the data line (that is, executes step 950). When the data sent from the command line is "110", the central control module reads the N*M-bit data obtained from the register set from the data line (that is, executes step 960). When step 950 or step 960 is executed, the central control module returns to the idle state.

In summary, the method for reading and writing registers provided by this application is applied to the chip. The chip includes a central control module and a register group. The central control module receives the target identification information and the corresponding target command sent by the central processor in parallel. The central control The module converts the above information into serial data. In the serial data, the target identification information is located before the target command, and the central control module broadcasts the above information to at least two controlled register groups in a serial manner. At least two The register group corresponding to the target identification information in the register group executes the target command, and realizes the information interaction between the register group and the central processing unit without the help of the bus system. By adding a central control module, the CPU sends out in parallel The data is converted into a serial mode, and the register set is connected to the central control module through the signal line when adding the register set, and the register set and the signal line are removed correspondingly when the register set is reduced, without redesigning as in the past The connection mode of all the register groups with the bus and the CPU reduces the design difficulty of adding or reducing the register groups in the chip design.

Optionally, because the embodiment of the present application can also identify the register set through the identification of the register set, instead of identifying the register set through address decoding in the related art, and the identification of the register set is more important than the data volume of the address. Small. Therefore, the embodiment of the present application reduces the difficulty for the central processing unit to find the corresponding register set, thereby improving the efficiency of reading and writing data from the corresponding register set.

Optionally, since the embodiment of the present application designs a simple signal line between the register set and the central control module, the logic complexity of the decoding work of the register set is reduced, and the design difficulty of adding a new register set to the chip is greatly reduced.

Optionally, since the central control module in the embodiment of the present application performs unified reading and writing management on the data of the controlled register group, and performs data conversion between parallel and serial, the central processing unit reads and writes the system It is easier to download the data in the register bank.

Optionally, due to the solution provided by the embodiment of the present application, a logic-simple data read-write standard is designed between the central control module and the register group. Therefore, the embodiment of the present application also helps to make statically controlled chips or chips with complex bus interfaces and expensive chips, or chips that require a unified central control module to control all register groups to achieve special functions to achieve higher data reading. Write efficiency, and reduce the difficulty of chip development when adding or subtracting register groups.

The embodiment of the present application can also provide a method for reading and writing registers applied in a subsystem. Please refer to FIG. 10 . FIG. 10 is a flowchart of a method for reading and writing a register provided by another exemplary embodiment of the present application. In Figure 10, the read and write methods of this register include:

In step 1001, the register group in the subsystem receives target identification information in a serial manner.

Wherein, the target identification information is the identification of the register group broadcast by the central control module, the central control module is arranged between the central processing unit and the register group, and the central control module is used to control the data interaction between the central processing unit and the registers.

Schematically, each register group in the subsystem receives the target identification information in a serial manner. For example, if the subsystem and the central control module are connected in the manner shown in FIG. 3 , take subsystem 2 as an example. Register set_1, register set_2 and register set_3 in subsystem 2 can all receive target identification information through signal lines.

Step 1002, the register set in the subsystem receives the target command in a serial manner.

Wherein, the target command is used to instruct the register bank to write the first data, or to instruct the register bank to output the stored second data, and in the serial data, the target identification information is located before the target command.

Schematically, the register group will receive the target command after receiving the target identification information. The register bank in the subsystem receives serial data in which the target identification information precedes the target command.

Step 1003, the first register group in the subsystem executes the target command, and the identifier of the first register group matches the target identification information.

Step 1004, the second register set in the subsystem does not respond to the target command, and the identifier of the second register set does not match the target identifier information.

Optionally, after the register set receives the target identification information and the target command, the register set compares whether its own identification matches the target identification information. In the subsystem, the register group whose own identification matches the target identification information is the first register group. The register set whose own identification does not match the target identification information is the second register set.

Furthermore, the first set of registers and the second set of registers in the subsystem will react differently to the target command. Wherein, the first register group in the subsystem will execute the target command, and the second register group will not respond to the target command.

To sum up, the register reading and writing method performed by the subsystem disclosed in the embodiment of the present application can enable the register set to be connected to the central control module through the signal line when adding the register set in the subsystem, and remove the corresponding register set when reducing the register set Register sets and signal lines are all that is needed, and there is no need to redesign the connection methods of all register sets, buses, and CPUs, which reduces the design difficulty of adding or reducing register sets for subsystems in chip design, and improves the overall new subsystem. Or reduce the difficulty of the subsystem.

The embodiment of the present application can also provide a method for reading and writing registers in which the register group and the central control module participate simultaneously, which is introduced as follows.

Please refer to FIG. 11 . FIG. 11 is a flowchart of a method for reading and writing registers provided by another exemplary embodiment of the present application. The method for reading and writing the register can be applied to any of the chips shown in FIG. 1 , FIG. 3 to FIG. 5 . In Figure 11, the read and write methods of this register include:

Step 1011, the central control module broadcasts the target keyword to the controlled register group within the first time period.

Wherein, the target keyword is used to indicate that the data sent in the second period represents the identifier of the designated register bank, that is, the content of the data sent in the second period can be determined to be the identifier corresponding to a certain register bank through the target keyword.

Correspondingly, the register group instructs the decoding module to receive the target keyword in the first period, and the target keyword is used to indicate the meaning represented by the data received in the second period. For example, in one possible manner, the target keyword is "001", which is used to indicate that the data received in the second period represents identification data, that is, the data received in the second period represents the ID of the register bank.

Step 1012, the central control module broadcasts the identification data to the controlled register groups within the second time period.

Among them, the target keyword and identification data belong to the target identification information.

Correspondingly, the register set receives the identification data within the second period, and the target keyword and the identification data belong to the target identification information. Schematically, the end moment of the first period is earlier than or equal to the start moment of the second period.

Step 1013, the central control module broadcasts the command keyword to the controlled register group within the third time period.

Wherein, the command keyword is used to indicate the type of the target command, and the type of the target command includes one of a read type or a write type.

Correspondingly, in the third period of time, when the identification data of the register group matches the identification of the register group, the decoding module is instructed to receive the command keyword, the command keyword is used to indicate the type of the target command, and the type of the target command includes the read type or one of the write types.

In a possible embodiment, when the identification data does not match the identification of the register set, the decoding module will no longer receive subsequent command keywords. Or, the decoding module no longer decodes and recognizes the subsequently received operation keys.

Step 1014, the central control module broadcasts or reads corresponding data according to the type of the target command within the fourth time period.

Correspondingly, in the fourth time period, the register group transmits data to the central control module or receives and reads data sent by the central control module according to the type of the target command.

Schematically, the end moment of the first period is earlier than or equal to the start moment of the second period, the end moment of the second period is earlier than or equal to the start moment of the third period, and the end moment of the third period is earlier than or equal to the fourth period The start moment of the period.

In the embodiment of the present application, the central control module may also implement the function of writing or reading data by performing step (1) or step (2).

Step (1), in the fourth period, when the type of the target command is write type, the central control module broadcasts the first data to the controlled register group.

Correspondingly, in the fourth period, when the type of the target command is a write type, the register bank stores the first data.

Step (2), in the fourth period, when the type of the target command is the read type, the central control module reads the second data from the register set corresponding to the target identification information.

Correspondingly, in the fourth period, when the type of the target command is a read type, the second data is output to the central control module.

In a possible implementation manner, the architecture shown in FIG. 4 is taken as an example. The central control module interacts with the register group through command lines and data lines. Please refer to FIG. 12 . FIG. 12 is a schematic diagram of a sequence of serial signals for register group writing based on FIG. 4 . The command line 410 serially transmits the target keyword "111" for the first period 11A. The data line 420 serially transmits identification data "10100001" during the second period 11B. The command line 410 serially transmits the write keyword “101” in the third period 11C, which indicates writing data into the register set. The data line 420 serially transmits 128-bit data in the fourth period 11D.

In another possible implementation manner, the architecture shown in FIG. 4 is taken as an example. The central control module interacts with the register group through command lines and data lines. Please refer to FIG. 13 . FIG. 13 is a schematic diagram of a sequence of serially reading data from a register set based on FIG. 4 . The command line 410 serially transmits the target keyword "111" in the first period 11E. The data line 420 serially transmits identification data "10100001" in the second period 11F. The command line 410 serially transmits the read keyword “110” in the third period 11G, which means to serially read 128-bit data from the register set. The data line 420 serially transmits 128-bit data during the fourth period 11H.

To sum up, this embodiment can be applied to a chip. The chip includes a central control module and a register group. The central control module receives the target identification information and the corresponding target command sent by the central processor in parallel. The central control module converts the above information into For serial data, in the serial data, the target identification information is located before the target command, and the central control module broadcasts the above information in a serial manner to at least two controlled register groups, and the corresponding target identification in at least two register groups The information register group executes the target command, realizes the information interaction between the register group and the central processing unit without the help of the bus system, and converts the data sent by the CPU in parallel to serial mode by adding a central control module , when increasing the register group, the register group can be connected to the central control module through the signal line, and the register group and the signal line can be removed correspondingly when the register group is reduced, without the need to redesign all the register groups and buses, The CPU connection method reduces the design difficulty of adding or reducing register groups in chip design

The embodiment of the present application also provides a computer-readable medium, the computer-readable medium stores at least one instruction, and the at least one instruction is loaded and executed by the processor to realize the reading of the register as described in each of the above embodiments. write method.

The embodiment of the present application also provides a computer program product, the computer program product stores at least one instruction, and the at least one instruction is loaded and executed by a processor to implement the register reading and writing method provided by the embodiment of the present application.

The serial numbers of the above embodiments of the present application are for description only, and do not represent the advantages and disadvantages of the embodiments.

Those of ordinary skill in the art can understand that all or part of the steps for implementing the above embodiments can be completed by hardware, and can also be completed by instructing related hardware through a program. The program can be stored in a computer-readable storage medium. The above-mentioned The storage medium mentioned can be a read-only memory, a magnetic disk or an optical disk, and the like.

The above descriptions are only exemplary embodiments of the present application that can be realized, and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the Within the protection scope of this application.

Claims (10)

1. A method for reading and writing registers, characterized in that it is applied in a chip, and the chip includes a central processing unit, a central control module and a subsystem, and the subsystem includes at least two register groups, and the central control module sets Between the central processor and the subsystem, and the central control module is used to control the data interaction between the central processor and the subsystem, the method includes: The central control module receives in parallel the target identification information sent by the central processor and the target command corresponding to the target identification information; The central control module converts the target identification information and the target command into serial data, wherein, in the serial data, the target identification information is located before the target command; The central control module broadcasts the target identification information and the target command to the register group in the controlled subsystem in a serial manner; The first register group in the subsystem executes the target command, the target command is used to instruct the register group to write the first data, or is used to instruct the register group to output the saved second data, the The first register group is a register group corresponding to the target identification information among the at least two register groups. 2. The method according to claim 1, wherein the central control module broadcasts the target identification information and the target command in a serial manner to the register group in the controlled subsystem, include: In the first period, the central control module broadcasts a target keyword to the controlled register group, and the target keyword is used to indicate that the data sent in the second period represents the identification of the specified register group; During the second period, the central control module broadcasts identification data to the controlled register group, and the target keyword and the identification data belong to the target identification information; In the third period, the central control module broadcasts a command keyword to the controlled register group, the command keyword is used to indicate the type of the target command, and the type of the target command includes a read type or a write one of the types; In the fourth period, the central control module broadcasts or reads corresponding data according to the type of the target command; Wherein, the end time of the first time period is earlier than or equal to the start time of the second time period, the end time of the second time period is earlier than or equal to the start time of the third time period, and the time period of the third time period is The end time is earlier than or equal to the start time of the fourth period. 3. The method according to claim 2, wherein, within the fourth period, the central control module broadcasts or reads corresponding data according to the type of the target command, including: In the fourth period, when the type of the target command is the write type, the central control module broadcasts first data to the controlled register group; or, In the fourth period, when the type of the target command is the read type, the central control module reads the second data from the register set corresponding to the target identification information. 4. The method according to any one of claims 1 to 3, characterized in that, data interaction is performed between the register group and the central control module through a signal line, and the signal line is used for serial transmission of data. 5. A method for reading and writing registers, characterized in that it is applied in a subsystem, and the subsystem includes at least two register groups, and the method includes: The register group in the subsystem receives target identification information in a serial manner, and the target identification information is the identification of the register group broadcast by the central control module, and the central control module is arranged between the central processing unit and the register group time, and the central control module is used to control the data interaction between the central processing unit and the register set; The register group in the subsystem receives a target command in a serial manner, and the target command is used to instruct the register group to write the first data, or to instruct the register group to output the saved second data, In the serial data, the target identification information is located before the target command; The first register group in the subsystem executes the target command, and the identifier of the first register group matches the target identification information; The second register set in the subsystem does not respond to the target command, and the identification of the second register set does not match the target identification information. 6. A method for reading and writing registers, characterized in that it is applied in register banks, and the method comprises: The target identification information is received in a serial manner, the target identification information is the identification of the register group broadcast by the central control module, the central control module is arranged between the central processing unit and the register group, and the central control module for controlling data interaction between the central processing unit and the register set; receiving a target command in a serial manner, where the target command is used to instruct the register bank to write the first data, or to instruct the register bank to output the saved second data; When the target identification information matches the register set identification, execute the target command. 7. A kind of chip, it is characterized in that, described chip comprises central processing unit, central control module and subsystem, and described subsystem comprises at least two register groups, and described central control module is arranged on described central processing unit and described between subsystems, and the central control module is used to control the data interaction between the central processing unit and the subsystems, The central control module is configured to receive in parallel the target identification information sent by the central processor and the target command corresponding to the target identification information; The central control module is configured to convert the target identification information and the target command into serial data, wherein, in the serial data, the target identification information is located before the target command; The central control module is configured to serially broadcast the target identification information and the target command to the controlled register group in the subsystem; The first register group in the subsystem executes the target command, the target command is used to instruct the register group to write the first data, or is used to instruct the register group to output the saved second data, the The first register group is a register group corresponding to the target identification information among the at least two register groups. 8. A register subsystem, characterized in that the subsystem includes at least two register banks, The register group in the subsystem receives target identification information in a serial manner, and the target identification information is the identification of the register group broadcast by the central control module, and the central control module is arranged between the central processing unit and the register group time, and the central control module is used to control the data interaction between the central processing unit and the register set; The register group in the subsystem receives a target command in a serial manner, and the target command is used to instruct the register group to write the first data, or to instruct the register group to output the saved second data, In the serial data, the target identification information is located before the target command; The first register group in the subsystem is used to execute the target command, and the identifier of the first register group matches the target identification information; The second register set in the subsystem does not respond to the target command, and the identification of the second register set does not match the target identification information. 9. A register bank, characterized in that, the register bank is used for: The target identification information is received in a serial manner, the target identification information is the identification of the register group broadcast by the central control module, the central control module is arranged between the central processing unit and the register group, and the central control module for controlling data interaction between the central processing unit and the register set; receiving a target command in a serial manner, where the target command is used to instruct the register bank to write the first data, or to instruct the register bank to output the saved second data; When the target identification information matches the register set identification, execute the target command. 10. A terminal, characterized in that the terminal comprises the chip according to claim 7.

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