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WO2021208436A1 - 存储器及存储器的读写方法 - Google Patents

存储器及存储器的读写方法 Download PDF

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Publication number
WO2021208436A1
WO2021208436A1 PCT/CN2020/130383 CN2020130383W WO2021208436A1 WO 2021208436 A1 WO2021208436 A1 WO 2021208436A1 CN 2020130383 W CN2020130383 W CN 2020130383W WO 2021208436 A1 WO2021208436 A1 WO 2021208436A1
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WO
WIPO (PCT)
Prior art keywords
memory
source line
storage element
current
bit line
Prior art date
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Ceased
Application number
PCT/CN2020/130383
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English (en)
French (fr)
Inventor
吴保磊
吴玉雷
王晓光
平尔萱
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to EP20931052.3A priority Critical patent/EP4009325A4/en
Priority to US17/310,385 priority patent/US11875835B2/en
Publication of WO2021208436A1 publication Critical patent/WO2021208436A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1655—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1657—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1693—Timing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1697—Power supply circuits

Definitions

  • the present invention relates to the field of memory, in particular to a memory and a method for reading and writing the memory.
  • MRAM Magnetic Random Access Memory
  • MRAM Magnetic Random Access Memory
  • MRAM in the prior art has at least the following insurmountable problems: MRAM is prone to damage or degradation of the magnetic tunnel junction due to excessive writing current during use, thereby affecting the performance and reliability of the MRAM. There is an urgent need to propose a new memory to overcome the above-mentioned problems.
  • the purpose of the present invention is to provide a memory and a method for reading and writing the memory, which can prevent the MRAM from easily affecting the performance and reliability of the device due to excessive current during use, and has a larger memory integration density.
  • a memory including: a memory cell including a memory element; a source line electrically connected to a first end of the memory element; and the memory is configured to pass a first current and a second current The current changes the storage state of the storage element, the first current flows through the storage element, and the second current flows through the source line, but does not flow through the storage element.
  • bit line the memory cell further includes a first selection transistor configured to electrically connect the second end of the storage element and the second end of the storage element in response to a first control signal. Bit line.
  • it further includes: a write bit line; a second selection transistor configured to electrically connect the first end of the source line and the write bit in response to a second control signal String.
  • the first current flows from the bit line to the source line through the storage element when writing a 1, and flows from the source line to the bit line through the storage cell when writing a 0 .
  • the second current flows from the first end of the source line to the second end of the source line when writing 1 and flows from the second end of the source line to the second end when writing 0.
  • the first end of the source line is
  • a third selection transistor configured to transmit a high or low level signal to the second end of the source line in response to a third control signal.
  • the memory is further configured to use the bit line to provide a high level or a low voltage to the second end of the storage element when the second end of the storage element is electrically connected to the bit line. flat.
  • the memory is further configured to use the write bit line to provide the first end of the source line when the first end of the source line is electrically connected to the write bit line High or low level.
  • the memory is further configured to provide a high level or a low level to the second end of the source line.
  • a plurality of memory cells are included, and the first end of the memory element in each memory cell is connected to the source line.
  • the memory is configured to read data stored in the storage element through a third current, and the third current flows from the bit line through the storage element to the second end of the source line .
  • bit line is configured to be electrically connected to the second end of the storage element during reading and provide a high level for the second end of the storage element, and the second end of the source line It is configured as low level when reading.
  • the storage element includes a magnetic tunnel junction.
  • the magnetic tunnel junction includes: a free layer connected to the source line; a non-magnetic isolation layer provided on the upper surface of the free layer; and a fixed layer provided on the upper surface of the non-magnetic insulating layer;
  • the direction of the magnetic moment of the free layer is variable, and the direction of the magnetic moment of the pinned layer is fixed; the first selection transistor is connected to the pinned layer.
  • the memory includes a storage unit, the storage unit includes a storage element, and the memory is configured to change the storage through a first current and a second current.
  • the storage state of the element the memory further includes a source line, which is electrically connected to the first end of the storage element, and when writing to the memory, it includes: providing a first current to the memory; A second current; wherein the first current flows through the storage element, and the second current flows through the source line, but does not flow through the storage element.
  • the memory further includes a bit line, which can provide a high level or a low level for the memory unit, and the memory unit further includes a first selection transistor.
  • the following steps are included: Controlling the first selection transistor through a first control signal, so that the first selection transistor is electrically connected to the second end of the storage element and the bit line in response to the first control signal.
  • the memory further includes a write bit line capable of providing a high level or a low level, and the memory further includes a second selection transistor.
  • the memory further includes the following steps: Two control signals control the second selection transistor so that the second selection transistor is electrically connected to the first end of the source line and the write bit line in response to the second control signal.
  • the memory further includes a third selection transistor, and when performing a write operation on the memory, the method further includes the following step: controlling the third selection transistor through a third control signal, so that the third selection transistor is responsive to The third control signal transmits a high or low level signal to the second end of the source line.
  • the first current provided to the memory flows from the bit line through the storage element to the source line when writing 1; when writing 0, it flows from the source line through the storage element to The bit line.
  • the second current provided to the memory flows from the write bit line to the second end of the source line when writing 1; when writing 0, it flows from the second end of the source line to The write bit line.
  • the method further includes performing a read operation on the memory, including: providing a third current to the memory, and the third current flows from the bit line through the storage element to the second end of the source line .
  • the memory and the reading and writing method of the memory of the present invention control the current flowing through the memory by controlling the voltage relationship between the three terminals of the memory, using the first current flowing through the memory cell and the first current flowing through the memory cell and the second current not flowing through the memory cell. Two currents are used to control the storage state of the storage unit, which avoids the degradation of memory performance and reliability caused by only using a large current through the storage unit to control the storage state of the storage device.
  • the memory and the method for reading and writing the memory can realize the reading and writing of data on the same storage unit, and has a higher integration density and access speed.
  • FIG. 1 is a schematic diagram of a connection structure of a memory in a specific embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a connection structure of a memory in a specific embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a connection structure of a memory in a specific embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a connection structure of a memory in a specific embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a sequence of read and write operations of the memory in a specific embodiment of the present invention.
  • Fig. 6 is a schematic flow diagram of the steps of a method for reading and writing a memory in a specific embodiment of the present invention.
  • MTJ Magnetic Tunnel Junction
  • the basic structure of the MTJ element has three layers of magnetic layer/insulating layer/magnetic layer. One magnetic layer is called a free layer, and the other magnetic layer is called a pinned layer.
  • the insulating layer in the middle is called a tunnel barrier layer or a non-magnetic isolation layer.
  • the direction of the magnetic moment (or the direction of magnetization) of the pinned layer is fixed, while the direction of the magnetic moment of the free layer is variable, usually parallel or opposite to the direction of the magnetic moment of the pinned layer.
  • the MTJ element is in a low resistance state, and when the magnetic moment directions of the free layer and the fixed layer are antiparallel, the MTJ element is in a high resistance state.
  • MRAM can realize the storage of binary 0 or 1 by changing the direction of the magnetic moment of the free layer in the MTJ element.
  • an MRAM based on the principle of STT Spin Transfer Torque
  • STT-MRAM Spin Transfer Torque
  • the writing principle of STT-MRAM is to provide a write current from the free layer to the fixed layer or from the fixed layer to the free layer through the tunnel barrier layer, and the magnetization direction of the free layer is changed relative to the magnetization direction of the fixed layer by the spin current Parallel or anti-parallel, so as to realize the writing operation to the MTJ element.
  • the write current of the STT-MRAM needs to pass through the tunnel barrier layer, excessive write currents during the use of the MRAM may damage the tunnel barrier layer, thereby affecting the performance and reliability of the MRAM.
  • an MRAM based on the principle of SHE spin Hall Effect, Spin Hall Effect
  • SHE-MRAM Spin Hall Effect
  • the SHE-MRAM must be based on a three-terminal device. Design, there is a problem of low storage density.
  • FIG. 1 is a schematic diagram of the connection structure of the memory in a specific embodiment of the present invention
  • FIG. 2 is a schematic diagram of the connection structure of the memory in a specific embodiment of the present invention
  • FIG. 4 is a schematic diagram of a connection structure of a memory in a specific embodiment of the present invention.
  • a memory including: a memory cell, including a storage element 101; a source line 204, which is electrically connected to the storage element 101 The first end 211; the memory is configured to change the storage state of the storage element 101 through a first current Iwrite1 and a second current Iwrite2, the first current Iwrite1 flows through the storage element 101, and the second current Iwrite2 flows through the source line 204 and does not flow through the storage element 101.
  • the memory can implement data reading and writing on the same storage element 101, and has a higher memory integration density and a faster access speed.
  • the first current Iwrite1 and the second current Iwrite2 are used to control write 1 and write 0 at the same time, and the second current Iwrite2 does not pass through the storage element 101, the flow through the storage during the write operation is reduced.
  • the current of the element 101 ensures that the current passing through the storage element 101 during writing is not too large, and the long-term reliability of the memory is ensured.
  • the second end 207 of the storage element 101 is configured as a high level when 1 is written, the first end 205 of the source line 204 is configured as a high level, and the source The second end 206 of the line 204 is configured to be a low level, and the current status in the memory corresponds to the write 1 state of the first current Iwrite1 and the second current Iwrite2; when writing 0, the second end of the storage element 101 is configured Is a low level, the first end 205 of the source line 204 is configured to be a low level, and the second end 206 of the source line 204 is configured to be a high level.
  • the current condition in the memory is the same as the first current Iwrite1 corresponds to the write 0 state of the second current Iwrite2.
  • the source line 204 is made of conductive materials, such as metals such as platinum and tantalum, topological insulators such as Bi 2 Se 3 , and semi-metallic materials MoTe 2 and chalcogenide materials Bi x Te 1-x may also be a combination of the aforementioned materials. It should be clear to those skilled in the art that the material for preparing the source line 204 can be selected as required.
  • connection between the source line 204 and the first end 211 of the storage element 101 may be a direct connection, or a connection realized through other contact structures. It should be clear to those skilled in the art that the connection manner of the source line 204 and the first end 211 of the storage element 101 can be selected as required.
  • the memory further includes: a bit line 103.
  • bit line 103 is marked as BL in FIGS. 2, 3, and 5;
  • the storage unit also includes The first selection transistor 209 is configured to electrically connect the second terminal 207 of the storage element 101 and the bit line 103 in response to a first control signal, and the first control signal may be The word line signal is marked as WL in FIGS. 2, 3, and 5.
  • the memory is further configured to use the bit line 103 as the second end of the storage element 101 when the second end 207 of the storage element 101 is electrically connected to the bit line 103.
  • the two terminals 207 provide a high level or a low level. Therefore, the first selection transistor 209 can be used as a switch between the second terminal 207 of the storage element 101 and a high level or a low level.
  • the gate of the first selection transistor 209 is connected to the first control signal.
  • the first selection transistor 209 is an NMOS transistor.
  • the first selection transistor 209 may also be a PMOS transistor, a CMOS switch, etc., which can be selected by those skilled in the art according to needs.
  • the first selection transistor 209 is configured to respond to the first control signal in the write state and electrically connect the second terminal 207 of the storage element 101 and the bit line 103, And the bit line 103 is configured to provide a high level for the second end 207 of the storage element 101 when writing a 1, and provide a low level for the second end 207 of the storage element 101 when writing a 0.
  • the memory further includes: a write bit line 102.
  • the write bit line 102 is marked as WBL in FIGS. 2, 3, and 5; and a second selection transistor 208
  • the second selection transistor 208 is configured to electrically connect the first end 205 of the source line 204 and the write bit line 102 in response to a second control signal, and the second control signal may be a write word line
  • the signal (Write word line) is marked as WWL in Figure 2, Figure 3, and Figure 5.
  • the memory is further configured to use the write bit line 102 as the The first end 205 of the source line 204 provides a high level or a low level.
  • the gate of the second selection transistor 208 is connected to the second control signal.
  • the second selection transistor 208 is an NMOS transistor.
  • the second selection transistor 208 is a PMOS transistor, a CMOS switch, etc., which can be selected by those skilled in the art according to needs.
  • the second selection transistor 208 is configured to electrically connect the first end 205 of the source line 204 and the write state in response to the second control signal in the write state.
  • Bit line 102, and the write bit line 102 is configured to provide a high level for the first end 205 of the source line 204 when writing 1, and when writing 0, it is the first end 205 of the source line 204 Provide low level.
  • the memory further includes: a third selection transistor 210, the third selection transistor 210 is configured to respond to a third control signal to turn a high or low power
  • the flat signal is transmitted to the second end 206 of the source line 204, and the third control signal is marked as WSL in FIG. 3.
  • the gate of the third selection transistor 210 is connected to the third control signal.
  • the third selection transistor 210 is an NMOS transistor.
  • the third selection transistor 210 is a PMOS transistor, a CMOS switch, etc., which can be selected by those skilled in the art according to needs.
  • the third selection transistor 210 is configured to respond to the third control signal in the write state, and transmit a low level to the first of the source line 204 when writing 1
  • the second terminal 206 transmits a high level to the second terminal 206 of the source line 204 when writing 0.
  • the third selection transistor 210 may not be provided, and the second end of the source line 204 may be directly provided with a high level or a low level, as shown in FIG. 2.
  • the first current Iwrite1 flows from the bit line through the storage element to the source line 204 when writing 1, that is, flows from the second end 207 of the storage element 101 to the source.
  • the second end 206 of the pole line 204 flows from the source line 204 through the memory cell to the bit line when writing 0, that is, flows from the second end 206 of the source line 204 to the storage element 101
  • the second current Iwrite2 flows from the first end 205 of the source line 204 to the second end 206 of the source line 204 when writing 1, and from the second end of the source line 204 when writing 0. 206 flows to the first end 205 of the source line 204.
  • the memory is configured to read data stored in the storage element 101 through a third current Iread, and the third current Iread flows from the bit line 103 through the storage element 101 to The second end 206 of the source line 204.
  • the memory is configured to provide a high level for the second end 207 of the storage element 101 and a low level for the second end 206 of the source line 204 during reading.
  • the direction of the current is from the second end 207 of the storage element 101 to the source line 204.
  • the second end 206 is configured to read data stored in the storage element 101 through a third current Iread, and the third current Iread flows from the bit line 103 through the storage element 101 to The second end 206 of the source line 204.
  • the memory is configured to provide a high level for the second end 207 of the storage element 101 and a low level for the second end 206 of the source line
  • the write bit line 102 is configured not to be electrically connected to the first end 205 of the source line 204. This can be achieved by controlling the second control signal to be a low level. In this case, the second selection transistor 208 is turned off, no matter whether the write bit line 102 is at a high level or a low level, it cannot affect the third current Iread in the memory.
  • the source A selection transistor is provided between the second end 206 of the line 204 and a high or low level signal.
  • the high level and low level mentioned in the present invention are both relative concepts, and do not limit the specific voltage value of the high level nor the specific voltage value of the low level, nor do they limit the specific voltage value of the low level in the present invention. All high levels are equal in average.
  • the high level on the bit line 103 and the high level written on the bit line 102 may be different voltages, and it is not limited that the high levels of the same position at different stages are equal, for example,
  • the high level applied by the bit line 103 in the write 1 state and the read state can be different voltage values.
  • the corresponding high-level and low-level values can be set by themselves according to process nodes, speed requirements, reliability requirements, etc.
  • FIG. 5 is a timing diagram of the read and write operations of the memory in a specific embodiment of the present invention.
  • SL represents the second end 206 of the source line 204 Voltage changes.
  • the third selection transistor 210 is not provided in FIG. 5, so there is no third control signal, but those skilled in the art should be able to obtain the operation timing of the third selection transistor 210 without any doubt based on the above text description.
  • the first selection transistor 209 and the second selection transistor 208 are both NMOS transistors.
  • the first control signal and the second control signal are both high level
  • the first selection transistor 209 and the second selection transistor 208 are both turned on
  • the bit line 103 is
  • the second end 207 of the storage element 101 provides a high level
  • the write bit line 102 provides a high level for the first end 205 of the source line 204.
  • the second end 206 of the source line 204 is at a low level.
  • the second current Iwrite2 at the second end 206.
  • the first control signal when reading, the first control signal is still high and the second control signal is low.
  • the first selection transistor 209 is turned on, and the second selection transistor 208 is turned off. OFF, the second end 206 of the source line 204 is connected to a low level.
  • the storage state of the storage element 101 can be obtained by detecting the magnitude of the third current Iread flowing from the second end 207 of the storage element 101 to the second end 206 of the source line 204.
  • the waiting state exists.
  • the first control signal and the second control signal are both at a low level, so that both the first selection transistor 209 and the second selection transistor 208 are turned off, and the second control signal of the source line 204 is turned off.
  • the two terminals 206 are at a low level, there is no voltage difference between the three ports of the entire memory, and no current flows in the memory.
  • the third control signal for controlling the third selection transistor 210 is also at a low level, and the third selection transistor 210 is also turned off.
  • the storage element 101 includes a magnetic tunnel junction.
  • the magnetic tunnel junction includes: a free layer 203 connected to the source line 204; a non-magnetic isolation layer 202 provided on the upper surface of the free layer 203; The fixed layer 201 on the upper surface of the insulating layer; the magnetic moment direction of the free layer 203 is variable, and the magnetic moment direction of the fixed layer 201 is fixed; the first selection transistor 209 is connected to the fixed layer 201.
  • the free layer 203 and the fixed layer 201 can also be changed positions, and can be set by themselves according to needs.
  • the non-magnetic isolation layer 202 includes at least one of a non-magnetic insulating layer or a non-magnetic metal layer.
  • the specific structure of the non-magnetic isolation layer 202 can be set as required.
  • the current direction is from the second end 207 of the storage element 101 to the first end 211 of the storage element 101, and the free layer 203
  • the current direction is from the first end of the storage element 101 to the second end 207 of the storage element 101, and the direction of the magnetic moment of the free layer 203 is the first Two directions.
  • the resistance of the magnetic tunnel junction is different. Therefore, when reading the data stored in the storage element 101, the resistance can be different in the two cases. Read it.
  • the first current Iwrite1 flowing through the storage element 101 and the second current Iwrite2 not flowing through the storage element 101 are used at the same time to change the storage state of the storage element 101.
  • the memory includes a plurality of memory cells, and the first end of the storage element 101 in each of the memory cells is connected to the source line 204.
  • This shared source line structure can increase storage density.
  • the more storage units included in the memory the more data the memory can store, and the larger the capacity of the memory.
  • the plurality of memory cells form an array, each row of memory cells is set to one source line 204, the bit lines 103 connected to each row of memory cells are connected to each other, and the first selection of each column of memory cells
  • the transistor 209 is connected to the same control line.
  • it can be realized by controlling a certain source line 204, a certain control line, a certain bit line 103, etc. in the array.
  • FIG. 6 is a schematic diagram of a step flow diagram of a method for reading and writing a memory.
  • the memory includes a storage unit, the storage unit includes a storage element 101, and the memory is configured to change the storage state of the storage element 101 through a first current Iwrite1 and a second current Iwrite2, so
  • the memory further includes a source line 204, which is electrically connected to the first end 211 of the memory element 101.
  • the memory When the memory is written, it includes: S61 provides the first current Iwrite1 to the memory; S62 provides the memory The second current Iwrite2; wherein, the first current Iwrite1 flows through the storage element 101, and the second current Iwrite2 flows through the source line 204, but does not flow through the storage element 101.
  • the memory can implement data reading and writing on the same storage element 101, and has a higher memory integration density and a faster access speed.
  • the memory further includes: a bit line 103; the memory cell further includes a first selection transistor 209, and the first selection transistor 209 is configured to be electrically connected to each other in response to a first control signal.
  • the second end 207 of the storage element 101 and the bit line 103 are described.
  • the memory is also configured to use the bit line 103 to provide the second end 207 of the storage element 101 with a high level or when the second end 207 of the storage element 101 is electrically connected to the bit line 103. Low level.
  • the first selection transistor 209 is configured to respond to the first control signal in the write state, and electrically connect the second terminal 207 of the storage element 101 and the bit line 103.
  • the memory further includes: a write bit line 102; a second selection transistor 208, the second selection transistor 208 is configured to be electrically connected to the source line in response to a second control signal
  • the first end 205 of 204 is connected to the write bit line 102.
  • the control of the write bit line 102 and the first end 205 of the source line 204 is also controlled by the on-off control of the second selection transistor 208.
  • the memory is also configured to use the write bit line 102 as the first end of the source line 204 when the first end 205 of the source line 204 is electrically connected to the write bit line 102.
  • 205 provides high or low level.
  • the memory further includes: a third selection transistor 210 configured to transmit a high or low level to the source line in response to a third control signal The second end of 204.
  • the first current Iwrite1 is provided to the memory to flow from the bit line 103 through the storage element 101 to the source line 204 when writing 1; when writing 0, it flows from the source line 204.
  • the line 204 flows to the bit line 103 through the memory cell.
  • the second current Iwrite2 provided to the memory flows from the write bit line 102 to the second end of the source line 204 when writing 1; when writing 0, it flows from the source
  • the second end of the polar line 204 flows to the write bit line 102.
  • the first current Iwrite1 and the second current Iwrite2 are generated by controlling the voltages of the three terminals of the memory so that the second terminal 207 of the storage element 101 and the first terminal 205 of the source line 204 are This is achieved by having a voltage difference between the second end 206 of the source line 204 and the source line 204.
  • the voltage of the second terminal 207 of the element 101 is higher than the voltage of the second terminal 206 of the source line 204, or the voltage of the second terminal 206 of the source line 204 is higher than the voltage of the second terminal 207 of the storage element 101.
  • first current Iwrite1 and second current Iwrite2 are classified by the path of the current. In fact, the current can be classified according to the two states of writing 1 and writing 0.
  • the first current Iwrite1 and the second current Iwrite2 are used to control write 1 and write 0 at the same time, and the second current Iwrite2 does not pass through the storage element 101, the flow through the storage during the write operation is reduced.
  • the current of the element 101 ensures that the current passing through the storage element 101 during writing is not too large, and the long-term reliability of the memory is ensured.
  • the read operation in the read-write method includes the following steps: provide a third current Iread to the memory, and the third current Iread flows from the bit line 103 through the storage element 101 to The second end of the source line 204 obtains the storage state of the storage element 101 by detecting the magnitude of the third current Iread.
  • the storage element 101 includes a magnetic tunnel junction.
  • the magnetic tunnel junctions have different resistances as the direction of the magnetic moment of the free layer 203 changes, and since the storage element 101 stores 1 or 0, it corresponds to the different directions of the magnetic moment of the free layer 203. Therefore, when the data stored in the storage element 101 is read through the third current Iread, the data stored in the storage element 101 can be read in combination with the resistance of the storage element 101.
  • the time sequence in FIG. 5 can be used to represent the level changes of the three terminals of the memory during the reading and writing process.
  • SL represents the voltage change of the second terminal 206 of the source line 204.
  • the first control signal and the second control signal are both high level
  • the first selection transistor 209 and the second selection transistor 208 are both turned on
  • the bit line 103 is The second end 207 of the storage element 101 provides a high level
  • the write bit line 102 provides a high level for the first end 205 of the source line 204.
  • the second end 206 of the source line 204 is at a low level.
  • the first control signal when reading, the first control signal is still high and the second control signal is low.
  • the first selection transistor 209 is turned on, and the second selection transistor 208 is turned off. OFF, the second end 206 of the source line 204 is at a low level.
  • the third current Iread flowing from the second end 207 of the storage element 101 to the second end 206 of the source line 204 is generated, and the storage of the storage element 101 can be obtained by detecting the magnitude of the third current Iread. state.
  • the first control signal and the second control signal are both at a low level, so that both the first selection transistor 209 and the second selection transistor 208 are turned off, and the second control signal of the source line 204 is turned off.
  • the two terminals 206 are always at a low level, there is no voltage difference between the three ports of the entire memory, and no current flows in the memory.
  • the third control signal for controlling the third selection transistor 210 is also at a low level, and the third selection transistor 210 is also turned off.
  • the first current Iwrite1 flowing through the storage element 101 and the second current Iwrite2 not flowing through the storage element 101 are used at the same time to perform a write operation on the storage element, Avoid the problem of excessive current when only using STT current for writing, that is, avoid the damage or degradation of the storage element 101 caused by using a large current to directly act on the storage element 101, thereby avoiding its impact on the performance and reliability of the memory .
  • the embodiment of the present invention uses the first current Iwrite1 and the second current Iwrite2 to perform the write operation, those skilled in the art should understand that based on the same principle, the first current Iwrite1 and the second current Iwrite2 can also be used for erasing. In addition to operations and other operations that change the storage state.

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  • Mram Or Spin Memory Techniques (AREA)

Abstract

一种存储器及存储器的读写方法，能够避免MRAM在使用过程中容易由于过大的写入电流而毁损或退化，并具有较大的存储器集成密度。所述存储器包括：存储单元，包括存储元件（101）；源极线（204），电连接所述存储元件（101）的第一端（211）；所述存储器被配置为通过第一电流（Iwrite1）和第二电流（Iwrite2）改变所述存储元件（101）的存储状态，所述第一电流（Iwrite1）流经所述存储元件（101），所述第二电流（Iwrite2）流经所述源极线（204），而不流经所述存储元件（101）。

Description

存储器及存储器的读写方法
相关申请引用说明
本申请要求于2020年04月16日递交的中国专利申请号202010299470.8，申请名为“存储器及存储器的读写方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本发明涉及存储器领域，具体涉及一种存储器及存储器的读写方法。
背景技术
MRAM(Magnetic Random Access Memory：磁性随机存储器)是可高速动作的非易失性的磁存储器。由于具有非易失性、随机访问、访问速度快等优点，MRAM被大量地研究。
现有技术中的MRAM至少存在以下难以克服的问题：MRAM在使用过程中容易由于过大的写入电流而毁损磁隧道结或退化，从而影响MRAM的性能和可靠性。亟需提出一种新的存储器来克服上述问题。
发明内容
本发明的目的在于提供一种存储器及存储器的读写方法，能够避免MRAM在使用过程中容易由于过大的电流而影响器件性能和可靠性，并具有较大的存储器集成密度。
为了解决上述技术问题，以下提供了一种存储器，包括：存储单元，包括存储元件；源极线，电连接所述存储元件的第一端；所述存储器被配置为通过第一电流和第二电流改变所述存储元件的存储状态，所述第一电流流经所述存储元件，所述第二电流流经所述源极线，而不流经所述存储元件。
可选的，还包括：位线；所述存储单元还包括第一选择晶体管，所述第一选择晶体管被配置为响应于第一控制信号而电连接所述存储元件的第二端与所述位线。
可选的，还包括：写入位线；第二选择晶体管，所述第二选择晶体管被配置为响应于第二控制信号而电连接所述源极线的第一端与所述写入位线。
可选的，所述第一电流在写1时从所述位线经过所述存储元件流向所述源极线，在写0时从所述源极线经过所述存储单元流向所述位线。
可选的，所述第二电流在写1时从所述源极线的第一端流向所述源极线的第二端，在写0时从所述源极线的第二端流向所述源极线的第一端。
可选的，还包括：第三选择晶体管，所述第三选择晶体管被配置为响应于第三控制信号而将一高或低电平信号传输至所述源极线的第二端。
可选的，所述存储器还被配置为在所述存储元件的第二端与所述位线电连接时，利用所述位线为所述存储元件的第二端提供高电平或低电平。
可选的，所述存储器还被配置为在所述源极线的第一端与所述写入位线电连接时，利用所述写入位线为所述源极线的第一端提供高电平或低电平。
可选的，所述存储器还被配置为给所述源极线的第二端提供高电平或低电平。
可选的，包括多个存储单元，且每个所述存储单元中的存储元件的第一端均连接至所述源极线。
可选的，所述存储器被配置为通过第三电流读取所述存储元件内存储的数据，所述第三电流从所述位线经过所述存储元件流向所述源极线的第二端。
可选的，所述位线被配置为读取时电连接至所述存储元件的第二端，并为所述存储元件的第二端提供高电平，所述源极线的第二端在读取时被配置为低电平。
可选的，所述存储元件包括磁隧道结。
可选的，所述磁隧道结包括：连接至所述源极线的自由层；设置在所述自由层上表面的非磁性隔离层；设置在所述非磁性绝缘层上表面的固定层；所述自由层的磁矩方向可变，所述固定层的磁矩方向固定；所述第一选择晶体管连接所述固定层。
为了解决上述问题，以下还提供了一种存储器的读写方法，所述存储器包括存储单元，所述存储单元包括存储元件，所述存储器被配置为通过第一电流和第二电流改变所述存储元件的存储状态，所述存储器还包括源极线，电连接所述存储元件的第一端，对所述存储器进行写操作时，包括：向所述存储器提供第一电流；向所述存储器提供第二电流；其中，所述第一电流流经所述存储元件，所述第二电流流经所述源极线，而不流经所述存储元件。
可选的，所述存储器还包括位线，能够为所述存储单元提供高电平或低电 平，所述存储单元还包括第一选择晶体管，对所述存储器进行写操作时，包括以下步骤：通过第一控制信号控制所述第一选择晶体管，使所述第一选择晶体管响应于所述第一控制信号，电连接所述存储元件的第二端与所述位线。
可选的，所述存储器还包括写入位线，能够提供高电平或低电平，所述存储器还包括第二选择晶体管，对所述存储器进行写操作时，还包括以下步骤：通过第二控制信号控制所述第二选择晶体管，使所述第二选择晶体管响应于所述第二控制信号，电连接所述源极线的第一端与所述写入位线。
可选的，所述存储器还包括第三选择晶体管，对所述存储器进行写操作时，还包括以下步骤：通过第三控制信号控制所述第三选择晶体管，使所述第三选择晶体管响应于所述第三控制信号，将一高或低电平信号传输至所述源极线的第二端。
可选的，向所述存储器提供的第一电流在写1时从所述位线经过所述存储元件流向所述源极线；在写0时从所述源极线经过所述存储元件流向所述位线。
可选的，向所述存储器提供的第二电流在写1时从所述写入位线流向所述源极线的第二端；在写0时从所述源极线的第二端流向所述写入位线。
可选的，还包括对所述存储器进行读操作，包括：向所述存储器提供第三电流，所述第三电流从所述位线经过所述存储元件流向所述源极线的第二端。
本发明的存储器和存储器的读写方法通过控制所述存储器三端之间的电压关系，来控制流经所述存储器的电流，使用流经存储单元的第一电流和不流经存储单元的第二电流来实现对存储单元的存储状态的控制，避免了只使用一个经过存储单元的大电流来控制存储器件的存储状态而造成的存储器性能和可靠性的退化。并且，所述存储器和存储器的读写方法可以在同一存储单元上实现数据的读写，具有较高的集成密度以及存取速度。
附图说明
图1为本发明的一种具体实施方式中的存储器的连接结构示意图。
图2为本发明的一种具体实施方式中的存储器的连接结构示意图。
图3为本发明的一种具体实施方式中的存储器的连接结构示意图。
图4为本发明的一种具体实施方式中的存储器的连接结构示意图。
图5为本发明的一种具体实施方式中的存储器的读写操作的时序示意图。
图6为本发明的一种具体实施方式中的存储器的读写方法的步骤流程示意图。
具体实施方式
研究发现，在MRAM中，可以使用MTJ(Magnetic Tunnel Junction：磁性隧道结)元件作为存储元件。MTJ元件的基本结构具有磁性层/绝缘层/磁性层这3层，一个磁性层被称为自由层，另一个磁性层被称为固定层。另外，中间的绝缘层被称为隧道势垒层或者非磁性隔离层。
一般而言，固定层的磁矩方向(或磁化方向)固定，而自由层的磁矩方向可变，通常与固定层的磁矩方向平行或者反方向平行。在自由层和固定层的磁矩方向平行的情况下，MTJ元件处于低电阻状态，在自由层和固定层的磁矩方向反平行时，MTJ元件处于高电阻状态。MRAM通过改变MTJ元件中自由层的磁矩方向，即可实现对二进制0或者1的存储。
现有技术中使用一种基于STT(Spin Transfer Torque，自旋转移矩)原理的MRAM，即STT-MRAM，使用STT原理控制所述自由层的磁化方向。STT-MRAM的写入原理是，经由隧道势垒层从自由层向固定层或者从固定层向自由层提供写入电流，通过自旋电流使自由层的磁化方向相对固定层的磁化方向改变为平行或者反平行，从而实现对MTJ元件的写入操作。
由于STT-MRAM的写入电流需要穿过隧道势垒层，MRAM在使用过程中多次过大的写入电流可能会损伤隧道势垒层，从而影响MRAM的性能及可靠性。并且，读取STT-MRAM中的数据时也需产生穿过MTJ元件的读取电流，在隧道势垒层受到损伤的情形下，读取电流可能增大，由于STT效应的存在，可能会出现误写入操作(自由层被误磁化)。
现有技术中还使用一种基于SHE(Spin Hall Effect，自旋霍尔效应)原理的MRAM，即SHE-MRAM来获取相对高的读写次数，但是，该SHE-MRAM必须基于三端器件的设计，存在存储密度不高的问题。
以下结合附图和具体实施方式对本发明提出的一种存储器及存储器的读写方法作进一步详细说明。
请参阅图1、图2和图4，其中图1为本发明的一种具体实施方式中的存储器的连接结构示意图，图2为本发明的一种具体实施方式中的存储器的连接 结构示意图，图4为本发明的一种具体实施方式中的存储器的连接结构示意图。
在图1、图2和图4所示的具体实施方式中，提供了一种存储器，包括：存储单元，包括存储元件101；源极线(source line)204，电连接所述存储元件101的第一端211；所述存储器被配置为通过第一电流Iwrite1和第二电流Iwrite2改变所述存储元件101的存储状态，所述第一电流Iwrite1流经所述存储元件101，所述第二电流Iwrite2流经所述源极线204，而不流经所述存储元件101。
在图1、图2和图4所示的具体实施方式中，所述存储器能够在同一个存储元件101上实现数据的读写，具有较高的存储器集成密度，以及较快的存取速度。
在该具体实施方式中，由于同时使用第一电流Iwrite1和第二电流Iwrite2来控制写1和写0，并且第二电流Iwrite2不经过所述存储元件101，减小写操作时流经所述存储元件101的电流，保证在写入时穿过所述存储元件101的电流不至于过大，保证存储器的长期可靠性。
在一种具体实施方式中，写1时所述存储元件101的第二端207被配置为高电平，所述源极线204的第一端205被配置为高电平，所述源极线204的第二端206被配置为低电平，存储器中的电流状况与第一电流Iwrite1和第二电流Iwrite2的写1状态对应；写0时，所述存储元件101的第二端被配置为低电平，所述源极线204的第一端205被配置为低电平，所述源极线204的第二端206被配置为高电平，存储器中的电流状况与第一电流Iwrite1和第二电流Iwrite2的写0状态对应。
在一种具体实施方式中，所述源极线204由导电材料制备而成，比如金属铂、钽等金属，Bi 2Se 3等拓扑绝缘体，以及半金属材料MoTe 2和硫族化物材料Bi xTe 1-x，也可以是前述材料的组合。本领域技术人员应当清楚可以根据需要选择制备所述源极线204的材料。
在一种具体实施方式中，所述源极线204与所述存储元件101的第一端211的连接可以是直接连接，也可以是通过其他的接触结构来实现的连接。本领域技术人员应当清楚可以根据需要选择所述源极线204与所述存储元件101的第一端211的连接方式。
在一种具体实施方式中，所述存储器还包括：位线(Bit line)103，需要注意的是，位线103在图2、图3、图5中标注为BL；所述存储单元还包括第一选择晶体管209，所述第一选择晶体管209被配置为响应于第一控制信号而电连接所述存储元件101的第二端207与所述位线103，所述第一控制信号可为字线信号(word line)，在图2、图3及图5中被标注为WL。
在一种具体实施方式中，所述存储器还被配置为在所述存储元件101的第二端207与所述位线103电连接时，利用所述位线103为所述存储元件101的第二端207提供高电平或低电平。因此，所述第一选择晶体管209可以作为存储元件101的第二端207与高电平或低电平之间的开关。
在一种具体实施方式中，所述第一选择晶体管209的栅极连接所述第一控制信号。在一种具体实施方式中，所述第一选择晶体管209为NMOS管。在另一种具体实施方式中，所述第一选择晶体管209也可为PMOS管、CMOS开关等，本领域技术人员可根据需要自行选择。
在一种具体实施方式中，所述第一选择晶体管209被配置为在写入状态时响应所述第一控制信号，电连接所述存储元件101的第二端207与所述位线103，且所述位线103被配置为写1时为所述存储元件101的第二端207提供高电平，写0时为所述存储元件101的第二端207提供低电平。
在一种具体实施方式中，所述存储器还包括：写入位线102，需要注意的是，写入位线102在图2、图3、图5中被标注为WBL；第二选择晶体管208，所述第二选择晶体管208被配置为响应于第二控制信号而电连接所述源极线204的第一端205与所述写入位线102，所述第二控制信号可为写字线信号(Write word line)，在图2、图3及图5中被标注为WWL。
在一种具体实施方式中，所述存储器还被配置为在所述源极线204的第一端205与所述写入位线102电连接时，利用所述写入位线102为所述源极线204的第一端205提供高电平或低电平。
在一种具体实施方式中，所述第二选择晶体管208的栅极连接所述第二控制信号。在一种具体实施方式中，所述第二选择晶体管208为NMOS管。在另一种具体实施方式中，所述第二选择晶体管208为PMOS管、CMOS开关等，本领域技术人员可根据需要自行选择。
在一种具体实施方式中，所述第二选择晶体管208被配置为在写入状态时响应于所述第二控制信号，电连接所述源极线204的第一端205与所述写入位线102，且所述写入位线102被配置为写1时为所述源极线204的第一端205提供高电平，写0时为所述源极线204的第一端205提供低电平。
请参阅图3，在一种具体实施方式中，所述存储器还包括：第三选择晶体管210，所述第三选择晶体管210被配置为响应于第三控制信号而将一高电平或低电平信号传输至所述源极线204的第二端206，所述第三控制信号在图3中被标注为WSL。
如图3所示，所述第三选择晶体管210的栅极连接所述第三控制信号。在一种具体实施方式中，所述第三选择晶体管210为NMOS管。在另一种具体实施方式中，所述第三选择晶体管210为PMOS管、CMOS开关等，本领域技术人员可根据需要自行选择。
在一种具体实施方式中，所述第三选择晶体管210被配置为在写入状态时响应于所述第三控制信号，在写1时将低电平传输至所述源极线204的第二端206，在写0时将高电平传输至所述源极线204的第二端206。
在一种其他的具体实施方式中，也可以不设置所述第三选择晶体管210，而是直接给所述源极线204的第二端提供高电平或者低电平，参阅图2。
在一种具体实施方式中，所述第一电流Iwrite1在写1时从所述位线经过所述存储元件流向所述源极线204，即从所述存储元件101的第二端207流向源极线204的第二端206，在写0时从所述源极线204经过所述存储单元流向所述位线，即从所述源极线204的第二端206流向所述存储元件101的第二端207。所述第二电流Iwrite2在写1时从所述源极线204的第一端205流向所述源极线204的第二端206，在写0时从所述源极线204的第二端206流向所述源极线204的第一端205。
在一种具体实施方式中，所述存储器被配置为通过第三电流Iread读取所述存储元件101内存储的数据，所述第三电流Iread从所述位线103经过所述存储元件101流向所述源极线204的第二端206。所述存储器被配置为读取时为所述存储元件101的第二端207提供高电平，为所述源极线204的第二端206提供低电平。存储元件101的第二端207与源极线204的第二端206之间具有 电压差，存在电流，电流方向为从所述存储元件101的第二端207，流向所述源极线204的第二端206。
需要注意的是，在读取时，所述写入位线102被配置为不与所述源极线204的第一端205电连接。这可以通过控制所述第二控制信号为低电平来实现。在这种情况下，所述第二选择晶体管208关断，无论写入位线102处于高电平还是低电平，都无法对存储器内的第三电流Iread造成影响。
在图3所示的具体实施方式中，所述位线103与存储元件101的第二端207之间、写入位线102与源极线204的第一端205之间、所述源极线204的第二端206与一高或低电平信号之间都设置有选择晶体管，通过关断所述第一选择晶体管209、第二选择晶体管208与第三选择晶体管210，可以使所述存储器处在一个等待状态。该等待状态下，该存储器内不存在任何电流。
需要注意的是，本发明所称高电平、低电平均为相对的概念，不限定高电平的具体电压值，也不限定低电平的具体电压值，并且也并不限定本发明中所有高电平均相等，例如所述位线103上的高电平与所述写入位线102上的高电平可以为不同电压，也不限定相同位置在不同阶段的高电平相等，例如所述位线103在写1状态和读取状态时所施加的高电平可以为不同电压值。本领域内技术人员应该理解，根据工艺结点、速度要求、可靠性要求等可自行设置相应高电平和低电平的值。
请参阅图5，为本发明的一种具体实施方式中的存储器的读写操作的时序示意图，在图5所示的具体实施方式中，SL代表所述源极线204的第二端206的电压变化。另外在图5中没有设置第三选择晶体管210，因此不存在第三控制信号，但本领域技术人员应可以根据上述文字描述毫无疑义地得到设置有第三选择晶体管210的操作时序。在该具体实施方式中，所述第一选择晶体管209和第二选择晶体管208都为NMOS管。
在图5中，写1时，所述第一控制信号、第二控制信号均为高电平，所述第一选择晶体管209、第二选择晶体管208均导通，所述位线103为所述存储元件101的第二端207提供高电平，所述写入位线102为所述源极线204的第一端205提供高电平。所述源极线204的第二端206为低电平。此时，存在从存储元件101的第二端207流向所述源极线204的第二端206的第一电流 Iwrite1，也存在从源极线204的第一端205流向所述源极线204的第二端206的第二电流Iwrite2。
在图5中，写0时，所述第一控制信号、第二控制信号仍为高电平，所述第一选择晶体管209、第二选择晶体管208仍导通，所述位线103为所述存储元件101的第二端207提供低电平，所述写入位线102为所述源极线204的第一端205提供低电平。所述源极线204的第二端206为高电平。此时，存在从所述源极线204的第二端流向所述存储元件101的第二端207的第一电流Iwrite1，也存在从所述源极线204的第二端流向所述源极线204的第一端205的第二电流Iwrite2。
在图5中，读取时，所述第一控制信号仍为高电平，所述第二控制信号为低电平，此时，所述第一选择晶体管209开启，第二选择晶体管208关断，所述源极线204的第二端206连接到低电平。此时，通过检测从所述存储元件101的第二端207流向所述源极线204的第二端206的第三电流Iread的大小即可得到所述存储元件101的存储状态。
在图5所示的具体实施方式中，存在所述等待状态。在所述等待状态下，所述第一控制信号、第二控制信号均为低电平，使得所述第一选择晶体管209和第二选择晶体管208都关断，所述源极线204的第二端206处于低电平，整个存储器的三个端口之间没有电压差，所述存储器内无电流流动。在图3所示的具有第三选择晶体管210的具体实施方式中，控制所述第三选择晶体管210的第三控制信号也处于低电平，所述第三选择晶体管210也关断。
在一种具体实施方式中，所述存储元件101包括磁隧道结。在一种具体实施方式中，所述磁隧道结包括：连接至所述源极线204的自由层203；设置在所述自由层203上表面的非磁性隔离层202；设置在所述非磁性绝缘层上表面的固定层201；所述自由层203的磁矩方向可变，所述固定层201的磁矩方向固定；所述第一选择晶体管209连接所述固定层201。本领域内技术人员应当理解，所述自由层203和所述固定层201也可调换位置，可根据需要自行设置。
在一种具体实施方式中，所述非磁性隔离层202包括非磁性绝缘层或非磁性金属层中的至少一种。实际上，可以根据需要设置所述非磁性隔离层202的具体结构。
在图2、图3所示的具体实施方式中，在写1时，电流方向为从所述存储元件101的第二端207流向所述存储元件101的第一端211，所述自由层203的磁矩方向为第一方向；在写0时，电流方向为从所述存储元件101的第一端流向所述存储元件101的第二端207，所述自由层203的磁矩方向为第二方向。由于所述自由层203的磁矩方向发生变化时，所述磁隧道结的电阻不同，因此，在读取所述存储元件101中存储的数据时，可根据两种情况下电阻不同的特点来进行读取。
在图1至图5所示的具体实施方式中，同时使用流经存储元件101的第一电流Iwrite1和不流经所述存储元件101的第二电流Iwrite2来改变所述存储元件101的存储状态，避免仅使用STT电流进行写入时电流过大的问题，即避免了使用大电流直接作用到存储元件101造成的所述存储元件101的毁损或退化，从而避免其对存储器性能和可靠性的影响。
请看图2和图3，所述存储器包括多个存储单元，且每个所述存储单元中的存储元件101的第一端均连接至所述源极线204。这种共用源极线的结构可增加存储密度。在该具体实施方式中，所述存储器内包含的存储单元越多，所述存储器能够存储的数据越多，存储器的容量也越大。
在一种具体实施方式中，所述多个存储单元构成阵列，每一行存储单元设置到一根源极线204，每一行存储单元连接到的位线103相互连接，每一列存储单元的第一选择晶体管209连接到同一控制线。在对某个存储单元进行读写控制时，可通过对阵列中某一源极线204、某一控制线、某一位线103等的控制来实现。
请看图1至图6，其中图6为一种存储器的读写方法的步骤流程示意图。在该具体实施方式中，所述存储器包括存储单元，所述存储单元包括存储元件101，所述存储器被配置为通过第一电流Iwrite1和第二电流Iwrite2改变所述存储元件101的存储状态，所述存储器还包括源极线204，电连接所述存储元件101的第一端211，对所述存储器进行写操作时，包括：S61向所述存储器提供第一电流Iwrite1；S62向所述存储器提供第二电流Iwrite2；其中，所述第一电流Iwrite1流经所述存储元件101，所述第二电流Iwrite2流经所述源极线204，而不流经所述存储元件101。
在图1、图2和图4所示的具体实施方式中，所述存储器能够在同一个存储元件101上实现数据的读写，具有较高的存储器集成密度，以及较快的存取速度。
在一种具体实施方式中，所述存储器还包括：位线103；所述存储单元还包括第一选择晶体管209，所述第一选择晶体管209被配置为响应于第一控制信号而电连接所述存储元件101的第二端207与所述位线103。所述存储器还被配置为在所述存储元件101的第二端207与所述位线103电连接时，利用所述位线103为所述存储元件101的第二端207提供高电平或低电平。
在一种具体实施方式中，所述第一选择晶体管209被配置为在写入状态时响应所述第一控制信号，电连接所述存储元件101的第二端207与所述位线103。
在一种具体实施方式中，所述存储器还包括：写入位线102；第二选择晶体管208，所述第二选择晶体管208被配置为响应于第二控制信号而电连接所述源极线204的第一端205与所述写入位线102。所述写入位线102与所述源极线204的第一端205的控制也受所述第二选择晶体管208的通断控制。所述存储器还被配置为在所述源极线204的第一端205与所述写入位线102电连接时，利用所述写入位线102为所述源极线204的第一端205提供高电平或低电平。
在一种具体实施方式中，所述存储器还包括：第三选择晶体管210，所述第三选择晶体管210被配置为响应于第三控制信号将一高或低电平传输至所述源极线204的第二端。
在一种具体实施方式中，向所述存储器提供第一电流Iwrite1在写1时从所述位线103经过所述存储元件101流向所述源极线204；在写0时从所述源极线204经过所述存储单元流向所述位线103。此处可以参考图2、3中的电流。
在一种具体实施方式中，向所述存储器提供的第二电流Iwrite2在写1时从所述写入位线102流向所述源极线204的第二端；在写0时从所述源极线204的第二端流向所述写入位线102。此处可以参考图2、3中的电流。
在该具体实施方式中，所述第一电流Iwrite1和第二电流Iwrite2的产生，是通过控制所述存储器三端的电压，使存储元件101的第二端207、源极线204 的第一端205和源极线204的第二端206之间具有电压差来实现的。需要使电流方向从存储元件101的第二端207流向源极线204的第二端206，或从源极线204的第二端206流向存储元件101的第二端207时，只需控制存储元件101的第二端207的电压高于源极线204的第二端206的电压，或源极线204的第二端206的电压高于存储元件101的第二端207的电压即可。需要使电流方向从源极线204的第一端205流向源极线204的第二端206，或从源极线204的第二端206流向源极线204的第一端205时，只需要控制源极线204的第一端205电压高于第二端206的电压，或源极线204的第二端206电压高于第一端205的电压即可实现。
需要注意的是，上述第一电流Iwrite1和第二电流Iwrite2是通过电流的路径来分类的。实际上也可以按照写1和写0两种状态来进行电流的分类。
在该具体实施方式中，由于同时使用第一电流Iwrite1和第二电流Iwrite2来控制写1和写0，并且第二电流Iwrite2不经过所述存储元件101，减小写操作时流经所述存储元件101的电流，保证在写入时穿过所述存储元件101的电流不至于过大，保证存储器的长期可靠性。
在一种具体实施方式中，所述读写方法中的读操作包括以下步骤：向所述存储器提供第三电流Iread，所述第三电流Iread从所述位线103经过所述存储元件101流向所述源极线204的第二端，通过检测第三电流Iread的大小来得到所述存储元件101的存储状态。
在一种具体实施方式中，所述存储元件101包括磁隧道结。所述磁隧道结随自由层203的磁矩方向的变化，而具有不同的电阻，并且，由于所述存储元件101存1或存0时，对应至所述自由层203不同的磁矩方向，因此在通过第三电流Iread读取所述存储元件101内存储的数据时，可结合所述存储元件101的电阻来读取所述存储元件101内存储的数据。
在一种具体实施方式中，可以使用图5中的时序来表示所述存储器的三端在读写过程中的电平变化。其中，SL代表所述源极线204的第二端206的电压变化。在图5中，写1时，所述第一控制信号、第二控制信号均为高电平，所述第一选择晶体管209、第二选择晶体管208均导通，所述位线103为所述存储元件101的第二端207提供高电平，所述写入位线102为所述源极线204 的第一端205提供高电平。所述源极线204的第二端206为低电平。此时，存在从存储元件101的第二端207流向所述源极线204的第二端206的第一电流Iwrite1，也存在从源极线204的第一端205流向所述源极线204的第二端的第二电流Iwrite2。
在图5中，写0时，所述第一控制信号、第二控制信号仍为高电平，所述第一选择晶体管209、第二选择晶体管208仍导通，所述位线103为所述存储元件101的第二端207提供低电平，所述写入位线102为所述源极线204的第一端205提供低电平。所述源极线204的第二端206为高电平。此时，存在从所述源极线204的第二端206流向所述存储元件101的第二端207的第一电流Iwrite1，也存在从所述源极线204的第二端206流向所述源极线204的第一端205的第二电流Iwrite2。
在图5中，读取时，所述第一控制信号仍为高电平，所述第二控制信号为低电平，此时，所述第一选择晶体管209开启，第二选择晶体管208关断，所述源极线204的第二端206为低电平。此时，从所述存储元件101的第二端207流向所述源极线204的第二端206的第三电流Iread得以产生，通过检测第三电流Iread的大小即可得到存储元件101的存储状态。
在图5所示的具体实施方式中，还存在等待状态(Standby)。在所述等待状态下，所述第一控制信号、第二控制信号均为低电平，使得所述第一选择晶体管209和第二选择晶体管208都关断，所述源极线204的第二端206始终处于低电平，整个存储器的三个端口之间没有电压差，所述存储器内无电流流动。在图3所示的具有第三选择晶体管210的具体实施方式中，控制所述第三选择晶体管210的第三控制信号也处于低电平，所述第三选择晶体管210也关断。
在上述存储器的读写方法的具体实施方式中，由于同时使用流经存储元件101的第一电流Iwrite1和不流经所述存储元件101的第二电流Iwrite2来对所述存储元件进行写操作，避免仅使用STT电流进行写入时电流过大的问题，即避免了使用大电流直接作用到存储元件101造成的所述存储元件101的毁损或退化，从而避免其对存储器性能和可靠性的影响。虽然本发明的实施例是通过第一电流Iwrite1和第二电流Iwrite2来进行写操作，但本领域内技术人员应当理解，基于相同原理，亦可利用第一电流Iwrite1和第二电流Iwrite2来进行 擦除操作等其他改变存储状态的操作。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (21)

  1. 一种存储器，其特征在于，包括：
    存储单元，包括存储元件；
    源极线，电连接所述存储元件的第一端；
    所述存储器被配置为通过第一电流和第二电流改变所述存储元件的存储状态，所述第一电流流经所述存储元件，所述第二电流流经所述源极线，而不流经所述存储元件。
  2. 根据权利要求1所述的存储器，其特征在于，还包括：
    位线；
    所述存储单元还包括第一选择晶体管，所述第一选择晶体管被配置为响应于第一控制信号而电连接所述存储元件的第二端与所述位线。
  3. 根据权利要求2所述的存储器，其特征在于，还包括：
    写入位线；
    第二选择晶体管，所述第二选择晶体管被配置为响应于第二控制信号而电连接所述源极线的第一端与所述写入位线。
  4. 根据权利要求2所述的存储器，其特征在于，所述第一电流在写1时从所述位线经过所述存储元件流向所述源极线，在写0时从所述源极线经过所述存储单元流向所述位线。
  5. 根据权利要求3所述的存储器，其特征在于，所述第二电流在写1时从所述源极线的第一端流向所述源极线的第二端，在写0时从所述源极线的第二端流向所述源极线的第一端。
  6. 根据权利要求1所述的存储器，其特征在于，还包括：
    第三选择晶体管，所述第三选择晶体管被配置为响应于第三控制信号而将一高或低电平信号传输至所述源极线的第二端。
  7. 根据权利要求2所述的存储器，其特征在于，所述存储器还被配置为在所述存储元件的第二端与所述位线电连接时，利用所述位线为所述存储元件的第二端提供高电平或低电平。
  8. 根据权利要求3所述的存储器，其特征在于，所述存储器还被配置为在所述源极线的第一端与所述写入位线电连接时，利用所述写入位线为所述源极线的第一端提供高电平或低电平。
  9. 根据权利要3所述的存储器，其特征在于，所述存储器还被配置为给所述源极线的第二端提供高电平或低电平。
  10. 根据权利要求1所述的存储器，其特征在于，包括多个存储单元，且每个所述存储单元中的存储元件的第一端均连接至所述源极线。
  11. 根据权利要求2所述的存储器，其特征在于，所述存储器被配置为通过第三电流读取所述存储元件内存储的数据，所述第三电流从所述位线经过所述存储元件流向所述源极线的第二端。
  12. 根据权利要求11所述的存储器，其特征在于，所述位线被配置为读取时电连接至所述存储元件的第二端，并为所述存储元件的第二端提供高电平，所述源极线的第二端在读取时被配置为低电平。
  13. 根据权利要求1所述的存储器，其特征在于，所述存储元件包括磁隧道结。
  14. 根据权利要求13所述的存储器，其特征在于，所述磁隧道结包括：
    连接至所述源极线的自由层；
    设置在所述自由层上表面的非磁性隔离层；
    设置在所述非磁性绝缘层上表面的固定层；
    所述自由层的磁矩方向可变，所述固定层的磁矩方向固定；
    所述第一选择晶体管连接所述固定层。
  15. 一种存储器的读写方法，其特征在于，所述存储器包括存储单元，所述存储单元包括存储元件，所述存储器被配置为通过第一电流和第二电流改变所述存储元件的存储状态，所述存储器还包括源极线，电连接所述存储元件的第一端，对所述存储器进行写操作时，包括：
    向所述存储器提供第一电流；
    向所述存储器提供第二电流；
    其中，所述第一电流流经所述存储元件，所述第二电流流经所述源极线，而不流经所述存储元件。
  16. 根据权利要求15所述的读写方法，其特征在于，所述存储器还包括位线，能够为所述存储单元提供高电平或低电平，所述存储单元还包括第一选择晶体管，对所述存储器进行写操作时，包括以下步骤：
    通过第一控制信号控制所述第一选择晶体管，使所述第一选择晶体管响应 于所述第一控制信号，电连接所述存储元件的第二端与所述位线。
  17. 根据权利要求15所述的读写方法，其特征在于，所述存储器还包括写入位线，能够提供高电平或低电平，所述存储器还包括第二选择晶体管，对所述存储器进行写操作时，还包括以下步骤：
    通过第二控制信号控制所述第二选择晶体管，使所述第二选择晶体管响应于所述第二控制信号，电连接所述源极线的第一端与所述写入位线。
  18. 根据权利要求15所述的读写方法，其特征在于，所述存储器还包括第三选择晶体管，对所述存储器进行写操作时，还包括以下步骤：
    通过第三控制信号控制所述第三选择晶体管，使所述第三选择晶体管响应于所述第三控制信号，将一高或低电平信号传输至所述源极线的第二端。
  19. 根据权利要求16所述的读写方法，其特征在于，向所述存储器提供的第一电流在写1时从所述位线经过所述存储元件流向所述源极线；在写0时从所述源极线经过所述存储元件流向所述位线。
  20. 根据权利要求17所述的读写方法，其特征在于，向所述存储器提供的第二电流在写1时从所述写入位线流向所述源极线的第二端；在写0时从所述源极线的第二端流向所述写入位线。
  21. 根据权利要求16所述的读写方法，其特征在于，还包括对所述存储器进行读操作，包括：
    向所述存储器提供第三电流，所述第三电流从所述位线经过所述存储元件流向所述源极线的第二端。
PCT/CN2020/130383 2020-04-16 2020-11-20 存储器及存储器的读写方法 Ceased WO2021208436A1 (zh)

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