WO2020211537A1 - Array substrate, display panel, manufacturing method therefor, and display device - Google Patents

Abstract

The preset invention relates to the technical field of displays. Disclosed is an array substrate (10), a display panel, a manufacturing method therefor, and a display device. The array substrate (10) comprises a base substrate (101) and a thin-film transistor (102), a planarization pattern (103), and a bonding pattern (104) layered on the base substrate (101) in a direction away from the base substrate (101). The planarization pattern (103) comprises a via (W) and a recess (H), and the via (W) is provided with a conductive structure (105) therein. The bonding pattern (104) is electrically connected to the thin-film transistor (102) through the conductive structure (105). The recess (H) is used to accommodate a binder (40). The present invention simplifies the configuration process for a light-emitting unit (30), thereby simplifying the manufacturing process for a display panel.

Description

Array substrate, display panel and manufacturing method thereof, and display device

This disclosure claims the priority of a Chinese patent application filed on April 17, 2019 with the application number 201910308732.X and the invention title "Array substrate, display panel and manufacturing method thereof", the entire content of which is incorporated into this disclosure by reference in.

Technical field

The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, a manufacturing method thereof, and a display device.

Background technique

A micro light-emitting diode (Micro LED) is a light-emitting diode with a size of micrometers. Due to the small size of the Micro LED, it can be used as a pixel on the display panel. The display panel prepared by using Micro LED can be called a Micro LED display panel. Compared with Organic Light-Emitting Diode (OLED) display panels, Micro LED display panels have better service life and viewing angles than OLED display panels. Therefore, Micro LED display technology has become the current research focus in the field of display technology.

Summary of the invention

The present disclosure provides an array substrate, a display panel, a manufacturing method thereof, and a display device. The technical solution is as follows:

In one aspect, an array substrate is provided, including:

A base substrate, and a thin film transistor, a planarization pattern, and a bonding pattern stacked on the base substrate in a direction away from the base substrate;

The planarization pattern has a via hole and a groove, the via hole is provided with a conductive structure, the bonding pattern is connected to the thin film transistor through the conductive structure, and the groove is used to accommodate an adhesive .

Optionally, the planarization pattern includes a first sub-pattern and a second sub-pattern surrounding the first sub-pattern;

The groove is located on the side of the first sub-pattern away from the base substrate, the via hole is located in the second sub-pattern, and the binding pattern is located in the first sub-pattern away from the substrate. One side of the bottom substrate.

Optionally, the thickness of the first sub-pattern is greater than the thickness of the second sub-pattern.

Optionally, the thickness of the first sub-pattern ranges from 1.5 to 2.5 microns, the thickness of the second sub-pattern ranges from 0.5 to 1.5 microns, and the depth of the groove ranges from 0.2 to 0.8 microns.

Optionally, there is no overlap area between the orthographic projection of the binding pattern on the base substrate and the orthographic projection of the groove on the base substrate.

Optionally, the binding pattern is arranged around the groove.

Optionally, the binding pattern includes a first binding sub-pattern and a second binding sub-graphic that are insulated from each other, and the via includes a first via and a second via;

The first bonding sub-pattern is connected to the first power signal line in the thin film transistor through the conductive structure in the first via hole, and the second bonding sub-pattern is connected through the conductive structure in the second via hole. The conductive structure is connected to the second power signal line in the thin film transistor.

Optionally, the bonding pattern and the conductive structure in the via are arranged in the same layer.

Optionally, the thin film transistor is one of a thin film transistor with a top gate structure and a thin film transistor with a bottom gate structure.

Optionally, the binding pattern is arranged around the groove, the binding pattern includes a first binding sub-graphic and a second binding sub-graphic that are insulated from each other, and the via includes a first via and a second Two vias;

The first bonding sub-pattern is connected to the first power signal line in the thin film transistor through the conductive structure in the first via hole, and the second bonding sub-pattern is connected through the conductive structure in the second via hole. The conductive structure is connected to the second power signal line in the thin film transistor;

The bonding pattern and the conductive structure in the via hole are arranged in the same layer.

In another aspect, a display panel is provided, including: a light-emitting unit and the array substrate according to any one of the aspects;

The light-emitting unit is located on a side of the planarization pattern away from the base substrate, and the light-emitting unit is fixedly connected to the binding pattern through the adhesive in the groove of the planarization pattern.

Optionally, the light emitting unit is a micro light emitting diode, the micro light emitting diode includes a light emitting body and electrode pins protruding from the light emitting body, the light emitting body includes a first electrode and a second electrode, the electrode The pins include a first pin connected to the first electrode and a second pin connected to the second electrode;

The binding pattern is arranged around the groove, and the binding pattern includes a first binding sub-pattern and a second binding sub-pattern that are insulated from each other, and the via on the planarization pattern includes a first via And a second via, the first bonding sub-pattern is connected to the first power signal line in the thin film transistor through the conductive structure in the first via, and the second bonding sub-pattern passes through the second The conductive structure in the via hole is connected to the second power signal line in the thin film transistor;

The end of the first pin away from the light-emitting body is connected to the first binding sub-pattern, and the end of the second pin away from the light-emitting body is connected to the second binding sub-pattern.

Optionally, the side surface of the electrode pin and the side surface of the binding pattern are fixedly connected by an adhesive in the groove.

In another aspect, a display device is provided, including: the display panel as described in any one of the other aspects.

In yet another aspect, a manufacturing method of an array substrate is provided, and the method includes:

Forming a thin film transistor on the base substrate;

Forming a planarization pattern on the base substrate on which the thin film transistor is formed, the planarization pattern having a via hole and a groove, and the groove is used for accommodating an adhesive;

A bonding pattern is formed on the base substrate on which the planarization pattern is formed, and a conductive structure is formed in the via hole, so that the bonding pattern is connected to the thin film transistor through the conductive structure.

Optionally, the forming a bonding pattern on the base substrate on which the planarization pattern is formed and forming a conductive structure in the via hole includes:

The bonding pattern is formed on the base substrate with the planarization pattern formed by a conductive material through a patterning process, and the conductive structure is formed in the via hole.

In yet another aspect, a method for manufacturing a display panel is provided, and the method includes:

Provide an array substrate, the array substrate including the array substrate according to any one of the aspects;

An adhesive is arranged in the groove of the flattened pattern, so that the volume of the adhesive in the groove is greater than the volume of the groove;

Disposing the light-emitting unit on the side of the binding pattern away from the base substrate;

Melting the adhesive so that the melted adhesive contacts the light-emitting unit and the binding pattern;

The melted adhesive is cured to fix and connect the light-emitting unit and the binding pattern.

Optionally, the light emitting unit is a micro light emitting diode, the micro light emitting diode includes a light emitting body and electrode pins protruding from the light emitting body, and the light emitting unit is arranged on the binding pattern away from the base substrate The side includes:

Setting the end of the electrode pin away from the light-emitting body on the side of the binding pattern away from the base substrate;

The melting the adhesive so that the melted adhesive contacts the light-emitting unit and the binding pattern includes:

The adhesive is melted so that the melted adhesive contacts the side surface of the electrode pin and the side surface of the binding pattern.

Optionally, the adhesive has hot-melt properties, and the melting treatment of the adhesive includes:

The adhesive is melted by heating.

Optionally, the disposing an adhesive in the groove of the planarization pattern includes:

The adhesive is coated in the groove by screen printing or photolithography process.

Description of the drawings

FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure;

2 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure;

4 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure;

FIG. 5 is a schematic structural diagram of a halftone mask provided by an embodiment of the present disclosure;

6 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

FIG. 7 is a flowchart of a method for manufacturing a display panel provided by an embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram of a groove provided with an adhesive provided by an embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of a micro LED provided on the side of the binding pattern away from the base substrate according to an embodiment of the present disclosure.

detailed description

In order to make the objectives, technical solutions, and advantages of the present disclosure clearer, the following further describes the embodiments of the present disclosure in detail with reference to the accompanying drawings.

The Micro LED display panel includes an array substrate and a plurality of Micro LED arrays arranged on the array substrate, and each Micro LED can be regarded as a pixel. In related technologies, after the Micro LED is transferred and placed on the array substrate by using a transfer device, the Micro LED needs to be welded on the array substrate through a chip-level bonding process to prepare a Micro LED display panel. Since the process of disposing the Micro LED on the array substrate in the related art is relatively complicated, the manufacturing process of the Micro LED display panel is relatively complicated.

FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure. As shown in FIG. 1, the array substrate 10 includes a base substrate 101, and a thin film transistor 102, a planarization pattern 103 and a bonding pattern 104 which are stacked on the base substrate 101 in a direction away from the base substrate 101.

Referring to FIG. 1, the planarization pattern 103 has a via W and a groove H. A conductive structure 105 is provided in the via W. The bonding pattern 104 is electrically connected to the thin film transistor 102 through the conductive structure 105. The groove H is used to contain the adhesive. The adhesive in the groove H is used to fix the light-emitting unit and the binding structure 104.

Optionally, the array substrate provided by the embodiment of the present disclosure may be used to prepare a Micro LED display panel.

In summary, the array substrate provided by the embodiment of the present disclosure has via holes and grooves on the planarization pattern, and the bonding pattern can be connected to the thin film transistor through the conductive structure in the via hole. Since the groove on the planarization pattern can contain the adhesive, when the light-emitting unit is arranged on the array substrate, the light-emitting unit can be fixedly connected to the binding pattern through the adhesive in the groove. Compared with the related art, there is no need to solder the light-emitting unit on the array substrate through a soldering process, which simplifies the setting process of the light-emitting unit, thereby simplifying the preparation process of the display panel.

Optionally, the binding pattern and the conductive structure in the via hole are arranged on the same layer. Wherein, the material for preparing the binding pattern and the conductive structure includes at least one of aluminum, neodymium and molybdenum.

It should be noted that the bonding pattern and the conductive structure in the via hole are arranged in the same layer, that is, the bonding pattern and the conductive structure in the via hole can be formed by one patterning process, which simplifies the manufacturing process of the array substrate.

Optionally, the thin film transistor is one of a thin film transistor with a top gate structure and a thin film transistor with a bottom gate structure.

In one implementation, the thin film transistor is a thin film transistor with a top gate structure. For example, referring to FIG. 1, the thin film transistor 102 includes an active layer pattern 1021, a gate insulating layer 1022, a gate G, a passivation layer 1023, and source and drain patterns stacked in a direction away from the base substrate 101. The source-drain pattern includes a source S and a drain D.

In another possible implementation, the thin film transistor is a thin film transistor with a bottom gate structure. Illustratively, FIG. 2 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure. As shown in FIG. 2, the thin film transistor 102 includes a gate G, a gate insulating layer 1022, an active layer pattern 1021, and a source/drain pattern stacked in a direction away from the base substrate 101. The source-drain pattern includes a source S and a drain D.

Optionally, the thin film transistor further includes a power signal line, and the power signal line may be prepared in the same layer as the source electrode and the drain electrode, that is, the source and drain pattern may also include a power signal line. Optionally, the power signal line includes a Vdd signal line and a Vss signal line. For example, referring to FIGS. 1 and 2, the source-drain pattern includes a source S, a drain D, and a power signal line L (only one power signal line is shown in the figure).

It should be noted that the gate of the thin film transistor in the array substrate shown in FIG. 1 and FIG. 2 may also have a two-layer structure, which is not limited by the embodiment of the present disclosure. The drawings provided in the embodiment of the present disclosure are only It is used as an exemplary description and is not used to limit the specific structure of the thin film transistor.

Optionally, there is no overlap area between the orthographic projection of the binding pattern on the base substrate and the orthographic projection of the groove on the planarization pattern on the base substrate. For example, referring to FIGS. 1 and 2, the binding pattern 104 is arranged around the groove H on the planarization pattern 103.

It should be noted that since the groove on the planarization pattern is used to contain the adhesive, if the binding pattern is arranged in the groove, the part of the binding pattern located in the groove cannot be used to connect the light-emitting unit. There is no overlap area between the orthographic projection of the binding pattern on the base substrate and the orthographic projection of the groove on the planarization pattern on the base substrate, that is, no binding pattern is arranged in the groove, which can save preparation materials.

Optionally, please continue to refer to FIG. 1 and FIG. 2, the binding pattern 104 includes a first binding sub-graphic 1041 and a second binding sub-graphic 1042 that are insulated from each other. The via W includes a first via and a second via. The first bonding sub-pattern 1041 is connected to the first power signal line in the thin film transistor 102 (the first power signal line is not shown in the figure) through the conductive structure in the first via hole. The second bonding sub-pattern 1042 is connected to the second power signal line L in the thin film transistor 102 through the conductive structure in the second via hole. Optionally, the first power signal line may be connected to the drain D, or the first power signal line may also be connected to the source S, which is not limited in the embodiment of the present disclosure. Optionally, the first power signal line is used to provide a high level signal, the first power signal line is a Vdd signal line; the second power signal line is used to provide a low level signal, and the second power signal line is a Vss signal line.

Optionally, the preparation material of the gate includes at least one of aluminum (Al), neodymium (Nd), and molybdenum (Mo). The source and drain pattern preparation materials include at least one of aluminum, neodymium, and molybdenum. The preparation materials of the active layer pattern include at least one of Indium Gallium Zinc Oxide (IGZO), Low Temperature Poly-silicon (LTPS) and Low Temperature Polycrystalline Oxide (LTPO) One kind.

In the following embodiments of the present disclosure, the structure of the array substrate is further described by taking the thin film transistor in the array substrate as the top gate structure as an example.

Optionally, FIG. 3 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure. As shown in FIG. 3, the planarization pattern 103 includes a first sub-pattern 1031 and a second sub-pattern 1032 surrounding the first sub-pattern 1031. The groove H is arranged on the side of the first sub-pattern 1031 away from the base substrate 101. The via W is located in the second sub-pattern 1032. The binding pattern 104 is located on the side of the first sub-pattern 1031 away from the base substrate 101. Optionally, the thickness of the first sub-pattern 1031 is greater than the thickness of the second sub-pattern 1032.

It should be noted that the planarization pattern includes a first sub-pattern and a second sub-pattern surrounding the first sub-pattern, and the thickness of the first sub-pattern is greater than the thickness of the second sub-pattern, that is, the planarization pattern has a boss structure. By arranging the binding pattern on the boss structure, it is convenient for the subsequent alignment setting of the light-emitting unit, and the setting yield of the light-emitting unit can be improved.

Optionally, the thickness of the source/drain pattern is generally 7500 angstroms, and the thickness of the planarization pattern is greater than the thickness of the source/drain pattern. Optionally, the thickness of the first sub-pattern ranges from 1.5 to 2.5 microns. The thickness of the second sub-pattern ranges from 0.5 to 1.5 microns. The depth of the grooves ranges from 0.2 to 0.8 microns.

In summary, the array substrate provided by the embodiment of the present disclosure has via holes and grooves on the planarization pattern, and the bonding pattern can be connected to the thin film transistor through the conductive structure in the via hole. Since the groove on the planarization pattern can contain the adhesive, when the light-emitting unit is arranged on the array substrate, the light-emitting unit can be fixedly connected to the binding pattern through the adhesive in the groove. Compared with the related art, there is no need to solder the light-emitting unit on the array substrate through a soldering process, which simplifies the setting process of the light-emitting unit, thereby simplifying the preparation process of the display panel.

FIG. 4 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure. As shown in Figure 4, the method includes the following working processes:

In step 201, a thin film transistor is formed on a base substrate.

Optionally, the preparation material of the base substrate includes at least one of glass, silicon wafer, quartz and plastic, and the embodiment of the present disclosure does not limit the preparation material of the base substrate.

In step 202, a planarization pattern is formed on the base substrate on which the thin film transistor is formed, and the planarization pattern has a via hole and a groove, and the groove is used for accommodating an adhesive.

Optionally, referring to FIG. 3, the planarization pattern 103 includes a first sub-pattern 1031 and a second sub-pattern 1032 surrounding the first sub-pattern 1031. The thickness of the first sub-pattern 1031 is greater than the thickness of the second sub-pattern 1032. The groove H is arranged on the side of the first sub-pattern 1031 away from the base substrate 101.

In step 203, a bonding pattern is formed on the base substrate with the planarization pattern and a conductive structure is formed in the via hole, so that the bonding pattern is connected to the thin film transistor through the conductive structure.

In an optional embodiment of the present disclosure, when the thin film transistor is a top gate structure thin film transistor, the implementation process of the above step 201 includes the following steps:

In step 2011a, an active layer pattern is formed on the base substrate.

Optionally, the preparation material of the active layer pattern includes at least one of IGZO, LTPS, and LTPO. For example, a patterning process can be used to form the active layer pattern on the base substrate. Among them, the patterning process includes: photoresist coating, exposure, development, etching and photoresist stripping.

In step 2012a, a gate insulating layer is formed on the base substrate on which the active layer pattern is formed.

Optionally, the material for preparing the gate insulating layer includes at least one of silicon dioxide, silicon nitride, and aluminum oxide. For example, the gate insulating layer can be formed on the base substrate with the active layer pattern formed by deposition.

In step 2013a, a gate is formed on the base substrate on which the gate insulating layer is formed.

Optionally, the preparation material of the grid includes at least one of aluminum, neodymium and molybdenum. For example, a patterning process can be used to form a gate on a base substrate on which a gate insulating layer is formed.

In step 2014a, a passivation layer is formed on the base substrate on which the gate is formed.

Optionally, the preparation material of the passivation layer includes at least one of silicon dioxide, silicon nitride and aluminum oxide. For example, the passivation layer can be formed on the base substrate on which the gate is formed by deposition.

In step 2015a, source and drain patterns are formed on the base substrate on which the passivation layer is formed.

Optionally, the material for preparing the source and drain patterns includes at least one of aluminum, neodymium, and molybdenum. For example, a patterning process can be used to form the source and drain patterns on the base substrate on which the passivation layer is formed.

In another optional embodiment of the present disclosure, when the thin film transistor is a thin film transistor with a bottom gate structure, the implementation process of the foregoing step 201 includes the following steps:

In step 2011b, a gate is formed on the base substrate.

For the material and preparation method of the gate, reference may be made to the above-mentioned step 2013a, which is not repeated in the embodiment of the present disclosure.

In step 2012b, a gate insulating layer is formed on the base substrate on which the gate is formed.

For the material and preparation method of the gate, reference may be made to the above step 2012a, which is not repeated in the embodiment of the present disclosure.

In step 2013b, an active layer pattern is formed on the base substrate on which the gate insulating layer is formed.

Wherein, the material and preparation method of the gate can refer to the above step 2011a, which is not described in detail in the embodiment of the present disclosure.

In step 2014b, source and drain patterns are formed on the base substrate on which the active layer pattern is formed.

For the material and preparation method of the gate, reference may be made to the above step 2015a, which is not described in detail in the embodiment of the present disclosure.

Optionally, the implementation process of step 202 includes the following steps:

In step 2021, a planarization layer is formed on the base substrate on which the thin film transistor is formed.

Optionally, a planarization layer is formed on the base substrate on which the thin film transistor is formed by a coating process. The thickness of the planarization layer is 1.5 to 2.5 microns. For example, when the thickness of the source and drain patterns in the thin film transistor is 7500 angstroms, the thickness of the planarization layer may be 2 microns. The process for forming a planarization layer with a thickness of 2 microns is relatively mature and stable, and has a better planarization effect on the film, and the uniformity of the obtained film is higher.

In step 2022, a halftone mask combined with a patterning process is used to pattern the planarization layer to obtain a planarization pattern.

Alternatively, the planarization layer may be prepared from a photosensitive resin material. A halftone mask can be used to expose the planarization layer from the side of the planarization layer away from the base substrate. The flattened layer after the exposure treatment is developed to obtain a flattened pattern.

Illustratively, FIG. 5 is a schematic structural diagram of a halftone mask provided by an embodiment of the present disclosure. The halftone mask can be used to prepare the planarization pattern in the array substrate as shown in FIG. 3. When the material of the planarization layer is a positive light-sensitive material, as shown in FIG. 5, the halftone mask may include a first light-transmitting area T1, a second light-transmitting area T2, and a third light-transmitting area with successively decreasing light transmittances. Light area T3 and light shielding area Z. The light-shielding area Z is a ring-shaped area, the third light-transmitting area T3 is an area enclosed by the light-shielding area Z, and the second light-transmitting area T2 is located at the periphery of the light-shielding area Z. Among them, the gray scale of the halftone mask indicates the degree of light transmittance, and the deeper the gray scale, the smaller the transmittance (black means opaque), that is, the gray scale of the halftone mask Corresponding to the degree to which the photoresist layer covered by its orthographic projection on the photoresist layer needs to be exposed, the deeper the gray level indicates the weaker the degree of exposure of the planarization layer.

It should be noted that the halftone mask shown in FIG. 5 is used to expose the planarization layer, and the exposed planarization layer is developed to obtain the planarization pattern as shown in FIG. 3 . The first light-transmitting area corresponds to the via hole, the second light-transmitting area corresponds to the second sub-pattern, the third light-transmitting area corresponds to the groove, and the light-shielding area corresponds to the first sub-pattern. Optionally, the thickness of the first sub-pattern ranges from 1.5 to 2.5 microns. The thickness of the second sub-pattern ranges from 0.5 to 1.5 microns. The depth of the grooves ranges from 0.2 to 0.8 microns.

It should be noted that since the thickness of the first sub-pattern is greater than the thickness of the second sub-pattern, that is, the first sub-pattern protrudes from the second sub-pattern, the binding pattern is provided on the side of the first sub-pattern away from the base substrate. , It is convenient for the subsequent positioning of the light-emitting unit, and can improve the installation yield of the light-emitting unit.

Optionally, the implementation process of the above step 203 includes: forming a bonding pattern on the side of the first sub-pattern away from the base substrate through a patterning process using a conductive material, and forming a conductive structure in the via hole.

Optionally, the material for preparing the binding pattern and the conductive structure (ie, the aforementioned conductive material) includes at least one of aluminum, neodymium, and molybdenum. By one patterning process, a binding pattern is formed on the side of the first sub-pattern away from the base substrate, and a conductive structure is formed in the via hole, which can simplify the preparation process of the array substrate.

In summary, the manufacturing method of the array substrate provided by the embodiment of the present disclosure, in the array substrate prepared by the method, the planarization pattern has via holes and grooves, and the binding pattern can pass through the conductive structure and the groove in the via hole. Thin film transistor connection. Since the groove on the planarization pattern can contain the adhesive, when the light-emitting unit is arranged on the array substrate, the light-emitting unit can be fixedly connected to the binding pattern through the adhesive in the groove. Compared with the related art, there is no need to solder the light-emitting unit on the array substrate through a soldering process, which simplifies the setting process of the light-emitting unit, thereby simplifying the preparation process of the display panel.

An embodiment of the present disclosure provides a display panel including: a light-emitting unit and an array substrate 10 as shown in any one of FIGS. 1 to 3.

Illustratively, FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure, and the display panel includes the array substrate as shown in FIG. 3. As shown in FIG. 6, the light-emitting unit 30 is located on the side of the planarization pattern 103 away from the base substrate 101, and the light-emitting unit 30 is fixedly connected to the binding pattern by the adhesive 40 in the groove of the planarization pattern 103.

To sum up, the display panel provided by the embodiments of the present disclosure includes via holes and grooves on the planarization pattern in the array substrate, and the bonding pattern can be connected to the thin film transistor through the conductive structure in the via hole. The light-emitting unit is fixedly connected with the binding pattern through the adhesive in the groove of the planarized pattern. Compared with the related art, there is no need to solder the light-emitting unit on the array substrate through a soldering process, which simplifies the setting process of the light-emitting unit, thereby simplifying the preparation process of the display panel.

Optionally, the light emitting unit is a micro LED. Please continue to refer to FIG. 6, the micro LED 30 includes a light-emitting body 301 and electrode pins protruding from the light-emitting body 301. The light-emitting body 301 includes a first electrode and a second electrode (the electrode is not shown in the figure). The electrode pins include a first pin 3021 connected to the first electrode and a second pin 3022 connected to the second electrode. The binding pattern 104 includes a first binding sub-pattern 1041 and a second binding sub-pattern 1042 located around the groove and insulated from each other. The via W on the planarization pattern 103 includes a first via and a second via. The first bonding sub-pattern 1041 is connected to the first power signal line in the thin film transistor 102 (the first power signal line is not shown in the figure) through the conductive structure in the first via hole, and the second bonding sub-pattern 1042 passes through the first power signal line. The conductive structure in the two via holes is connected to the second power signal line L in the thin film transistor 102. An end of the first pin 3021 away from the light-emitting body 301 is connected to the first binding sub-pattern 1041. The end of the second pin 3022 away from the light-emitting body 301 is connected to the second binding sub-pattern 1042. When the first electrode of the light-emitting body is the anode and the second electrode is the cathode, the first power signal line is a Vdd signal line for providing a high-level signal, and the second power signal line is a Vss signal line for providing a low-level signal. Flat signal.

Optionally, please continue to refer to FIG. 6, the side surface of the electrode pin and the side surface of the binding pattern 104 are fixedly connected by the adhesive 40 in the groove.

It should be noted that the end of the electrode pin of the micro LED away from the light-emitting body is in direct contact with the binding pattern, which can eliminate the interference of other film layers, facilitate the overlap between the metals, and ensure the conductivity.

It should be noted that the adhesive is an insulating material. Optionally, the adhesive is one of hot melt adhesive and polyimide adhesive.

To sum up, the display panel provided by the embodiments of the present disclosure includes via holes and grooves on the planarization pattern in the array substrate, and the bonding pattern can be connected to the thin film transistor through the conductive structure in the via hole. The light-emitting unit is fixedly connected with the binding pattern through the adhesive in the groove of the planarized pattern. Compared with the related art, there is no need to solder the light-emitting unit on the array substrate through a soldering process, which simplifies the setting process of the light-emitting unit, thereby simplifying the preparation process of the display panel.

FIG. 7 is a flowchart of a manufacturing method of a display panel provided by an embodiment of the present disclosure. As shown in Figure 7, the method includes the following working processes:

In step 501, an array substrate is provided.

Optionally, the array substrate includes the array substrate shown in any one of FIGS. 1 to 3. The manufacturing method of the array substrate and the structure and material of each film layer can refer to the above-mentioned embodiment of the structure and manufacturing method of the array substrate, which is not repeated in the embodiments of the present disclosure.

In step 502, an adhesive is arranged in the groove of the planarized pattern, so that the volume of the adhesive in the groove is greater than the volume of the groove.

Illustratively, FIG. 8 is a schematic structural diagram of a groove provided with an adhesive provided in an embodiment of the present disclosure. As shown in FIG. 8, by providing an adhesive 40 with a height greater than the depth of the groove H in the groove H, the volume of the adhesive 40 is greater than the volume of the groove H. It should be noted that the adhesive is arranged in the groove of the planarization pattern to fix the position of the adhesive, prevent the adhesive from flowing to the surface of the binding pattern, and affect the contact between the light-emitting unit and the binding pattern.

Optionally, an adhesive is coated in the grooves of the planarization pattern by screen printing or photolithography. When the depth of the groove is in the range of 0.2 to 0.8 microns, the height of the adhesive can be in the range of 2.5 to 4 microns. It should be noted that by providing an adhesive whose height is greater than the depth of the groove, it is convenient to fix the light-emitting unit later. The adhesive can be accurately set in the groove through the alignment platform.

Optionally, when the adhesive is coated in the grooves of the planarization pattern by screen printing, the thickness of the applied adhesive can be controlled by the amount of glue applied by screen printing. When the adhesive is coated in the grooves of the planarized pattern through a photolithography process, the thickness of the applied adhesive can be controlled by the amount of glue dispensed in the photolithography process.

It should be noted that the selected adhesive needs to have a certain viscosity to adhere the array substrate and the light-emitting unit, and the adhesive is an insulating material. In addition, the binder must have fluidity under certain conditions. For example, the adhesive is in a fluid state after heating. Optionally, the adhesive is one of hot melt adhesive and polyimide adhesive.

In step 503, the light emitting unit is arranged on the side of the binding pattern away from the base substrate.

Optionally, the light emitting unit is a micro LED, and the micro LED includes a light emitting body and electrode pins protruding from the light emitting body. The implementation process of step 503 includes: setting the end of the electrode pin away from the light-emitting body on the side of the binding pattern away from the base substrate. Since the height of the adhesive is greater than the depth of the groove, the micro LED can be arranged on the side of the binding pattern away from the base substrate by pressing and attaching. The precise alignment of the light-emitting unit and the bound graphics can be achieved through the alignment platform.

It should be noted that the end of the electrode pin of the micro LED away from the light-emitting body is in direct contact with the binding pattern, which can eliminate the interference of other film layers, facilitate the overlap between the metals, and ensure the conductivity.

For example, FIG. 9 is a schematic structural diagram of a micro LED provided on a side of the binding pattern away from the base substrate provided by an embodiment of the present disclosure. As shown in FIG. 9, the light-emitting body 301 in the micro LED 30 can be preliminarily fixed to the array substrate by the adhesive 40 to avoid misalignment of the electrode pins of the micro LED 30 and the binding pattern 104 in the subsequent process, resulting in poor contact.

In step 504, the adhesive is melted so that the melted adhesive contacts the light-emitting unit and the binding pattern.

Optionally, the implementation process of step 504 includes: melting the adhesive so that the heated and melted adhesive contacts the side surface of the electrode pin and the side surface of the binding pattern. Optionally, the adhesive has hot melt properties. The adhesive can be melted by heating.

Optionally, in the process of melting the adhesive, a certain pressure is applied to the micro LED on the side of the binding pattern away from the base substrate to ensure that the electrode pins of the micro LED are in contact with the binding pattern and Counterpoint. The adhesive will collapse after being heated, and the collapsed adhesive will contact the side of the electrode pin and the side of the binding pattern without affecting the contact between the electrode pin and the binding pattern, thereby realizing the effective binding of the micro LED set.

In step 505, the melted adhesive is cured to fix and connect the light-emitting unit and the binding pattern.

Optionally, after the adhesive contacts the side of the electrode pin and the side of the binding pattern, the adhesive is cooled and solidified to fix the connection of the light-emitting unit and the binding pattern. Illustratively, the display panel shown in FIG. 6 can be prepared by using the above method.

In summary, in the method for manufacturing the display panel provided by the embodiments of the present disclosure, the planarization pattern in the array substrate has via holes and grooves, and the bonding pattern can be connected to the thin film transistor through the conductive structure in the via hole. The light-emitting unit is fixedly connected with the binding pattern through the adhesive in the groove of the planarization pattern. Compared with the related art, the light-emitting unit does not need to be welded on the array substrate through a soldering process, thus simplifying the setting process of the light-emitting unit and thus The preparation process of the display panel can be simplified. In addition, the cost of the adhesive is low, so the manufacturing cost of the display panel can be saved. By adopting the manufacturing method of the display panel provided by the embodiments of the present disclosure, multiple micro LEDs can be aligned with the corresponding binding patterns, and the adhesive can be uniformly heated, so that the adhesive is fixedly connected to the corresponding micro LEDs and the binding patterns. By setting the pattern, the massive transfer of the micro LED can be realized and the transfer efficiency of the micro LED can be improved.

It should be noted that the sequence of steps in the manufacturing method of the array substrate and the manufacturing method of the display panel provided by the embodiments of the present disclosure can be adjusted appropriately, and the steps can also be increased or decreased accordingly according to the situation. Anyone skilled in the art is familiar with Within the technical scope disclosed in the present disclosure, various methods that can be easily conceived should be covered by the protection scope of the present disclosure, and therefore will not be repeated.

The structure in the foregoing method embodiment has been described in detail in the relevant structure-side embodiment, and detailed description will not be given here.

The embodiment of the present disclosure also provides a display device, which may include a display panel as shown in FIG. 6.

Optionally, the display device provided by the embodiment of the present disclosure may be any product or component with display function such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, and navigator.

It should be noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or intervening layers may be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element, or there may be more than one intervening layer or element. In addition, it can also be understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or elements, or more than one intervening layer may also be present. Or components. Similar reference numerals indicate similar elements throughout.

In the embodiments of the present disclosure, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance. The term "plurality" refers to two or more, unless specifically defined otherwise.

The term "and/or" in the embodiments of the present disclosure is merely an association relationship describing associated objects, indicating that there can be three types of relationships, for example, A and/or B, which can mean that there is A alone, and both A and B, there are three cases of B alone. In addition, the character "/" in this text generally indicates that the associated objects before and after are in an "or" relationship.

The above are only optional embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the concept and principle of the present disclosure shall be included in the protection of the present disclosure. Within range.

Claims (20)

An array substrate, including: A base substrate (101), and a thin film transistor (102), a planarization pattern (103) and a bonding pattern (10) stacked on the base substrate (101) in a direction away from the base substrate (101) 104); The planarization pattern (103) has a via hole and a groove, a conductive structure (105) is arranged in the via hole, and the bonding pattern (104) passes through the conductive structure (105) and the thin film transistor ( 102) Connection, the groove is used to contain the adhesive. The array substrate according to claim 1, wherein the planarization pattern (103) comprises a first sub-pattern (1031) and a second sub-pattern (1032) surrounding the first sub-pattern (1031); The groove is located on the side of the first sub-pattern (1031) away from the base substrate (101), the via hole is located in the second sub-pattern (1032), and the binding pattern (104 ) Is located on the side of the first sub-pattern (1031) away from the base substrate (101). The array substrate according to claim 2, wherein the thickness of the first sub-pattern (1031) is greater than the thickness of the second sub-pattern (1032). The array substrate according to claim 2 or 3, wherein the thickness of the first sub-pattern (1031) is in the range of 1.5 to 2.5 microns, the thickness of the second sub-pattern (1032) is in the range of 0.5 to 1.5 microns, and the The depth of the grooves ranges from 0.2 to 0.8 microns. The array substrate according to any one of claims 1 to 4, the orthographic projection of the binding pattern (104) on the base substrate (101) and the groove on the base substrate (101) There is no overlap area in the orthographic projection. The array substrate according to claim 5, wherein the binding pattern (104) is arranged around the groove. The array substrate according to any one of claims 1 to 6, wherein the bonding pattern (104) comprises a first bonding sub-pattern (1041) and a second bonding sub-pattern (1042) that are insulated from each other, and the via Including a first via hole and a second via hole; The first bonding sub-pattern (1041) is connected to the first power signal line in the thin film transistor (102) through the conductive structure in the first via, and the second bonding sub-pattern (1042) It is connected to the second power signal line in the thin film transistor (102) through the conductive structure in the second via hole. The array substrate according to any one of claims 1 to 7, wherein the bonding pattern (104) and the conductive structure (105) in the via are arranged in the same layer. The array substrate according to any one of claims 1 to 8, wherein the thin film transistor (102) is one of a thin film transistor with a top gate structure and a thin film transistor with a bottom gate structure. The array substrate according to claim 3, wherein the binding pattern (104) is arranged around the groove, and the binding pattern (104) includes a first binding sub-pattern (1041) and a second binding sub-pattern (1041) and a second binding sub-pattern (1041) insulated from each other. The stator pattern (1042), the vias include a first via and a second via; The first bonding sub-pattern (1041) is connected to the first power signal line in the thin film transistor (102) through the conductive structure (105) in the first via hole, and the second bonding sub-pattern (1042) Connect with the second power signal line in the thin film transistor (102) through the conductive structure (105) in the second via; The bonding pattern (104) and the conductive structure (105) in the via hole are arranged in the same layer. A display panel, comprising: a light-emitting unit (30) and the array substrate (10) according to any one of claims 1 to 10; The light-emitting unit (30) is located on a side of the planarization pattern (103) away from the base substrate (101), and the light-emitting unit (30) passes through the adhesive (30) in the groove of the planarization pattern (103). 40) Fixed connection with the binding graphic (104). The display panel according to claim 11, the light emitting unit (30) is a micro light emitting diode, the micro light emitting diode includes a light emitting body (301) and electrode pins protruding from the light emitting body (301), so The light-emitting body (301) includes a first electrode and a second electrode, and the electrode pins include a first pin (3021) connected to the first electrode and a second pin (3021) connected to the second electrode. 3022); The binding pattern (104) is arranged around the groove, and the binding pattern (104) includes a first binding sub-graphic (1041) and a second binding sub-graphic (1042) that are insulated from each other. The via hole on the planarization pattern (103) includes a first via hole and a second via hole. The first bonding sub-pattern (1041) passes through the conductive structure (105) and the thin film transistor ( 102) is connected to the first power signal line, the second bonding sub-pattern (1042) is connected to the second power signal in the thin film transistor (102) through the conductive structure (105) in the second via hole Wire connection One end of the first pin (3021) away from the light-emitting body (301) is connected to the first binding sub-pattern (1041), and the second pin (3022) is away from the light-emitting body (301) One end of is connected to the second binding sub-graphic (1042). The display panel according to claim 12, wherein the side surface of the electrode pin and the side surface of the binding pattern (104) are fixedly connected by an adhesive (40) in the groove. A display device, comprising: the display panel according to any one of claims 11 to 13. A manufacturing method of an array substrate, the method comprising: Forming a thin film transistor on the base substrate; Forming a planarization pattern on the base substrate on which the thin film transistor is formed, the planarization pattern having a via hole and a groove, and the groove is used for accommodating an adhesive; A bonding pattern is formed on the base substrate on which the planarization pattern is formed, and a conductive structure is formed in the via hole, so that the bonding pattern is connected to the thin film transistor through the conductive structure. 15. The method of claim 15, wherein the forming a bonding pattern on the base substrate with the planarization pattern and forming a conductive structure in the via hole comprises: The bonding pattern is formed on the base substrate with the planarization pattern formed by a conductive material through a patterning process, and the conductive structure is formed in the via hole. A method for manufacturing a display panel, the method includes: Provide an array substrate, the array substrate comprising the array substrate according to any one of claims 1 to 10; An adhesive is arranged in the groove of the flattened pattern, so that the volume of the adhesive in the groove is greater than the volume of the groove; Disposing the light-emitting unit on the side of the binding pattern away from the base substrate; Melting the adhesive so that the melted adhesive contacts the light-emitting unit and the binding pattern; The melted adhesive is cured to fix and connect the light-emitting unit and the binding pattern. The method according to claim 17, wherein the light-emitting unit is a micro light-emitting diode, the micro light-emitting diode comprises a light-emitting body and electrode pins protruding from the light-emitting body, and the light-emitting unit is arranged in a binding pattern away from One side of the base substrate includes: Setting the end of the electrode pin away from the light-emitting body on the side of the binding pattern away from the base substrate; The melting the adhesive so that the melted adhesive contacts the light-emitting unit and the binding pattern includes: The adhesive is melted so that the melted adhesive contacts the side surface of the electrode pin and the side surface of the binding pattern. The method according to claim 17 or 18, wherein the adhesive has hot-melt properties, and the melting treatment of the adhesive comprises: The adhesive is melted by heating. 17. The method according to any one of claims 17 to 19, wherein the placing the adhesive in the grooves of the planarization pattern comprises: The adhesive is coated in the groove by screen printing or photolithography process.

Images