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WO2019171666A1 - Dispositif à semi-conducteur, convertisseur de puissance électrique et procédé de production de dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur, convertisseur de puissance électrique et procédé de production de dispositif à semi-conducteur Download PDF

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Publication number
WO2019171666A1
WO2019171666A1 PCT/JP2018/042867 JP2018042867W WO2019171666A1 WO 2019171666 A1 WO2019171666 A1 WO 2019171666A1 JP 2018042867 W JP2018042867 W JP 2018042867W WO 2019171666 A1 WO2019171666 A1 WO 2019171666A1
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WIPO (PCT)
Prior art keywords
main surface
thickness
insulating layer
semiconductor device
main
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2018/042867
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English (en)
Japanese (ja)
Inventor
祥 小杉
麻緒 澤川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2019520761A priority Critical patent/JP6639740B1/ja
Publication of WO2019171666A1 publication Critical patent/WO2019171666A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H10W40/10—
    • H10W70/60—
    • H10W74/01—
    • H10W74/10—
    • H10W74/40—
    • H10W90/00—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the present invention relates to a semiconductor device, a power conversion device, and a method for manufacturing a semiconductor device.
  • Patent Document 1 discloses a semiconductor device including an insulating wiring substrate, a power semiconductor element, and an insulating film.
  • the insulated wiring board includes an insulated substrate and a conductor layer formed on the insulated substrate.
  • the power semiconductor element is mounted on an insulating wiring board.
  • the insulating film is formed on the conductor layer.
  • the present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device capable of increasing a dielectric breakdown voltage. Another object of the present invention is to provide a power converter that can increase the breakdown voltage.
  • the semiconductor device of the present invention includes an insulating circuit board, a semiconductor element, and an insulating layer.
  • the insulated circuit board includes an insulated substrate and a conductor layer.
  • the insulating substrate includes a first main surface and a second main surface opposite to the first main surface.
  • the conductor layer is provided on the first main surface of the insulating substrate.
  • the conductor layer includes a main body portion and a protruding portion.
  • the main body includes a third main surface that contacts the first main surface, a fourth main surface opposite to the third main surface, and a first side surface that connects the third main surface and the fourth main surface. Including.
  • the protruding portion protrudes from the first side surface.
  • the projecting portion connects the fifth main surface contacting the first main surface, the sixth main surface opposite to the fifth main surface, the fifth main surface and the sixth main surface, and the first main surface.
  • the first thickness of the protrusion defined by the first distance between the fifth main surface and the sixth main surface is the main body defined by the second distance between the third main surface and the fourth main surface. Less than the second thickness.
  • the semiconductor element is bonded to the conductor layer.
  • the insulating layer is formed on the fourth main surface, the first side surface, the sixth main surface, and the second side surface. Formed by the third thickness of the insulating layer at the first convex corner of the main body formed by the intersection of the fourth main surface and the first side surface, and the fifth main surface and the second side surface Of the insulating layer at the third convex corner of the protrusion formed by the fourth thickness of the insulating layer at the second convex corner of the protruding portion intersecting the sixth main surface and the second side surface.
  • Each of the fifth thicknesses is larger than the sixth thickness of the insulating layer formed on the fourth main surface other than the first convex corners.
  • the method for manufacturing a semiconductor device of the present invention includes bonding a semiconductor element to a conductor layer of an insulated circuit board.
  • the insulated circuit board includes an insulated substrate and a conductor layer.
  • the insulating substrate includes a first main surface and a second main surface opposite to the first main surface.
  • the conductor layer is provided on the first main surface of the insulating substrate.
  • the conductor layer includes a main body portion and a protruding portion.
  • the main body includes a third main surface that contacts the first main surface, a fourth main surface opposite to the third main surface, and a first side surface that connects the third main surface and the fourth main surface. Including.
  • the protruding portion protrudes from the first side surface.
  • the projecting portion connects the fifth main surface contacting the first main surface, the sixth main surface opposite to the fifth main surface, the fifth main surface and the sixth main surface, and the first main surface.
  • the first thickness of the protrusion defined by the first distance between the fifth main surface and the sixth main surface is the main body defined by the second distance between the third main surface and the fourth main surface. Less than the second thickness.
  • the method for manufacturing a semiconductor device of the present invention further includes forming an insulating layer on the fourth main surface, the first side surface, the sixth main surface, and the second side surface. Formed by the third thickness of the insulating layer at the first convex corner of the conductor layer formed by the intersection of the fourth main surface and the first side surface, and the fifth main surface and the second side surface Of the insulating layer at the third convex corner of the protrusion formed by the fourth thickness of the insulating layer at the second convex corner of the protruding portion intersecting the sixth main surface and the second side surface.
  • Each of the fifth thicknesses is larger than the sixth thickness of the insulating layer formed on the fourth main surface other than the first convex corners.
  • the power conversion device of the present invention includes a main conversion circuit and a control circuit.
  • the main conversion circuit includes the semiconductor device of the first embodiment, and is configured to convert input power and output the converted power.
  • the control circuit is configured to output a control signal for controlling the main conversion circuit to the main conversion circuit.
  • the insulating layer is locally thickly formed on the first convex corner of the main body and the second convex corner and the third convex corner of the protrusion.
  • the breakdown voltage of the semiconductor device and the power conversion device of the present invention increases. According to the method for manufacturing a semiconductor device of the present invention, a semiconductor device having an increased breakdown voltage can be manufactured. During the use of the semiconductor device, the occurrence of dielectric breakdown in the insulating layer can be suppressed.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment.
  • 2 is a schematic partial enlarged cross-sectional view of a region II shown in FIG. 1 of the semiconductor device according to the first embodiment.
  • FIG. FIG. 3 is a diagram showing a flowchart of a method for manufacturing a semiconductor device according to the first embodiment.
  • it is a figure which shows the electric field strength distribution formed around the 1st conductor layer when forming an insulating layer on the 1st conductor layer and the 2nd conductor layer by the electrodeposition method. .
  • a 1st comparative example when forming an insulating layer on a 1st conductor layer and a 2nd conductor layer by an electrodeposition method, it is a figure which shows electric field strength distribution formed around the 1st conductor layer.
  • a 2nd comparative example when forming an insulating layer on the 1st conductor layer and the 2nd conductor layer by an electrodeposition method, it is a figure showing electric field strength distribution formed around the 1st conductor layer.
  • a 3rd comparative example when forming an insulating layer on a 1st conductor layer and a 2nd conductor layer by an electrodeposition method, it is a figure showing electric field strength distribution formed around the 1st conductor layer.
  • FIG. 6 is a block diagram showing a configuration of a power conversion system according to Embodiment 2.
  • Embodiment 1 FIG. A semiconductor device 1 according to the first embodiment will be described with reference to FIGS.
  • the semiconductor device 1 mainly includes an insulating circuit substrate 10, semiconductor elements 20 and 20 a, and an insulating layer 14.
  • the semiconductor device 1 may further include a sealing member 37.
  • the semiconductor device 1 may further include a case 30.
  • the semiconductor device 1 may further include an insulating layer 14b.
  • the semiconductor device 1 may be a power semiconductor module including power semiconductor elements as the semiconductor elements 20 and 20a.
  • the insulated circuit board 10 includes an insulated substrate 11 and a first conductor layer 12.
  • the insulating substrate 11 includes a first main surface 11a and a second main surface 11b opposite to the first main surface 11a.
  • the insulating substrate 11 is not particularly limited, but may be made of aluminum nitride (AlN).
  • the first main surface 11 a is the front surface of the insulating substrate 11, and the second main surface 11 b is the back surface of the insulating substrate 11.
  • the first conductor layer 12 is provided on the first main surface 11 a of the insulating substrate 11.
  • the first conductor layer 12 is not particularly limited, but may be made of copper or aluminum.
  • the first conductor layer 12 includes a main body portion 15 and a protruding portion 16.
  • the main body 15 includes a third main surface 15a that contacts the first main surface 11a, a fourth main surface 15b opposite to the third main surface 15a, a third main surface 15a, and a fourth main surface 15b. And a first side surface 15c to be connected.
  • the main body 15 includes a first convex corner 15d formed by the fourth main surface 15b and the first side 15c intersecting each other.
  • the main body portion 15 includes a first ridge line 15i formed by the fourth main surface 15b and the first side surface 15c intersecting each other.
  • the third main surface 15 a is the back surface of the main body 15, and the fourth main surface 15 b is the front surface of the main body 15.
  • the protruding portion 16 protrudes from the first side surface 15 c of the main body portion 15.
  • the protruding length L of the protruding portion 16 from the first side surface 15c may be, for example, 100 ⁇ m or more, 200 ⁇ m or more, or 500 ⁇ m or more.
  • the protruding length L of the protruding portion 16 from the first side surface 15c may be, for example, 800 ⁇ m or less.
  • the protrusion 16 includes a fifth main surface 16a that contacts the first main surface 11a, a sixth main surface 16b opposite to the fifth main surface 16a, a fifth main surface 16a, and a sixth main surface 16b.
  • the second side surface 16c is connected and is opposite to the first side surface 15c.
  • the fourth main surface 15 b is formed on the entire outer periphery of the main body 15 in a plan view.
  • the fifth main surface 16 a is the back surface of the protrusion 16
  • the sixth main surface 16 b is the front surface of the protrusion 16.
  • the protrusion 16 includes a second convex corner 16d formed by the intersection of the fifth main surface 16a and the second side 16c.
  • the protrusion 16 includes a second ridge line 16i formed by the intersection of the fifth main surface 16a and the second side surface 16c.
  • the protrusion 16 includes a third convex corner 16e formed by the sixth main surface 16b and the second side 16c intersecting each other.
  • the protrusion 16 includes a third ridge line 16j formed by the sixth main surface 16b and the second side surface 16c intersecting each other.
  • the first thickness t 1 of the protrusion 16 defined by the first distance between the fifth main surface 16a and the sixth main surface 16b is the second thickness between the third main surface 15a and the fourth main surface 15b. It is smaller than the second thickness t 2 of the main body 15 defined by the distance.
  • the first thickness t 1 may be, for example, 40 ⁇ m or less, or 20 ⁇ m or less.
  • the semiconductor elements 20 and 20a may be power semiconductor elements such as insulated gate bipolar transistors (IGBTs) or metal oxide semiconductor field effect transistors (MOSFETs).
  • the semiconductor elements 20 and 20a may be diodes such as freewheeling diodes.
  • the semiconductor elements 20 and 20a may be formed of a semiconductor material such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN).
  • the semiconductor elements 20 and 20a are joined to the first conductor layer 12 via conductive joining members 21 and 21a such as solder, respectively.
  • the insulating layer 14 may be, for example, a polyimide resin layer or an epoxy resin layer.
  • the insulating layer 14 is formed on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c.
  • the insulating layer 14 may be continuously formed on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c.
  • the third thickness t 3 of the insulating layer 14 in the first convex corner 15d of the main body 15 is the sixth thickness of the insulating layer 14 formed on the fourth major surface 15b other than the first convex corner 15d. greater than the thickness t 6.
  • the third thickness t 3 of the insulating layer 14 is defined as the shortest distance between the first ridge line 15 i of the main body 15 and the surface of the insulating layer 14.
  • the fourth thickness t 4 of the insulating layer 14 in the second convex corner portion 16d of the protruding portion 16 is the sixth thickness of the insulating layer 14 formed on the fourth major surface 15b other than the first convex corner portion 15d. greater than the thickness t 6.
  • the fourth thickness t 4 of the insulating layer 14 is defined as the shortest distance between the second ridge line 16 i of the protruding portion 16 and the surface of the insulating layer 14.
  • the fifth thickness t 5 of the insulating layer 14 in the third convex corner 16e of the protrusion 16 is the sixth thickness of the insulating layer 14 formed on the fourth major surface 15b other than the first convex corner 15d. greater than the thickness t 6.
  • the fourth thickness t 4 of the insulating layer 14 is defined as the shortest distance between the third ridge line 16 j of the protrusion 16 and the surface of the insulating layer 14.
  • the third thickness t 3 is the seventh thickness t 7 of the insulating layer 14 formed on the first side surface 15c other than the first convex corner 15d and the third thickness t 3 other than the third convex corner 16e. It may be larger than the eighth thickness t 8 of the insulating layer 14 formed on the six major surfaces 16b.
  • the fourth thickness t 4 is the seventh thickness t 7 of the first convex corner portion 15d other than the first side surface 15c insulating layer formed on 14, and, other than the third convex corners 16e first It may be larger than the eighth thickness t 8 of the insulating layer 14 formed on the six major surfaces 16b.
  • the seventh thickness t 7 of the first convex corner portion 15d other than the first side surface 15c insulation layer formed on 14, and, other than the third convex corners 16e first It may be larger than the eighth thickness t 8 of the insulating layer 14 formed on the six major surfaces 16b.
  • the insulating layer 14 formed on the first convex corner portion 15 d has the same cross-sectional shape over the entire outer periphery of the main body portion 15.
  • the cross section is a cross section perpendicular to the fourth major surface 15b and the first side surface 15c.
  • the insulating layer 14 formed on the second convex corner portion 16 d has the same cross-sectional shape over the entire outer periphery of the protruding portion 16.
  • the insulating layer 14 formed on the third convex corner portion 16 e has the same cross-sectional shape over the entire outer periphery of the protruding portion 16.
  • the cross section is a cross section perpendicular to the sixth main surface 16b and the first side surface 15c.
  • the insulated circuit board 10 may further include a second conductor layer 13.
  • the second conductor layer 13 is provided on the second main surface 11 b of the insulating substrate 11.
  • the second conductor layer 13 may be configured in the same manner as the first conductor layer 12.
  • the second conductor layer 13 may include a main body portion 17 and a protruding portion 18.
  • the insulating layer 14 b may be formed on the main body portion 17 and the protruding portion 18 of the second conductor layer 13.
  • the insulating layer 14 b has the same cross-sectional shape over the entire outer periphery of the main body portion 17.
  • the insulating layer 14 b has the same cross-sectional shape over the entire outer periphery of the protrusion 18.
  • the insulating layer 14b may be, for example, a polyimide resin layer or an epoxy resin layer.
  • the case 30 may include a base portion 31, an outer enclosure 32, and a lid portion 35.
  • the outer enclosure 32 is connected to the base portion 31 and the lid portion 35.
  • the base portion 31, the envelope 32, and the lid portion 35 may be made of a resin having electrical insulation properties such as polyphenylene sulfide (PPS) resin.
  • PPS polyphenylene sulfide
  • the insulated circuit board 10 may be bonded to the base portion 31.
  • the second conductor layer 13 of the insulated circuit board 10 may be bonded to the base portion 31 via the adhesive layer 28.
  • the adhesive layer 28 may be made of a resin adhesive such as a silicone resin adhesive.
  • the case 30 may further include lead terminals 33 and 33a.
  • the semiconductor elements 20 and 20a may be electrically connected to the lead terminals 33 and 33a through the conductive wires 22a, 22b, 22c, and 22d.
  • the conductive wire 22a may be connected to the lead terminal 33 and the first conductor layer 12 using a conductive bonding member (not shown) such as solder.
  • the conductive wire 22b may be connected to the first conductor layer 12 and the semiconductor element 20 using a conductive bonding member (not shown) such as solder.
  • the conductive wire 22c may be connected to the semiconductor element 20 and the semiconductor element 20a using a conductive bonding member (not shown) such as solder.
  • the conductive wire 22d may be connected to the semiconductor element 20a and the lead terminal 33a using a conductive bonding member (not shown) such as solder.
  • the lead terminals 33 and 33 a are connected to a power source (not shown) arranged outside the case 30.
  • the semiconductor device 1 may further include a sealing member 37.
  • the sealing member 37 seals the semiconductor elements 20, 20 a, the main body portion 15, and the protruding portion 16.
  • the sealing member 37 may further seal the insulating substrate 11.
  • the sealing member 37 may seal the conductive wires 22a, 22b, 22c, and 22d.
  • the sealing member 37 has electrical insulation.
  • the sealing member 37 may be an insulating silicone gel.
  • the insulating layer 14 has a higher withstand voltage than the sealing member 37.
  • the manufacturing method of the semiconductor device 1 according to the present embodiment includes bonding the semiconductor elements 20 and 20a to the first conductor layer 12 of the insulating circuit substrate 10 (S1).
  • the insulated circuit board 10 includes an insulated substrate 11 and a first conductor layer 12.
  • the insulating substrate 11 includes a first main surface 11a and a second main surface 11b opposite to the first main surface 11a.
  • the first conductor layer 12 is provided on the first main surface 11 a of the insulating substrate 11.
  • the first conductor layer 12 includes a main body portion 15 and a protruding portion 16.
  • the main body 15 includes a third main surface 15a that contacts the first main surface 11a, a fourth main surface 15b opposite to the third main surface 15a, a third main surface 15a, and a fourth main surface 15b. And a first side surface 15c to be connected.
  • the protruding portion 16 protrudes from the first side surface 15c.
  • the protrusion 16 includes a fifth main surface 16a that contacts the first main surface 11a, a sixth main surface 16b opposite to the fifth main surface 16a, a fifth main surface 16a, and a sixth main surface 16b.
  • the second side surface 16c is connected and is opposite to the first side surface 15c.
  • the first thickness t 1 of the protrusion 16 defined by the first distance between the fifth main surface 16a and the sixth main surface 16b is the second thickness between the third main surface 15a and the fourth main surface 15b. It is smaller than the second thickness t 2 of the main body 15 defined by the distance.
  • the insulating layer 14 is formed by using the fourth main surface 15 b and the first side surface 15 c of the main body 15 and the sixth main surface 16 b of the protruding portion 16. And forming on the second side surface 16c (S2).
  • the insulating layer 14 may be, for example, a polyimide resin layer or an epoxy resin layer.
  • the third thickness t 3 of the insulating layer 14 in the first convex corner 15d of the first conductor layer 12 is on the fourth major surface 15b other than the first convex corner 15d. It is larger than the sixth thickness t 6 of the formed insulating layer 14.
  • the fourth thickness t 4 of the insulating layer 14 in the second convex corner portion 16d of the protruding portion 16 is the sixth thickness of the insulating layer 14 formed on the fourth major surface 15b other than the first convex corner portion 15d. greater than the thickness t 6.
  • the fifth thickness t 5 of the insulating layer 14 in the third convex corner 16e of the protrusion 16 is the sixth thickness of the insulating layer 14 formed on the fourth major surface 15b other than the first convex corner 15d. greater than the thickness t 6.
  • the third thickness t 3 is the seventh thickness t 7 of the insulating layer 14 formed on the first side surface 15c other than the first convex corner 15d and the third thickness t 3 other than the third convex corner 16e. It may be larger than the eighth thickness t 8 of the insulating layer 14 formed on the six major surfaces 16b.
  • the fourth thickness t 4 is the seventh thickness t 7 of the first convex corner portion 15d other than the first side surface 15c insulating layer formed on 14, and, other than the third convex corners 16e first It may be larger than the eighth thickness t 8 of the insulating layer 14 formed on the six major surfaces 16b.
  • the seventh thickness t 7 of the first convex corner portion 15d other than the first side surface 15c insulating layer formed on 14, and, other than the third convex corners 16e first It may be larger than the eighth thickness t 8 of the insulating layer 14 formed on the six major surfaces 16b.
  • Forming the insulating layer 14 includes forming the insulating layer 14 on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c by electrodeposition, Insulating layer 14 may be heat cured. Specifically, the insulated circuit board 10 on which the semiconductor elements 20 and 20a are mounted is immersed in an electrodeposition bath (not shown) containing a solution containing an insulating material constituting the insulating layer 14. Then, a voltage is applied between the first conductor layer 12 and the solution. This voltage may be a pulse voltage. Thus, the insulating layer 14 is simultaneously formed on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c. Then, the insulating layer 14 is heat cured.
  • the protrusion 16 when the insulating layer 14 is formed on the first conductor layer 12 by the electrodeposition method, the first convex corner 15d of the main body 15 and the second convex corner 16d of the protruding portion 16 are used. And the electric field concentrates on the third convex corner 16e. A high electric field is locally applied to the first convex corner 15d of the main body 15 and the second convex corner 16d and the third convex corner 16e of the protrusion 16 (see FIG. 4). . Therefore, a thicker insulating layer 14 is selectively formed on the first convex corner 15d of the main body 15 and the second convex corner 16d and the third convex corner 16e of the protrusion 16. Is done. In the example of the present embodiment shown in FIG. 4, the protrusion 16 has a protrusion length L of 0.1 mm and a first thickness t 1 of 10 ⁇ m.
  • the first conductor layer 12 does not include the protruding portion 16.
  • the insulating layer 14 is formed on the first conductor layer 12 by the electrodeposition method, a sufficiently high voltage is not applied to the convex corner portion 15g of the first conductor layer 12 in contact with the insulating substrate 11.
  • the thick insulating layer 14 is not formed on the convex corner portion 15 g of the first conductor layer 12. Therefore, when a high voltage is applied to the semiconductor elements 20 and 20a in the usage state of the semiconductor device of the first comparative example, creeping discharge is generated from the convex corners 15g of the first conductor layer 12, and the insulating layer 14 Dielectric breakdown sometimes occurred.
  • the protrusion 16 has a protrusion length L of 0.1 mm and a first thickness t 1 of 50 ⁇ m.
  • the insulating layer 14 is formed on the first conductor layer 12 by the electrodeposition method, a sufficiently high voltage is not applied to the second convex corner 16d of the protrusion 16.
  • the thick insulating layer 14 is not formed on the second convex corner 16d of the protrusion 16. Therefore, when a high voltage is applied to the semiconductor elements 20 and 20a in the usage state of the semiconductor device of the second comparative example, creeping discharge is generated from the second convex corner portion 16d of the protruding portion 16, and the insulating layer 14 Dielectric breakdown sometimes occurred.
  • the protruding portion 16 has a protruding length L of 1.0 mm and a first thickness t 1 of 10 ⁇ m.
  • the insulating layer 14 when the insulating layer 14 is formed on the first conductor layer 12 by the electrodeposition method, a sufficiently high voltage is not applied to the first convex corner portion 15d of the main body portion 15.
  • the thick insulating layer 14 is not formed on the first convex corner 15 d of the main body 15. Therefore, when a high voltage is applied to the semiconductor elements 20 and 20a in the usage state of the semiconductor device of the third comparative example, creeping discharge is generated from the first convex corner portion 15d of the main body portion 15, and the insulating layer 14 may have a dielectric breakdown.
  • the protruding length L of the protruding portion 16 from the first side surface 15c is 100 ⁇ m or more and the first thickness t 1 is 20 ⁇ m or less
  • the first protruding corner portion 15d of the main body portion 15 and the protruding portion An electric field having an electric field strength of 0.2 kV / mm or more is generated in the 16 second convex corners 16d and the third convex corners 16e.
  • the protrusion length L of the protrusion 16 from the first side surface 15c is 500 ⁇ m or more and the first thickness t 1 is 40 ⁇ m or less
  • the first convex corner 15d of the main body 15 and An electric field having an electric field strength of 0.2 kV / mm or more is generated in the second convex corner portion 16d and the third convex corner portion 16e of the protruding portion 16. Therefore, the insulating layer 14 is locally thickly formed on the first convex corner 15d of the main body 15 and the second convex corner 16d and the third convex corner 16e of the protrusion 16.
  • the breakdown voltage of the semiconductor device 1 increases. Even when a high voltage is applied to the semiconductor elements 20 and 20a in the usage state of the semiconductor device 1, the occurrence of dielectric breakdown in the insulating layer 14 can be suppressed.
  • Forming the insulating layer 14 on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c means that the fourth main surface 15b, the first side surface 15c, and the sixth It may include removing the oxide layer on the surface of the first conductor layer 12 before electrodepositing the insulating layer 14 on the main surface 16b and the second side surface 16c.
  • the oxide layer on the surface of the first conductor layer 12 may be removed in advance by applying a voltage to the first conductor layer 12.
  • the insulating layer 14 b may be formed on the main body portion 17 and the protruding portion 18 of the second conductor layer 13 by the same process as the insulating layer 14.
  • the insulating layer 14 b may be formed simultaneously with the insulating layer 14.
  • the semiconductor elements 20, 20 a, the main body portion 15, and the protruding portion 16 are sealed with the sealing member 37 (S ⁇ b> 3). Further prepare.
  • the insulating layer 14 has a higher withstand voltage than the sealing member 37.
  • the insulated circuit board 10 on which the semiconductor elements 20 and 20 a are mounted is attached in the case 30.
  • the second conductor layer 13 of the insulated circuit board 10 may be bonded to the base portion 31 via the adhesive layer 28. Then, after injecting the sealing resin into the case 30, the sealing resin is cured.
  • the sealing member 37 may be formed.
  • the semiconductor device 1 may not include the case 30.
  • the semiconductor elements 20, 20a, the insulating circuit board 10, the conductive wires 22a, 22b, 22c, 22d, and some of the lead terminals 33, 33a may be sealed with the sealing member 37 by the transfer molding method. Good.
  • the semiconductor device 1 includes an insulating circuit substrate 10, semiconductor elements 20 and 20 a, and an insulating layer 14.
  • the insulated circuit board 10 includes an insulated substrate 11 and a first conductor layer 12.
  • the insulating substrate 11 includes a first main surface 11a and a second main surface 11b opposite to the first main surface 11a.
  • the first conductor layer 12 is provided on the first main surface 11 a of the insulating substrate 11.
  • the first conductor layer 12 includes a main body portion 15 and a protruding portion 16.
  • the main body 15 includes a third main surface 15a that contacts the first main surface 11a, a fourth main surface 15b opposite to the third main surface 15a, a third main surface 15a, and a fourth main surface 15b. And a first side surface 15c to be connected.
  • the protruding portion 16 protrudes from the first side surface 15c.
  • the protrusion 16 includes a fifth main surface 16a that contacts the first main surface 11a, a sixth main surface 16b opposite to the fifth main surface 16a, a fifth main surface 16a, and a sixth main surface 16b.
  • the second side surface 16c is connected and is opposite to the first side surface 15c.
  • the first thickness t 1 of the protrusion 16 defined by the first distance between the fifth main surface 16a and the sixth main surface 16b is the second thickness between the third main surface 15a and the fourth main surface 15b. It is smaller than the second thickness t 2 of the main body 15 defined by the distance.
  • the semiconductor elements 20 and 20 a are bonded to the first conductor layer 12.
  • the insulating layer 14 is formed on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c.
  • the fifth thickness t 5 of the insulating layer 14 in the third convex corner portion 16e of the protruding portion 16 formed thereby is formed on the fourth main surface 15b other than the first convex corner portion 15d. It is larger than the sixth thickness t 6 of the insulating layer 14.
  • the insulating layer 14 is locally thickly formed on the first convex corner 15d of the main body 15 and the second convex corner 16d and the third convex corner 16e of the protrusion 16.
  • the breakdown voltage of the semiconductor device 1 increases. During use of the semiconductor device 1, the occurrence of dielectric breakdown in the insulating layer 14 can be suppressed.
  • the third thickness t 3 , the fourth thickness t 4, and the fifth thickness t 5 are respectively on the first side surface 15c other than the first convex corner portion 15d. It is larger than the seventh thickness t 7 of the formed insulating layer 14 and the eighth thickness t 8 of the insulating layer 14 formed on the sixth main surface 16b other than the third convex corner portion 16e. May be.
  • the insulating layer 14 is locally thickly formed on the first convex corner 15d of the main body 15 and the second convex corner 16d and the third convex corner 16e of the protrusion 16. The breakdown voltage of the semiconductor device 1 increases. During use of the semiconductor device 1, the occurrence of dielectric breakdown in the insulating layer 14 can be suppressed.
  • ninth thickness t 9 of the second convex corners 16d and the third convex corners 16e second side 16c insulating layer formed on 14 other than the first 7 may be greater than the thickness t 7 and 8 the thickness t 8.
  • the insulating layer 14 is locally thickly formed on the first convex corner 15 d of the main body 15 and the entire second side surface 16 c of the protrusion 16. The breakdown voltage of the semiconductor device 1 increases. During use of the semiconductor device 1, the occurrence of dielectric breakdown in the insulating layer 14 can be suppressed.
  • the protruding length L of the protruding portion 16 from the first side surface 15c may be 100 ⁇ m or more, and the first thickness t 1 may be 20 ⁇ m or less.
  • the insulating layer 14 can be formed on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c in a single step.
  • the semiconductor device 1 has a structure that can be efficiently manufactured.
  • the protruding length L of the protruding portion 16 from the first side surface 15c may be 500 ⁇ m or more, and the first thickness t 1 may be 40 ⁇ m or less.
  • the insulating layer 14 can be formed on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c in a single step.
  • the semiconductor device 1 has a structure that can be efficiently manufactured.
  • the manufacturing method of the semiconductor device 1 includes bonding the semiconductor elements 20 and 20a to the first conductor layer 12 of the insulating circuit substrate 10 (S1).
  • the insulated circuit board 10 includes an insulated substrate 11 and a first conductor layer 12.
  • the insulating substrate 11 includes a first main surface 11a and a second main surface 11b opposite to the first main surface 11a.
  • the first conductor layer 12 is provided on the first main surface 11 a of the insulating substrate 11.
  • the first conductor layer 12 includes a main body portion 15 and a protruding portion 16.
  • the main body 15 includes a third main surface 15a that contacts the first main surface 11a, a fourth main surface 15b opposite to the third main surface 15a, a third main surface 15a, and a fourth main surface 15b.
  • the protruding portion 16 protrudes from the first side surface 15c.
  • the protrusion 16 includes a fifth main surface 16a that contacts the first main surface 11a, a sixth main surface 16b opposite to the fifth main surface 16a, a fifth main surface 16a, and a sixth main surface 16b.
  • the second side surface 16c is connected and is opposite to the first side surface 15c.
  • the first thickness t 1 of the protrusion 16 defined by the first distance between the fifth main surface 16a and the sixth main surface 16b is the second thickness between the third main surface 15a and the fourth main surface 15b. It is smaller than the second thickness t 2 of the main body 15 defined by the distance.
  • the manufacturing method of the semiconductor device 1 of the present embodiment further includes forming the insulating layer 14 on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c (S2). Prepare.
  • the fifth thickness t 5 of the insulating layer 14 in the third convex corner 16e of the protrusion 16 formed by intersecting each other is on the fourth main surface 15b other than the first convex corner 15d. It is larger than the sixth thickness t 6 of the formed insulating layer 14.
  • the insulating layer 14 is locally thickly formed on the first convex corner 15d of the main body 15 and the second convex corner 16d and the third convex corner 16e of the protrusion 16. According to the method for manufacturing the semiconductor device 1 of the present embodiment, the semiconductor device 1 having an increased breakdown voltage can be manufactured. During use of the semiconductor device 1, the occurrence of dielectric breakdown in the insulating layer 14 can be suppressed.
  • the third thickness t 3 , the fourth thickness t 4, and the fifth thickness t 5 are respectively the first side surfaces other than the first convex corner portion 15d.
  • the insulating layer 14 is locally thickly formed on the first convex corner 15d of the main body 15 and the second convex corner 16d and the third convex corner 16e of the protrusion 16. According to the method for manufacturing the semiconductor device 1 of the present embodiment, the semiconductor device 1 having an increased breakdown voltage can be manufactured. During use of the semiconductor device 1, the occurrence of dielectric breakdown in the insulating layer 14 can be suppressed.
  • the ninth thickness t 9 of the insulating layer 14 formed on the second side surface 16c other than the second convex corner portion 16d and the third convex corner portion 16e. May be larger than the seventh thickness t 7 and the eighth thickness t 8 .
  • the insulating layer 14 is locally thickly formed on the first convex corner 15 d of the main body 15 and the entire second side surface 16 c of the protrusion 16. According to the method for manufacturing the semiconductor device 1 of the present embodiment, the semiconductor device 1 having an increased breakdown voltage can be manufactured. During use of the semiconductor device 1, the occurrence of dielectric breakdown in the insulating layer 14 can be suppressed.
  • the insulating layer 14 may be formed simultaneously on the fourth main surface 15b, the first side surface 15c, the sixth main surface 16b, and the second side surface 16c. According to the manufacturing method of the semiconductor device 1 of the present embodiment, the semiconductor device 1 having an increased breakdown voltage can be efficiently manufactured.
  • forming the insulating layer 14 may include forming the insulating layer 14 by an electrodeposition method. According to the method for manufacturing the semiconductor device 1 of the present embodiment, the semiconductor device 1 having an increased breakdown voltage can be manufactured.
  • the protruding length L of the protruding portion 16 from the first side surface 15c may be 100 ⁇ m or more, and the first thickness t 1 may be 20 ⁇ m or less. According to the manufacturing method of the semiconductor device 1 of the present embodiment, the semiconductor device 1 having an increased breakdown voltage can be efficiently manufactured.
  • the protrusion length L of the protrusion 16 from the first side surface 15c may be 500 ⁇ m or more, and the first thickness t 1 may be 40 ⁇ m or less. According to the manufacturing method of the semiconductor device 1 of the present embodiment, the semiconductor device 1 having an increased breakdown voltage can be efficiently manufactured.
  • Embodiment 2 the semiconductor device 1 according to the first embodiment is applied to a power conversion device.
  • power conversion device 200 of the present embodiment is a three-phase inverter.
  • the power conversion system shown in FIG. 9 includes a power supply 100, a power conversion device 200, and a load 300.
  • the power source 100 is a DC power source and supplies DC power to the power conversion device 200.
  • the power supply 100 is not specifically limited, For example, it may be comprised with a DC system, a solar cell, or a storage battery, and may be comprised with the rectifier circuit or AC / DC converter connected to the AC system.
  • the power supply 100 may be configured by a DC / DC converter that converts DC power output from the DC system into another DC power.
  • the power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts the DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300.
  • the power conversion apparatus 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. 203.
  • the load 300 is a three-phase electric motor that is driven by AC power supplied from the power conversion device 200.
  • the load 300 is not particularly limited, but is an electric motor mounted on various electric devices, and is used as an electric motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner, for example.
  • the main conversion circuit 201 includes a switching element (not shown) and a free wheeling diode (not shown).
  • the main conversion circuit 201 converts the DC power supplied from the power supply 100 into AC power and supplies it to the load 300 by switching the voltage supplied from the power supply 100 by the switching element.
  • the main conversion circuit 201 is a two-level three-phase full bridge circuit, and includes six switching elements and respective switching elements. It can be composed of six freewheeling diodes in antiparallel.
  • each switching element and each free-wheeling diode of the main conversion circuit 201 the semiconductor elements 20 and 20a included in the semiconductor device 1 of the first embodiment described above can be applied.
  • the semiconductor device 202 constituting the main conversion circuit 201 the semiconductor device 1 of the first embodiment described above can be applied.
  • Six switching elements are connected in series for every two switching elements to constitute upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase and W phase) of the full bridge circuit.
  • the output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.
  • the main conversion circuit 201 includes a drive circuit (not shown) that drives each switching element.
  • the driver circuit may be incorporated in the semiconductor device 202 or provided outside the semiconductor device 202.
  • the drive circuit generates a drive signal for driving the switching element included in the main conversion circuit 201 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 201.
  • a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element.
  • the semiconductor device 1 according to the first embodiment is applied as the semiconductor device 202 included in the main conversion circuit 201. Therefore, power conversion device 200 according to the present embodiment has low cost and high reliability.
  • the present invention is not limited to this and can be applied to various power conversion devices.
  • a two-level power conversion device is used.
  • a three-level power conversion device or a multi-level power conversion device may be used.
  • the present invention may be applied to a single-phase inverter.
  • the present invention may be applied to a DC / DC converter or an AC / DC converter.
  • the power conversion device to which the present invention is applied is not limited to the case where the load is an electric motor.
  • the power supply device of an electric discharge machine or a laser processing machine, or an induction heating cooker or a non-contact power supply system It can be incorporated into a power supply.
  • the power conversion device to which the present invention is applied can be used as a power conditioner such as a solar power generation system or a power storage system.
  • Embodiment 1 and Embodiment 2 disclosed this time should be considered as illustrative in all points and not restrictive.
  • the scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
  • 1,202 Semiconductor device 10 Insulated circuit board, 11 Insulated board, 11a First main surface, 11b Second main surface, 12 First conductor layer, 13 Second conductor layer, 14, 14b Insulating layer, 15, 17 Body part 15a, 3rd main surface, 15b, 4th main surface, 15c, 1st side surface, 15d, 1st convex corner, 15g, convex corner, 15i, 1st ridge, 16, 18 projecting portion, 16a, 5th main surface, 16b 6th principal surface, 16c 2nd side surface, 16d 2nd convex corner, 16e 3rd convex corner, 16i 2nd ridgeline, 16j 3rd ridgeline, 20, 20a semiconductor element, 21, 21a conductive joining member, 22a , 22b, 22c, 22d Conductive wire, 28 Adhesive layer, 30 Case, 31 Base part, 32 Enclosure, 33, 33a Lead terminal, 35 Cover part, 37 Sealing member, 100 Power supply 200 power converter, 201 main conversion circuit, 203 a control

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Inverter Devices (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur (1) comprenant une carte de circuit isolée (10) et une couche isolante (14). La carte de circuit isolée (10) comprend une première couche conductrice (12). La première couche conductrice (12) comprend : une partie de corps principal (15) et une partie saillante(16). La couche isolante (14) est formée sur une quatrième surface principale (15b) et sur une première surface latérale (15c) de la partie de corps principal (15) et sur une sixième surface principale (16b) et sur une seconde surface latérale (16c) de la partie saillante (16). La troisième épaisseur (t3) de la couche isolante (14) au niveau d'une première partie de coin saillante (15d), la quatrième épaisseur (t4) de la couche isolante (14) au niveau d'une seconde partie de coin saillante (16d) et la cinquième épaisseur (t5) de la couche isolante (14) au niveau d'une troisième partie de coin saillante (16e) sont plus grandes que la sixième épaisseur (t6) de la couche isolante (14) sur la quatrième surface principale (15b). Par conséquent, la tension de claquage diélectrique de ce dispositif à semi-conducteur (1) peut être augmentée.
PCT/JP2018/042867 2018-03-06 2018-11-20 Dispositif à semi-conducteur, convertisseur de puissance électrique et procédé de production de dispositif à semi-conducteur Ceased WO2019171666A1 (fr)

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JP2019520761A JP6639740B1 (ja) 2018-03-06 2018-11-20 半導体装置、電力変換装置及び半導体装置の製造方法

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340374A (ja) * 1998-05-28 1999-12-10 Hitachi Ltd 半導体装置
JP2010103311A (ja) * 2008-10-23 2010-05-06 Toyota Central R&D Labs Inc 積層基板
JP2015115383A (ja) * 2013-12-10 2015-06-22 三菱電機株式会社 半導体装置およびその製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3957341B2 (ja) * 1996-04-18 2007-08-15 日本インター株式会社 複合半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340374A (ja) * 1998-05-28 1999-12-10 Hitachi Ltd 半導体装置
JP2010103311A (ja) * 2008-10-23 2010-05-06 Toyota Central R&D Labs Inc 積層基板
JP2015115383A (ja) * 2013-12-10 2015-06-22 三菱電機株式会社 半導体装置およびその製造方法

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