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WO2019148579A1 - 薄膜晶体管阵列基板及其制造方法 - Google Patents

薄膜晶体管阵列基板及其制造方法 Download PDF

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Publication number
WO2019148579A1
WO2019148579A1 PCT/CN2018/078339 CN2018078339W WO2019148579A1 WO 2019148579 A1 WO2019148579 A1 WO 2019148579A1 CN 2018078339 W CN2018078339 W CN 2018078339W WO 2019148579 A1 WO2019148579 A1 WO 2019148579A1
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Prior art keywords
layer
insulating layer
storage electrode
gate insulating
depositing
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French (fr)
Inventor
周星宇
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/023,702 priority Critical patent/US10553614B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor array substrate and a method of fabricating the same.
  • the thin film transistor array substrate includes: a substrate substrate 110, a buffer layer 120, a gate electrode 131, a first storage electrode 132, a gate insulating layer 140, and metal oxide.
  • the gate 131 and the first storage electrode 132 are required to form a photomask.
  • a photomask is required to form the gate insulating layer 140.
  • a photomask is needed to form the metal oxide active layer 150.
  • a photomask is required, and a source 171, a drain 172, and a second storage electrode 173 are required to form a photomask.
  • a passivation layer 180 is required to form a photomask, and the pixel electrode 190 is required to form a photomask, thereby forming an entire thin film transistor array.
  • the substrate requires up to seven masks, resulting in a larger number of masks, higher costs, and complicated processes.
  • a technical problem to be solved by embodiments of the present invention is to provide a thin film transistor array substrate and a method of fabricating the same.
  • the number of masks required to fabricate the thin film transistor array substrate can be reduced.
  • the first aspect of the present invention provides a method for manufacturing a thin film transistor array substrate, including:
  • a third metal layer is deposited and patterned to form a pixel electrode.
  • the step of depositing the gate insulating layer is specifically: depositing a gate insulating layer under high temperature conditions.
  • the first storage electrode, the gate insulating layer, and the second storage electrode collectively form the storage capacitor.
  • the etch barrier layer forms a storage through hole corresponding to the first storage electrode, and the storage through hole further extends downward to a part of the gate insulating layer.
  • the high temperature ranges from more than 300 °C.
  • the thickness of the gate insulating layer is
  • the step of depositing the second insulating layer is specifically: depositing the second insulating layer by a PECVD process under low temperature conditions.
  • the thickness of the second insulating layer is
  • a second embodiment of the present invention provides a thin film transistor array substrate, including:
  • a gate insulating layer covering the gate and the first storage electrode
  • a metal oxide active layer formed on the gate insulating layer, the metal oxide active layer being disposed corresponding to the gate;
  • An etch barrier layer is formed on the metal oxide active layer and the gate insulating layer, and the etch barrier layer is provided with a storage through hole corresponding to the first storage electrode;
  • a source and a drain respectively electrically connected to the metal oxide semiconductor layer through the etch barrier layer;
  • a second storage electrode which is located in the through hole, and the first storage capacitor, the gate insulating layer and the second storage electrode form a storage capacitor
  • a passivation layer covering the etch stop layer, the source, the drain, and the second storage electrode
  • a pixel electrode formed on the passivation layer, the pixel electrode being electrically connected to the drain.
  • the denseness of the gate insulating layer is higher than the etch stop layer.
  • the gate insulating layer directly deposits the gate insulating layer, the gate insulating layer covers the gate electrode and the first storage electrode, and the gate insulating layer is not patterned by the photomask, thereby manufacturing the thin film transistor array relative to the prior art.
  • the substrate is reduced from 7 masks to 6 masks, saving a mask, saving costs and reducing processes.
  • the storage capacitor since the storage capacitor includes at least a portion of the gate insulating layer, since the gate insulating layer is relatively dense, the storage capacitor is not easily broken down.
  • FIG. 1 is a schematic view of a thin film transistor array substrate of the prior art
  • FIG. 2 is a flow chart showing a method of a thin film transistor array substrate according to an embodiment of the present invention
  • 3a-3f are schematic views showing deposition of respective film layers of a thin film transistor array substrate on a substrate according to an embodiment of the invention
  • FIGS. 4a-4f are schematic views of respective film layers of a thin film transistor array substrate after being patterned by an embodiment of the present invention.
  • Embodiments of the present invention provide a method for fabricating a thin film transistor array substrate. Referring to FIG. 2 to FIG. 4f, the method includes:
  • the base substrate 210 may be a glass substrate, a transparent plastic substrate, or the like, and the base substrate 210 may be flexible or non-flexible.
  • S120 depositing a first metal layer 230 on the substrate substrate 210, and patterning to form a gate electrode 331, a first storage electrode 332;
  • a first metal layer 230 is deposited on the substrate substrate 210.
  • the material of the first metal layer 230 is, for example, a single metal such as Mo, Al, Cu, Ti, or an alloy.
  • the thickness of the first metal layer 230 is (Amy) For example Wait.
  • the first metal layer 230 is patterned by a photomask to form a gate electrode 331 and a first storage capacitor 332.
  • the gate electrode 331 and the first storage electrode 332 are separated from each other. Settings.
  • scan lines are also formed on the base substrate 210, and the scan lines are electrically connected to the corresponding gates 331.
  • the method further includes:
  • a buffer layer 220 is deposited on the upper surface of the entire column of substrates, and the material of the buffer layer 220 is SiO or SiN or a mixture of the two.
  • the thickness of the buffer layer 220 is For example Wait.
  • the buffer layer may not be spaced between the substrate and the gate and the first storage electrode, that is, the gate and the first storage electrode are directly formed on the lining. On the base substrate.
  • a gate insulating layer 240 is deposited on the gate electrode 331, the first storage electrode 332, the scan line, and the buffer layer 220.
  • the gate insulating layer 240 is a complete entire layer.
  • the gate insulating layer 240 is formed by deposition under high temperature conditions. Specifically, the high temperature range of the deposited gate insulating layer 240 is greater than 300 ° C, for example, 310 ° C, 350 ° C, 400. °C, 450 ° C, 500 ° C, 550 ° C, 600 ° C, and the like. Since the temperature is higher when the gate insulating layer 240 is deposited, the gate insulating layer 240 formed is relatively dense and is not easily broken down.
  • the gate insulating layer 240 is thicker, and the thickness of the gate insulating layer 240 is For example Wait. In the present embodiment, since the gate insulating layer 240 is an entire layer, the mask is not required to be patterned. In addition, the material of the gate insulating layer 240 is, for example, SiOx, SiNx, or the like.
  • S140 depositing a metal oxide semiconductor layer 250 and patterning to form a metal oxide active layer 350;
  • a metal oxide semiconductor layer 250 is deposited on the gate insulating layer 240.
  • the material of the metal oxide semiconductor layer 250 is, for example, IGZO (indium gallium zinc oxide). ), IZTO (indium zinc tin oxide), IGZTO (indium gallium zinc tin oxide), etc., the thickness of the metal oxide semiconductor layer 250 is For example Wait. After the metal oxide semiconductor layer 250 is deposited, it is exposed, developed, and etched by a photomask to form a metal oxide active layer 350. Referring to FIG. 4b, the metal oxide active layer 350 is located at the gate. Above the 331.
  • a second insulating layer 260 is deposited on the metal oxide active layer 350 and the gate insulating layer 240.
  • the metal oxide active layer 350 is disposed under the second insulating layer 260.
  • the metal oxide active layer 350 itself cannot withstand relatively high temperatures, so that the second insulating layer 260 is deposited under low temperature conditions, specifically by PECVD (Plasma Enhanced Chemical Vapor Deposition) under low temperature conditions. Chemical vapor deposition) process deposition. Since the temperature does not damage the underlying metal oxide active layer 350 under low temperature conditions.
  • the low temperature range is lower than 300 ° C, for example, 250 ° C, 200 ° C, 150 ° C, 100 ° C, etc., so that the second insulating layer 260 is relatively loose relative to the gate insulating layer 240.
  • the material of the second insulating layer 260 is, for example, a structure of SiOx, SiNx or a plurality of layers.
  • the second insulating layer 260 is formed by deposition by a PECVD process, plasma of the insulating material may be struck on the metal oxide active layer 350 at the time of deposition, and plasma may be deposited if the thickness of the second insulating layer 260 is relatively thick.
  • the body striking metal oxide active layer 350 may be too long to easily cause damage to the metal oxide active layer 350.
  • the thickness of the second insulating layer 260 is For example Wait. In this embodiment, the thickness of the second insulating layer 260 is not too thick, and it is not easy to damage the metal oxide active layer 350 during the process, and the second insulating layer 260 is not too thin, otherwise it is electrically insulated. Poor performance.
  • the second insulating layer 260 is patterned by a photomask, specifically, the second insulating layer 260 is exposed, developed, and etched through the photomask.
  • An etch stop layer 360 is formed.
  • the etching process is dry etching.
  • the etch stop layer 360 after the etch stop layer 360 is formed, at least three holes are formed in the etch stop layer 360, specifically a source through hole 361, a drain through hole 362, and a storage through hole 363, wherein the source The pole through hole 361 and the drain through hole 362 are located on the metal oxide active layer 350 and are located on both sides thereof, and the storage through hole 363 is disposed corresponding to the first storage electrode 332.
  • the dry etching can control different regions to form different etching depths, and is stopped when etching to the metal oxide active layer 350.
  • the gate insulating layer 240, that is, the memory via 363 also extends downward into the portion of the gate insulating layer 240, that is, overetched over the first storage electrode 332.
  • the etching of the second insulating layer on the first storage electrode may be designed according to the needs of the storage capacitor, but at least a portion of the gate insulating layer.
  • the thickness of the gate insulating layer 240 above the first storage electrode 332 is less than or equal to the thickness of the second insulating layer 260.
  • S160 depositing a second metal layer 270, and patterning a source 371, a drain 372, and a second storage electrode 373, wherein the first storage electrode 332 and the second storage electrode 373 are two electrodes of a storage capacitor;
  • a second metal layer 270 is deposited on the etch barrier layer 360.
  • the material of the second metal layer 270 is, for example, a single metal such as Mo, Al, Cu, Ti, or a metal. Alloy, the thickness of the second metal layer 270 is For example Wait. At this time, the second metal layer 270 enters the source through hole 361, the drain through hole 362, and the storage through hole 363.
  • the second metal layer 270 is patterned by a photomask, see FIG. 4d, thereby forming a source electrode 371, a drain electrode 372, a second storage electrode 373, the source electrode 371 and a metal oxide active layer.
  • One side of the 350 is connected, the drain 372 is connected to the other side of the metal oxide active layer 350, the second storage electrode 373 is disposed corresponding to the first storage electrode 332, and the second storage electrode 373 is
  • the gate insulating layer 240 is sandwiched between the first storage electrodes 332 such that the first storage electrode 332, the gate insulating layer 240, and the second storage electrode 373 form a storage capacitor.
  • the gate insulating layer 240 between the first storage electrode 332 and the second storage electrode 373 is formed by high temperature, which is relatively dense, the storage capacitor is not easily broken down.
  • a data line is further formed on the etch barrier layer 360, and the data line is electrically connected to the source 371.
  • the gate 331 is at a high level, the signal transmitted on the data line is transmitted to the drain 372 via the source 371 and the metal oxide active layer 350.
  • S170 depositing a third insulating layer 280 and patterning to form a passivation layer 380;
  • the third insulating layer 280 is deposited on the data line, the source 371, the drain 372, the second storage electrode 373, and the etch barrier layer 360.
  • the third insulating layer 280 is a SiOx layer, a SiNx layer or a multi-film layer structure.
  • the passivation layer 380 is patterned by the photomask to the third insulating layer 280, see FIG. 4e. Specifically, a pixel via 381 is formed on the passivation layer 380. The pixel via 381 is located above the drain 372. The pixel via 381 is used to connect the drain 372 and the pixel electrode 390 formed later. . In addition, in the embodiment, other via holes are formed on the passivation layer for electrical signal transmission.
  • a third metal layer 290 is deposited on the passivation layer 380, and the third metal layer 290 enters the pixel vias 381 and other vias.
  • the material of the third metal layer 290 is ITO or the like.
  • the third metal layer 290 is patterned by a photomask. Referring to FIG. 4f, the formation of the pixel electrode 390 and other lines is realized. In the present embodiment, the pixel electrode 390 is electrically connected to the drain 372.
  • the gate insulating layer 240 since the gate insulating layer 240 is directly deposited, the gate insulating layer 240 covers the gate electrode 331 and the first storage electrode 332, and the gate insulating layer 240 does not need to be patterned by the photomask. Therefore, compared with the prior art, the thin film transistor array substrate is reduced from 7 reticle to 6 reticle, which saves a reticle, thereby saving cost and reducing the process. Moreover, in the present embodiment, since the storage capacitor includes at least a portion of the gate insulating layer 240, since the gate insulating layer 240 is relatively dense, the storage capacitor is not easily broken down.
  • the embodiment of the present invention further provides a thin film transistor array substrate.
  • the array substrate includes a substrate substrate 210, a gate electrode 331, a first storage electrode 332, a gate insulating layer 240, and a metal oxide active source.
  • the base substrate 210 may be a glass substrate, a transparent plastic substrate, or the like, and the base substrate 210 may be flexible or non-flexible.
  • the gate electrode 331 and the first storage electrode 332 are indirectly formed on the base substrate 210, and the gate electrode 331 and the first storage electrode 332 are patterned by the same metal layer to form the gate.
  • the material of the pole 331 and the first storage electrode 332 is, for example, a single metal such as Mo, Al, Cu, or Ti, or may be an alloy.
  • the buffer layer 220 is disposed between the gate electrode 331, the first storage electrode 332, and the base substrate 210. Of course, in other embodiments of the present invention, the buffer layer may not be disposed.
  • scan lines are also formed on the base substrate 210, and the scan lines are electrically connected to the corresponding gates 331.
  • a gate insulating layer 240 is formed on the gate electrode 331, the first storage electrode 332, the scan line, and the buffer layer 220.
  • the gate insulating layer 240 is a complete entire layer.
  • the gate insulating layer 240 is deposited under high temperature conditions. Specifically, the high temperature range of the deposited gate insulating layer 240 is greater than 300 ° C, for example, 310 ° C, 350 ° C, 400 ° C, 450 ° C, 500 ° C, 550 ° C, 600 ° C, and the like. Since the temperature is higher when the gate insulating layer 240 is deposited, the gate insulating layer 240 is denser and is less likely to be broken down.
  • the gate insulating layer 240 is thicker, and the thickness of the gate insulating layer 240 is For example Wait. In the present embodiment, since the gate insulating layer 240 is an entire layer, the mask is not required to be patterned. In addition, the material of the gate insulating layer 240 is, for example, SiOx, SiNx, or the like.
  • the metal oxide active layer 350 is located above the gate 331, and the material forming the metal oxide active layer 350 is, for example, IGZO (indium gallium zinc oxide).
  • IGZO indium gallium zinc oxide
  • a metal oxide semiconductor material such as IZTO (indium zinc tin oxide) or IGZTO (indium gallium zinc tin oxide)
  • the thickness of the metal oxide active layer 350 is For example Wait. Since the active layer is made of a metal oxide semiconductor material, the thin film transistor including the metal oxide active layer 350 has a faster electron mobility and a smaller size of the thin film transistor, which can increase the aperture ratio of the array substrate, and is easier to achieve high definition. .
  • the etch stop layer 360 is formed on the metal oxide active layer 350 and the gate insulating layer 240.
  • the etch stop layer 360 is formed by low temperature deposition and patterning, and is formed at a low temperature.
  • the etch stop layer 360 is relatively loose relative to the gate insulating layer 240.
  • the material of the etch barrier layer 360 is, for example, a structure of SiOx, SiNx or a plurality of layers.
  • the thickness of the etch stop layer 360 is
  • At least three holes are formed in the etch stop layer 360, specifically a source through hole 361, a drain through hole 362, and a storage through hole 363 (please refer to FIG. 4c), wherein the source The through hole 361 and the drain through hole 362 are located on the metal oxide active layer 350 and are located on both sides thereof, and the storage through hole 363 is disposed corresponding to the first storage electrode 332.
  • the source 371, the drain 372, and the second storage electrode 373 are formed on the etch barrier layer 360.
  • the source 371, the drain 372, and the second storage electrode 373 are formed by the same metal pattern.
  • the material forming the source 371, the drain 372, and the second storage electrode 373 is, for example, a single metal such as Mo, Al, Cu, or Ti, or a metal alloy, and the source 371, the drain 372, and the second storage electrode 373 Thickness is
  • the source 371 is connected to one side of the metal oxide active layer 350
  • the drain 372 is connected to the other side of the metal oxide active layer 350
  • the second storage electrode 373 corresponds to the first storage.
  • the electrode 332 is disposed, and the gate insulating layer 240 is sandwiched between the second storage electrode 373 and the first storage electrode 332, so that the first storage electrode 332, the gate insulating layer 240, and the first The two storage electrodes 373 form a storage capacitor.
  • a passivation layer 380 is formed on the source 371, the drain 372, the second storage electrode 373, and the etch barrier layer 360, and the passivation layer 380 is an SiOx layer, a SiNx layer, or a multi-film layer structure.
  • a pixel via 381 is formed on the passivation layer 380 (see FIG. 4e), the pixel via 381 is located above the drain 372, and the pixel via 381 is used to connect the drain. 372 and a pixel electrode 390 formed later.
  • the passivation layer 380 is further provided with other via holes for electrical signal transmission.
  • the pixel electrode 390 is formed on the passivation layer 380, and the pixel electrode 390 enters the pixel via 381.
  • the material of the pixel electrode 390 is ITO or the like.
  • the pixel electrode 390 is electrically connected to the drain 372.

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Abstract

一种薄膜晶体管阵列基板的制造方法，包括：提供衬底基板（210）；在衬底基板（210）上沉积第一金属层（230），并图案化形成栅极（331）、第一存储电极（332）；沉积栅极绝缘层（240），所述栅极绝缘层（240）覆盖栅极（331）、第一存储电极（332）；沉积金属氧化物半导体层（250），并图案化形成金属氧化物有源层（350）；沉积第二绝缘层（260），并图案化形成蚀刻阻挡层（360）；沉积第二金属层（270），并图案化形成源极（371）、漏极（372）、第二存储电极（373），所述第一存储电极（332）、第二存储电极（373）为存储电容的两个电极；沉积第三绝缘层（280），并图案化形成钝化层（380）；沉积第三金属层（290），并图案化形成像素电极（390）。以及一种薄膜晶体管阵列基板。所述制造方法能够减少制造薄膜晶体管阵列基板所需要的光罩的数目。

Description

薄膜晶体管阵列基板及其制造方法
本发明要求2018年2月5日递交的发明名称为“薄膜晶体管阵列基板及其制造方法”的申请号201810111246.4的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示技术领域，特别是涉及一种薄膜晶体管阵列基板及其制造方法。
背景技术
现有的一种薄膜晶体管阵列基板，请参见图1，所述薄膜晶体管阵列基板包括：衬底基板110、缓冲层120、栅极131、第一存储电极132、栅极绝缘层140、金属氧化物有源层150、蚀刻阻挡层160、源极171、漏极172、第二存储电极173、钝化层180和像素电极190，其中，所述栅极绝缘层140在对应第一存储电极132处设有存储贯通孔，所述第一存储电极132、蚀刻阻挡层160和第二存储电极173形成存储电容。
在上述的结构中，形成栅极131、第一存储电极132需要一道光罩，形成栅极绝缘层140需要一道光罩，形成金属氧化物有源层150需要一道光罩，形成蚀刻阻挡层160需要一道光罩，形成源极171、漏极172、第二存储电极173需要一道光罩，形成钝化层180需要一道光罩，形成像素电极190需要一道光罩，从而，形成整个薄膜晶体管阵列基板需要多达7道光罩，导致需要光罩数目较多，成本较高，制程也复杂。
发明内容
本发明实施例所要解决的技术问题在于，提供一种薄膜晶体管阵列基板及其制造方法。可减少制造薄膜晶体管阵列基板所需要的光罩的数目。
为了解决上述技术问题，本发明第一方面实施例提供了一种薄膜晶体管阵列基板的制造方法，包括：
提供衬底基板；
在衬底基板上沉积第一金属层，并图案化形成栅极、第一存储电极；
沉积栅极绝缘层，所述栅极绝缘层覆盖栅极、第一存储电极；
沉积金属氧化物半导体层，并图案化形成金属氧化物有源层；
沉积第二绝缘层，并图案化形成蚀刻阻挡层；
沉积第二金属层，并图案化形成源极、漏极、第二存储电极，所述第一存储电极、第二存储电极为存储电容的两个电极；
沉积第三绝缘层，并图案化形成钝化层；
沉积第三金属层，并图案化形成像素电极。
其中，所述沉积栅极绝缘层的步骤具体为：在高温条件下沉积栅极绝缘层。
其中，所述第一存储电极、栅极绝缘层、第二存储电极共同形成所述存储电容。
其中，所述蚀刻阻挡层对应第一存储电极处形成存储贯通孔，所述存储贯通孔还向下延伸进入到部分栅极绝缘层。
其中，所述高温的范围为大于300℃。
其中，所述栅极绝缘层的厚度为
Figure PCTCN2018078339-appb-000001
其中，所述沉积第二绝缘层的步骤具体为：在低温条件下通过PECVD工艺沉积第二绝缘层。
其中，所述第二绝缘层的厚度为
Figure PCTCN2018078339-appb-000002
本发明第二方面实施例提供了一种薄膜晶体管阵列基板，包括：
衬底基板；
栅极，其形成在衬底基板上；
第一存储电极，其形成在衬底基板上；
栅极绝缘层，其覆盖所述栅极、第一存储电极；
金属氧化物有源层，其形成在所述栅极绝缘层上，所述金属氧化物有源层对应所述栅极设置；
蚀刻阻挡层，其形成在所述金属氧化物有源层和所述栅极绝缘层上，所述 蚀刻阻挡层对应第一存储电极处设有存储贯通孔；
源极和漏极，其分别穿过蚀刻阻挡层与金属氧化物半导体层电连接；
第二存储电极，其位于贯通孔中，所述第一存储电容、栅极绝缘层和所述第二存储电极形成存储电容；
钝化层，其覆盖所述蚀刻阻挡层、源极、漏极和第二存储电极；
像素电极，其形成在钝化层上，所述像素电极与所述漏极电连接。
其中，所述栅极绝缘层的致密性高于所述蚀刻阻挡层。
实施本发明实施例，具有如下有益效果：
由于直接沉积栅极绝缘层，所述栅极绝缘层覆盖所述栅极、第一存储电极，不需要通过光罩对栅极绝缘层进行图案化，从而，相对现有技术，制造薄膜晶体管阵列基板由7道光罩缩减为6道光罩，节省了一道光罩，从而节省了成本，并且减少了工序。而且，在本实施例中，由于所述存储电容包括至少部分栅极绝缘层，由于栅极绝缘层比较致密，从而存储电容也不容易被击穿。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术一种薄膜晶体管阵列基板的示意图；
图2是本发明一实施例薄膜晶体管阵列基板方法的流程图；
图3a-图3f是本发明一实施例薄膜晶体管阵列基板各个膜层沉积在衬底基板上的示意图；
图4a-图4f是本发明一实施例薄膜晶体管阵列基板的各个膜层经过图案化处理后的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清 楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本申请说明书、权利要求书和附图中出现的术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。此外，术语“第一”、“第二”和“第三”等是用于区别不同的对象，而并非用于描述特定的顺序。
本发明实施例提供一种薄膜晶体管阵列基板的制造方法，请参见图2-图4f，所述方法包括：
S110：提供衬底基板210；
在本实施例中，所述衬底基板210可以为玻璃基板、透明塑料基板等，所述衬底基板210可以为柔性的，也可以是非柔性。
S120：在衬底基板210上沉积第一金属层230，并图案化形成栅极331、第一存储电极332；
在本实施例中，请参见图3a，在衬底基板210上沉积第一金属层230，所述第一金属层230的材料例如为Mo、Al、Cu、Ti等单金属，也可以是合金，例如Mo和Al合金等，所述第一金属层230的厚度为
Figure PCTCN2018078339-appb-000003
(埃米)
Figure PCTCN2018078339-appb-000004
例如为
Figure PCTCN2018078339-appb-000005
等。形成第一金属层230后，请参见图4a，通过光罩对所述第一金属层230图案化形成栅极331、第一存储电容332，所述栅极331、第一存储电极332彼此分离设置。另外，在本实施例中，所述衬底基板210上还会形成扫描线，所述扫描线与对应的栅极331电连接。
另外，为了防止衬底基板210中的杂质渗透到栅极331、第一存储电极332中，在本实施例中，在步骤S120之前，还包括：
S190：在衬底基板210上沉积缓冲层220；
在本实施例中，整个整列基板的上表面上都沉积了缓冲层220，所述缓冲 层220的材料为SiO或者SiN或者两种的混合物。所述缓冲层220的厚度为
Figure PCTCN2018078339-appb-000006
例如为
Figure PCTCN2018078339-appb-000007
等。当然，在沉积缓冲层220之前，一般还需要对衬底基板210进行清洗。另外，在本发明的其他实施例中，所述衬底基板和所述栅极、第一存储电极之间还可以不间隔缓冲层，也即所述栅极、第一存储电极直接形成在衬底基板上。
S130：沉积栅极绝缘层240，所述栅极绝缘层240覆盖栅极331、第一存储电极332；
在本实施例中，在栅极331、第一存储电极332、扫描线、缓冲层220上沉积一层栅极绝缘层240，在此处，栅极绝缘层240为完整的一整层。在本实施例中，所述栅极绝缘层240是在高温条件下沉积形成的，具体说来，沉积栅极绝缘层240的高温的范围为大于300℃，例如为310℃、350℃、400℃、450℃、500℃、550℃、600℃等。由于沉积栅极绝缘层240时温度较高，从而形成的栅极绝缘层240较为致密，不容易被击穿。在本实施例中，所述栅极绝缘层240较厚，所述栅极绝缘层240的厚度范围为
Figure PCTCN2018078339-appb-000008
例如为
Figure PCTCN2018078339-appb-000009
Figure PCTCN2018078339-appb-000010
等。在本实施例中，由于栅极绝缘层240为一整层，从而不需要光罩去对其进行图案化处理。另外，所述栅极绝缘层240的材料例如为SiOx、SiNx等。
S140：沉积金属氧化物半导体层250，并图案化形成金属氧化物有源层350；
在本实施例中，请参见图3b，在栅极绝缘层240上沉积金属氧化物半导体层250，所述金属氧化物半导体层250的材料例如为IGZO(indium gallium zinc oxide，铟镓锌氧化物)、IZTO(铟锌锡氧化物)、IGZTO(铟镓锌锡氧化物)等，所述金属氧化物半导体层250的厚度为
Figure PCTCN2018078339-appb-000011
例如为
Figure PCTCN2018078339-appb-000012
Figure PCTCN2018078339-appb-000013
等。沉积金属氧化物半导体层250后，其后通过光罩对其进行曝光、显影、蚀刻形成金属氧化物有源层350，请参见图4b，所述金属氧化物有源层350位于所述栅极331的上方。
S150:沉积第二绝缘层260，并图案化形成蚀刻阻挡层360；
在本实施例中，请参见图3c，在所述金属氧化物有源层350、栅极绝缘层 240上沉积第二绝缘层260，由于第二绝缘层260下方有金属氧化物有源层350，而金属氧化物有源层350本身不能承受比较高的温度，从而所述第二绝缘层260在低温条件下沉积形成，具体为在低温条件下通过PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学的气相沉积)工艺沉积形成。由于在低温条件下，温度不会损坏下面的金属氧化物有源层350。在本实施例中，所述低温的范围为低于300℃，例如为250℃、200℃、150℃、100℃等，从而所述第二绝缘层260相对栅极绝缘层240比较疏松。在本实施例中，所述第二绝缘层260的材料例如为SiOx、SiNx或者多层的结构。
而且，由于第二绝缘层260是通过PECVD工艺沉积形成，从而在沉积时绝缘材料的等离子体会击打在金属氧化物有源层350上，如果第二绝缘层260厚度比较厚，则沉积时等离子体击打金属氧化物有源层350会过长，从而容易导致金属氧化物有源层350损坏，为了避免这种情况出现，在本实施例中，所述第二绝缘层260的厚度为
Figure PCTCN2018078339-appb-000014
例如为
Figure PCTCN2018078339-appb-000015
Figure PCTCN2018078339-appb-000016
等。在本实施例中，所述第二绝缘层260的厚度不太厚，不容易在制程过程中损坏金属氧化物有源层350，所述第二绝缘层260也不能太薄，不然电性绝缘性能较差。
在本实施例中，沉积形成第二绝缘层260后，请参见图4c，通过光罩对第二绝缘层260进行图案化，具体为通过光罩对第二绝缘层260进行曝光、显影、蚀刻形成蚀刻阻挡层360。在本实施例中，所述蚀刻工艺为干蚀刻。在本实施例中，形成蚀刻阻挡层360后，所述蚀刻阻挡层360上至少形成三种孔，具体为源极贯通孔361、漏极贯通孔362和存储贯通孔363，其中，所述源极贯通孔361、漏极贯通孔362位于金属氧化物有源层350上，并位于其两侧，所述存储贯通孔363对应第一存储电极332设置。在形成上述三种贯通孔的过程中，通过干蚀刻工艺蚀刻第二绝缘层260时，干蚀刻可以控制不同区域形成不同的蚀刻深度，当蚀刻到金属氧化物有源层350此处就会停止蚀刻以形成源极贯通孔361、漏极贯通孔362，同时，第一存储电极332上方继续进行干蚀刻，将第一存储电极332上方的第二绝缘层260的材料蚀刻完，并且蚀刻掉部分栅极绝缘层240，也即所述存储贯通孔363还向下延伸进入到栅极绝缘层240部分，也即在第一存储电极332上方进行了过蚀刻。另外，在本发明的其他实 施例中，第一存储电极上对第二绝缘层的蚀刻可以根据存储电容的需要进行设计，但至少包括部分栅极绝缘层。在本实施例中，所述第一存储电极332上方的栅极绝缘层240的厚度小于或等于第二绝缘层260的厚度。
S160:沉积第二金属层270，并图案化形成源极371、漏极372、第二存储电极373，所述第一存储电极332、第二存储电极373为存储电容的两个电极；
在本实施例中，请参见图3d，在所述蚀刻阻挡层360上沉积第二金属层270，所述第二金属层270的材料例如为Mo、Al、Cu、Ti等单金属，或者金属合金，所述第二金属层270的厚度为
Figure PCTCN2018078339-appb-000017
例如为
Figure PCTCN2018078339-appb-000018
Figure PCTCN2018078339-appb-000019
等。此时，所述第二金属层270会进入源极贯通孔361、漏极贯通孔362和存储贯通孔363中。
此后，通过光罩对所述第二金属层270进行图案化，请参见图4d，从而形成源极371、漏极372、第二存储电极373，所述源极371与金属氧化物有源层350的一侧连接，所述漏极372与金属氧化物有源层350的另一侧连接，所述第二存储电极373对应所述第一存储电极332设置，所述第二存储电极373与所述第一存储电极332之间夹着所述栅极绝缘层240，从而，所述第一存储电极332、栅极绝缘层240和所述第二存储电极373形成存储电容。在本实施例中，由于第一存储电极332和第二存储电极373之间的栅极绝缘层240是通过高温形成，从而比较致密，存储电容不容易被击穿。
另外，在本实施例中，通过对所述第二金属层270进行图案化，所述蚀刻阻挡层360上还形成数据线，所述数据线与所述源极371电连接。当栅极331为高电平时，所述数据线上传输的信号经由源极371、金属氧化物有源层350传到漏极372。
S170:沉积第三绝缘层280，并图案化形成钝化层380；
在本实施例中，请参见图3e，所述第三绝缘层280沉积在数据线、源极371、漏极372、第二存储电极373和蚀刻阻挡层360，所述第三绝缘层280厚度比较厚，达到平坦化的效果，在本实施例中，所述第三绝缘层280的厚度为
Figure PCTCN2018078339-appb-000020
例如为
Figure PCTCN2018078339-appb-000021
等。在本实施例中，所述第三绝缘层280为SiOx层、SiNx层或者多膜层结构。
在形成第三绝缘层280后，通过光罩对第三绝缘层280图案化钝化层380， 请参见图4e。具体说来，所述钝化层380上形成像素过孔381，所述像素过孔381位于所述漏极372上方，所述像素过孔381用于连接漏极372与后面形成的像素电极390。另外，在本实施例中，所述钝化层上还形成其他过孔，用于电性信号传送。
S180:沉积第三金属层290，并图案化形成像素电极390。
在本实施例中，请参见图3f，在所述钝化层380上沉积第三金属层290，并且第三金属层290进入像素过孔381和其他过孔中。所述第三金属层290的材料为ITO等。其后通过光罩对第三金属层290图案化，请参见图4f，实现形成像素电极390和其他线路，在本实施例中，所述像素电极390与所述漏极372电连接。
在本实施例中，由于直接沉积栅极绝缘层240，所述栅极绝缘层240覆盖所述栅极331、第一存储电极332，不需要通过光罩对栅极绝缘层240进行图案化，从而，相对现有技术，制造薄膜晶体管阵列基板由7道光罩缩减为6道光罩，节省了一道光罩，从而节省了成本，并且减少了工序。而且，在本实施例中，由于所述存储电容包括至少部分栅极绝缘层240，由于栅极绝缘层240比较致密，从而存储电容也不容易被击穿。
本发明实施例例还提供一种薄膜晶体管阵列基板，请参见图4f，所述阵列基板包括衬底基板210、栅极331、第一存储电极332、栅极绝缘层240、金属氧化物有源层350、蚀刻阻挡层360、源极371、漏极372、第二存储电极373、钝化层380和像素电极390。
在本实施例中，所述衬底基板210可以为玻璃基板、透明塑料基板等，所述衬底基板210可以为柔性的，也可以是非柔性。
在本实施例中，所述栅极331、第一存储电极332间接形成在衬底基板210上，所述栅极331和第一存储电极332由同一层金属层图案化形成，形成所述栅极331、第一存储电极332的材料例如为Mo、Al、Cu、Ti等单金属，也可以是合金。在本实施例中，所述栅极331、第一存储电极332和所述衬底基板210之间设置了缓冲层220，当然，在本发明的其他实施例中，还可以不设置缓冲层。另外，在本实施例中，所述衬底基板210上还会形成扫描线，所述扫描线与对应的栅极331电连接。
在本实施例中，在栅极331、第一存储电极332、扫描线、缓冲层220上形成一层栅极绝缘层240，在此处，栅极绝缘层240为完整的一整层。在本实施例中，所述栅极绝缘层240是在高温条件下沉积而成的，具体说来，沉积栅极绝缘层240的高温的范围为大于300℃，例如为310℃、350℃、400℃、450℃、500℃、550℃、600℃等。由于沉积栅极绝缘层240时温度较高，从而栅极绝缘层240较为致密，不容易被击穿。在本实施例中，所述栅极绝缘层240较厚，所述栅极绝缘层240的厚度范围为
Figure PCTCN2018078339-appb-000022
例如为
Figure PCTCN2018078339-appb-000023
Figure PCTCN2018078339-appb-000024
等。在本实施例中，由于栅极绝缘层240为一整层，从而不需要光罩去对其进行图案化处理。另外，所述栅极绝缘层240的材料例如为SiOx、SiNx等。
在本实施例中，所述金属氧化物有源层350位于所述栅极331的上方，形成金属氧化物有源层350的材料例如为IGZO(indium gallium zinc oxide，铟镓锌氧化物)、IZTO(铟锌锡氧化物)、IGZTO(铟镓锌锡氧化物)等金属氧化物半导体材料，所述金属氧化物有源层350的厚度为
Figure PCTCN2018078339-appb-000025
例如为
Figure PCTCN2018078339-appb-000026
等。由于有源层采用金属氧化物半导体材料，从而包括金属氧化物有源层350的薄膜晶体管，电子迁移率较快，薄膜晶体管尺寸比较小，可提高阵列基板的开口率，较容易实现高精细化。
在本实施例中，所述蚀刻阻挡层360形成在金属氧化物有源层350、栅极绝缘层240上，所述蚀刻阻挡层360通过低温沉积并图案化形成，由于是低温形成，从而所述蚀刻阻挡层360相对栅极绝缘层240比较疏松。在本实施例中，所述蚀刻阻挡层360的材料例如为SiOx、SiNx或者多层的结构。所述蚀刻阻挡层360的厚度为
Figure PCTCN2018078339-appb-000027
在本实施例中，所述蚀刻阻挡层360上至少形成三种孔，具体为源极贯通孔361、漏极贯通孔362和存储贯通孔363(请参见图4c)，其中，所述源极贯通孔361、漏极贯通孔362位于金属氧化物有源层350上，并位于其两侧，所述存储贯通孔363对应第一存储电极332设置。
在本实施例中，所述源极371、漏极372、第二存储电极373形成在蚀刻阻挡层360上，所述源极371、漏极372、第二存储电极373由同一层金属图 案形成，形成源极371、漏极372、第二存储电极373的材料例如为Mo、Al、Cu、Ti等单金属，或者金属合金，所述源极371、漏极372、第二存储电极373的厚度为
Figure PCTCN2018078339-appb-000028
所述源极371与金属氧化物有源层350的一侧连接，所述漏极372与金属氧化物有源层350的另一侧连接，所述第二存储电极373对应所述第一存储电极332设置，所述第二存储电极373与所述第一存储电极332之间夹着所述栅极绝缘层240，从而，所述第一存储电极332、栅极绝缘层240和所述第二存储电极373形成存储电容。
在本实施例中，在源极371、漏极372、第二存储电极373和蚀刻阻挡层360上形成钝化层380，所述钝化层380为SiOx层、SiNx层或者多膜层结构。在本实施例中，所述钝化层380上形成像素过孔381(请参见图4e)，所述像素过孔381位于所述漏极372上方，所述像素过孔381用于连接漏极372与后面形成的像素电极390。另外，在本实施例中，所述钝化层380上还设有其他过孔，用于电性信号传送。
在本实施例中，在所述钝化层380上形成像素电极390，并且像素电极390进入像素过孔381中。所述像素电极390的材料为ITO等。所述像素电极390与所述漏极372电连接。
需要说明的是，本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。对于装置实施例而言，由于其与方法实施例基本相似，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (10)

  1. 一种薄膜晶体管阵列基板的制造方法，其中，包括：
    提供衬底基板；
    在衬底基板上沉积第一金属层，并图案化形成栅极、第一存储电极；
    沉积栅极绝缘层，所述栅极绝缘层覆盖栅极、第一存储电极；
    沉积金属氧化物半导体层，并图案化形成金属氧化物有源层；
    沉积第二绝缘层，并图案化形成蚀刻阻挡层；
    沉积第二金属层，并图案化形成源极、漏极、第二存储电极，所述第一存储电极、第二存储电极为存储电容的两个电极；
    沉积第三绝缘层，并图案化形成钝化层；
    沉积第三金属层，并图案化形成像素电极。
  2. 如权利要求1所述的薄膜晶体管阵列基板的制造方法，其中，所述沉积栅极绝缘层的步骤具体为：
    在高温条件下沉积栅极绝缘层。
  3. 如权利要求2所述的薄膜晶体管阵列基板的制造方法，其中，所述第一存储电极、栅极绝缘层、第二存储电极共同形成所述存储电容。
  4. 如权利要求3所述的薄膜晶体管阵列基板的制造方法，其中，所述蚀刻阻挡层对应第一存储电极处形成存储贯通孔，所述存储贯通孔还向下延伸进入到部分栅极绝缘层。
  5. 如权利要求2所述的薄膜晶体管阵列基板的制造方法，其中，所述高温的范围为大于300℃。
  6. 如权利要求2所述的薄膜晶体管阵列基板的制造方法，其中，所述栅极绝缘层的厚度为
    Figure PCTCN2018078339-appb-100001
  7. 如权利要求1所述的薄膜晶体管阵列基板的制造方法，其中，所述沉积第二绝缘层的步骤具体为：在低温条件下通过PECVD工艺沉积第二绝缘层。
  8. 如权利要求7所述的薄膜晶体管阵列基板的制造方法，其中，所述第二绝缘层的厚度为
    Figure PCTCN2018078339-appb-100002
  9. 一种薄膜晶体管阵列基板，其中，包括：
    衬底基板；
    栅极，其形成在衬底基板上；
    第一存储电极，其形成在衬底基板上；
    栅极绝缘层，其覆盖所述栅极、第一存储电极；
    金属氧化物有源层，其形成在所述栅极绝缘层上，所述金属氧化物有源层对应所述栅极设置；
    蚀刻阻挡层，其形成在所述金属氧化物有源层和所述栅极绝缘层上，所述蚀刻阻挡层对应第一存储电极处设有存储贯通孔；
    源极和漏极，其分别穿过蚀刻阻挡层与金属氧化物半导体层电连接；
    第二存储电极，其位于贯通孔中，所述第一存储电容、栅极绝缘层和所述第二存储电极形成存储电容；
    钝化层，其覆盖所述蚀刻阻挡层、源极、漏极和第二存储电极；
    像素电极，其形成在钝化层上，所述像素电极与所述漏极电连接。
  10. 如权利要求9所述的薄膜晶体管阵列基板，其中，所述栅极绝缘层的致密性高于所述蚀刻阻挡层。
PCT/CN2018/078339 2018-02-05 2018-03-07 薄膜晶体管阵列基板及其制造方法 Ceased WO2019148579A1 (zh)

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