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WO2019095408A1 - Substrat de réseau, son procédé de fabrication et panneau d'affichage - Google Patents

Substrat de réseau, son procédé de fabrication et panneau d'affichage Download PDF

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Publication number
WO2019095408A1
WO2019095408A1 PCT/CN2017/112188 CN2017112188W WO2019095408A1 WO 2019095408 A1 WO2019095408 A1 WO 2019095408A1 CN 2017112188 W CN2017112188 W CN 2017112188W WO 2019095408 A1 WO2019095408 A1 WO 2019095408A1
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WO
WIPO (PCT)
Prior art keywords
layer
drain
source
region
via hole
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Ceased
Application number
PCT/CN2017/112188
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English (en)
Chinese (zh)
Inventor
张鹏振
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Publication of WO2019095408A1 publication Critical patent/WO2019095408A1/fr
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Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Definitions

  • the invention relates to a display panel technology, in particular to an array substrate, a manufacturing method thereof and a display panel.
  • IGZO In-Ga-Zn-O, indium gallium zinc oxide
  • TFT thin film transistor
  • the present invention provides an array substrate, a manufacturing method thereof, and a display panel, thereby improving an aperture ratio and a storage capacitor size while reducing an area occupied by the storage capacitor.
  • the invention provides an array substrate comprising a glass substrate, a buffer layer, a semiconductor layer, a gate insulating layer, a gate, an interlayer insulating layer, a source, a drain, a flat layer, a common electrode, a passivation layer, and a pixel electrode. ;among them,
  • a buffer layer is formed on the substrate; a semiconductor layer is formed on the buffer layer; the semiconductor layer includes an active region and a source region and a drain region disposed on both sides of the active region, wherein the gate insulating layer and the gate are sequentially Formed on the active region; the interlayer insulating layer is formed on a buffer layer, a source region, and a drain region that are not blocked by the semiconductor layer; and the interlayer insulating layer is formed at a corresponding source region and a drain region a first via hole; the source and the drain are respectively in contact with the source region and the drain region via the first via hole; the flat layer is formed at the source and the drain, and is not blocked by the source and the drain On the interlayer insulating layer; the common electrode is formed on the flat layer, and the passivation layer is formed on the common electrode and the flat layer not blocked by the common electrode, and the passivation layer and the corresponding drain on the flat layer are formed on the same a second via hole, the third via hole; the pixel electrode is
  • the semiconductor layer is made of indium gallium zinc oxide.
  • the passivation layer is made of yttrium oxide.
  • the invention also provides a display panel comprising the oxide array substrate.
  • the invention also provides a method for fabricating an array substrate, comprising the following steps:
  • a source and a drain are respectively formed on the interlayer insulating layer, and the source and the drain are respectively in contact with the source region and the drain region via the first via hole;
  • a pixel electrode is formed on the passivation layer, and the pixel electrode is in contact with the drain via the second via hole and the third via hole.
  • the forming a semiconductor layer on the buffer layer comprises depositing an amorphous indium gallium zinc oxide film on the buffer layer and patterning the amorphous indium gallium zinc oxide film to obtain a semiconductor layer.
  • the material of the passivation layer is selected from the group consisting of cerium oxide.
  • the material of the interlayer insulating layer is at least one selected from the group consisting of silicon oxide and silicon nitride.
  • the source region and the drain region of the semiconductor layer are plasma-treated after the gate is formed on the gate insulating layer.
  • the plasma treatment employs an H 2 plasma or an Ar plasma.
  • Figure 1 is a schematic view of the structure of the present invention
  • FIG. 2 is a schematic view showing the fabrication of a semiconductor layer on a buffer layer of the present invention
  • FIG. 3 is a schematic view showing a gate insulating layer and a gate electrode formed by the present invention.
  • Figure 4 is a schematic view showing the formation of an interlayer insulating layer of the present invention.
  • Figure 5 is a schematic view showing the fabrication of the source and the drain of the present invention.
  • Figure 6 is a schematic view showing the formation of a flat layer and a common electrode of the present invention.
  • Figure 7 is a schematic illustration of the fabrication of a passivation layer in accordance with the present invention.
  • an oxide array substrate of the present invention includes a glass substrate 1 and a buffer layer 2, a semiconductor layer 3, a gate insulating layer 4, a gate electrode 5, an interlayer insulating layer 6, and a source which are sequentially disposed. 7.
  • the drain 8 the flat layer 9, the common electrode 10, the passivation layer 11, and the pixel electrode 12;
  • the buffer layer 2 is formed on the substrate 1; the substrate may be a glass substrate;
  • a semiconductor layer 3 is formed on the buffer layer 2; the semiconductor layer 3 is made of indium gallium zinc oxide (IGZO);
  • the semiconductor layer 3 includes an active region 31 and a source region 32 and a drain region 33 disposed on both sides of the active region 31;
  • the gate insulating layer 4 and the gate 5 are sequentially formed on the active region 31; the material of the gate insulating layer is silicon oxide (SiOx);
  • the interlayer insulating layer 6 is formed on the buffer layer 2, the source region 32, and the drain region 33 that are not blocked by the semiconductor layer 3; the material of the interlayer insulating layer 6 is selected from silicon oxide (SiOx), nitrided At least one of silicon (SiNx); specifically, when the material of the interlayer insulating layer 6 is selected from silicon oxide, plasma treatment of the source region 32 and the drain region 33 is also required, and plasma treatment uses H 2 (hydrogen gas) a plasma or an Ar (argon) plasma;
  • a first via 61 is formed on the interlayer insulating layer 6 corresponding to the source region 32 and the drain region 33;
  • the source 7 and the drain 8 are in contact with the source region 32 and the drain region 33 via the first via 61, respectively;
  • the flat layer 9 is formed on the source 7, the drain 8 and the interlayer insulating layer 6 not blocked by the source 7 and the drain 8;
  • the common electrode 10 is formed on the flat layer 9;
  • the passivation layer 11 is formed on the common electrode 10 and the flat layer 9 not blocked by the common electrode 10.
  • the passivation layer 11 and the corresponding drain 8 on the flat layer 9 are formed with a second via 111 and a third via. 91;
  • the passivation layer 11 is made of yttria (Y 2 O 3 ) having high dielectric constant and high transmittance, thereby further increasing the storage capacitor size and reducing the storage capacitor area.
  • Y 2 O 3 yttria
  • the pixel electrode 12 is formed on the passivation layer 11 and is in contact with the drain 8 via the second via 111 and the third via 91.
  • the present invention fabricates an array substrate for in-plane switching (IPS) mode by using the above-described top gate self-aligned structure and using a high dielectric constant and high transmittance passivation layer 11 to reduce the occupation of the storage capacitor
  • the area is increased to increase the aperture ratio while increasing the size of the storage capacitor.
  • the invention also discloses a method for fabricating an array substrate, comprising the following steps:
  • Step 1 providing a substrate 1; the substrate 1 may be a glass substrate;
  • Step 2 forming a buffer layer 2 on the substrate 1; specifically, forming a buffer layer by chemical vapor deposition (CVD);
  • Step 3 forming a semiconductor layer 3 on the buffer layer 2 (as shown in FIG. 3); specifically, depositing an amorphous indium gallium zinc oxide (a-IGZO) film 34 (shown in FIG. 2) by deposition, and then The amorphous indium gallium zinc oxide film 34 is etched by a photolithography process to form a semiconductor layer 3; the semiconductor layer 3 includes an active region 31 and a source region 32 and a drain region 33 provided on both sides of the active region 31.
  • the deposition may be performed by physical vapor deposition (PVD); the photolithography process may be performed using an existing standard photolithography process;
  • Step 4 sequentially forming a gate insulating layer 4 and a gate 5 on the active region 31 of the semiconductor layer 3 (as shown in FIG. 3); specifically, the gate insulating layer 4 is made of silicon oxide (SiOx) material.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • the coating photoresist shown may be spin-coated; the etching process may be dry etching (Dry etch) or wet etching;
  • Step 5 forming an interlayer insulating layer 6 on the buffer layer 2 not blocked by the semiconductor layer 3, the source region 32 of the semiconductor layer 3, the drain region 33, and the gate electrode 5 (shown in FIG. 4); specifically, An interlayer insulating layer 6 is deposited on the buffer layer 2 not blocked by the semiconductor layer 3, the source region 32 of the oxide semiconductor 3, the drain region 33, and the gate electrode 5 by chemical vapor deposition (CVD).
  • the material of the interlayer insulating layer 6 may be selected from at least one of silicon oxide and silicon nitride;
  • Step 6 forming a first via 61 on the corresponding source region 32 and the drain region 33 on the interlayer insulating layer 6; specifically, forming a first via 61 by a photolithography process;
  • Step 7 forming a source 7 and a drain 8 respectively on the interlayer insulating layer 6.
  • the source 7 and the drain 8 are respectively in contact with the source region 32 and the drain region 33 via the first via 61 (FIG. 5). Shown); specifically, Forming an electrode metal film layer on the interlayer insulating layer 6 by physical vapor deposition (PVD), and patterning to form the source electrode 7 and the drain electrode 8 by a photolithography process; the photolithography process may adopt standard existing light The engraving process is carried out, and no specific limitation is made here;
  • Step 8 A flat layer 9 (shown in FIG. 6) is formed on the interlayer insulating layer 6 not blocked by the source 7 and the drain 8, and the source 7 and the drain 8; specifically, the specificity of the flat layer 9
  • the fabrication can be implemented by using the flat layer 9 in the thin film transistor array substrate in the prior art, and is not specifically limited herein;
  • Step 9 forming a common electrode 10 on the flat layer 9 (shown in FIG. 6); specifically, forming a transparent ITO film on the flat layer 9 by physical vapor deposition (PVD), and performing lithography on the ITO film Patterning to form a common electrode 10;
  • PVD physical vapor deposition
  • Step 10 forming a passivation layer 11 on the common electrode 10 and on the flat layer 9 not blocked by the common electrode 10 (shown in FIG. 7); specifically, the passivation layer 11 is made of yttria (Y 2 O 3 ) material. Specifically, a passivation layer 11 is formed on the common electrode 10 and on the flat layer 9 not blocked by the common electrode 10 by vapor deposition; the vapor deposition may be performed by atomic layer deposition (ALD) or physical vapor deposition. (PVD); the cerium oxide has high dielectric constant and high transmittance, thereby further increasing the storage capacitor size and reducing the storage capacitor area, improving pixel stability and the aperture ratio of the thin film transistor device;
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • Step 11 forming a second via 111 and a third via 91 respectively on the passivation layer 11 and the corresponding drain 8 on the flat layer 9; specifically, the passivation layer 11 and the flat layer 9 by a photolithography process Forming a second via 111 and a third via 91 at the drain 8;
  • Step 12 forming a pixel electrode 12 on the passivation layer 11, the pixel electrode 12 being in contact with the drain 8 via the second via 111 and the third via 91; specifically, using physical vapor deposition (PVD)
  • PVD physical vapor deposition
  • a transparent ITO film is formed on the passivation layer 11, and the ITO film is patterned by a photolithography process to form a pixel electrode 12, and the pixel electrode 12 passes through the second via 111, the third via 91 and the drain 8. contact.
  • the material of the interlayer insulating layer 6 is selected from silicon oxide
  • plasma is also performed on the source region 32 and the drain region 33 of the semiconductor layer 3 after the gate electrode 5 is formed on the gate insulating layer 4. deal with.
  • the plasma treatment uses a H 2 (hydrogen) plasma or an Ar (argon) plasma.
  • the passivation layer uses yttrium oxide (Y 2 O 3 ) to have excellent heat resistance, corrosion resistance and high temperature stability, high dielectric constant, good transparency, and can be doped with rare earth elements such as Nd 3+ . Performance; using a high dielectric constant and a high transmittance Y 2 O 3 as a passivation layer, the storage capacitor capacity can be increased while reducing the area of the storage capacitor, thereby increasing the aperture ratio and the transmittance.
  • Y 2 O 3 yttrium oxide
  • the present invention also discloses a display panel including the above array substrate, which will not be described herein.
  • the invention has the passivation layer material Y 2 O 3 with high dielectric constant and high transmittance in the IPS structure, increases the storage capacitor size, reduces the storage capacitor area, improves the pixel stability and the device aperture ratio;
  • the gate self-aligned structure can reduce a mask, make the overlap between the source drain and the gate smaller, and also reduce the parasitic capacitance of the TFT, thereby reducing the RC (Resistance-Capacitance). Delay to improve its response speed.

Landscapes

  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un substrat de réseau, comprenant un substrat de verre (1), une couche tampon (2), une couche semi-conductrice (3), une couche d'isolation de grille (4), une grille (5), une couche d'isolation intercouche (6), une source (7), un drain (8), une couche plate (9), une électrode commune (10), une couche de passivation (11), et une électrode de pixel (12). La présente invention porte également sur un procédé de fabrication d'un substrat de réseau et un panneau d'affichage. L'invention adopte une structure auto-alignée de grille supérieure capable de réduire la capacité parasite afin de réduire la taille d'une partie de chevauchement entre la source et le drain et la grille, ce qui permet d'améliorer le rapport d'ouverture et la capacité d'un condensateur de stockage tout en réduisant la surface occupée par le condensateur de stockage. De plus, l'invention réduit la capacité parasite d'un dispositif de transistor à couches minces, conduisant à un retard RC inférieur et à une vitesse de réponse améliorée du dispositif de transistor à couches minces.
PCT/CN2017/112188 2017-11-14 2017-11-21 Substrat de réseau, son procédé de fabrication et panneau d'affichage Ceased WO2019095408A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201711122463.5A CN107833893A (zh) 2017-11-14 2017-11-14 阵列基板及其制作方法、显示面板
CN201711122463.5 2017-11-14

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WO2019095408A1 true WO2019095408A1 (fr) 2019-05-23

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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109471279B (zh) * 2018-12-24 2021-11-12 Tcl华星光电技术有限公司 阵列基板以及液晶显示面板
CN109755260A (zh) * 2018-12-24 2019-05-14 惠科股份有限公司 一种显示面板、显示面板的制造方法和显示装置
CN109872690B (zh) * 2019-03-27 2020-09-08 武汉华星光电半导体显示技术有限公司 显示面板
CN115863351B (zh) * 2022-11-09 2025-10-17 福建华佳彩有限公司 一种高性能tft阵列基板及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020109811A1 (en) * 2001-02-13 2002-08-15 June-Ho Park Array substrate for reflective and transflective liquid crystal display devices and manufacturing method for the same
CN103489824A (zh) * 2013-09-05 2014-01-01 京东方科技集团股份有限公司 一种阵列基板及其制备方法与显示装置
CN105552080A (zh) * 2016-01-13 2016-05-04 广州新视界光电科技有限公司 基于金属氧化物薄膜晶体管的非挥发性存储器的制备方法
CN105552114A (zh) * 2015-12-14 2016-05-04 华南理工大学 一种基于非晶氧化物半导体材料的薄膜晶体管及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020109811A1 (en) * 2001-02-13 2002-08-15 June-Ho Park Array substrate for reflective and transflective liquid crystal display devices and manufacturing method for the same
CN103489824A (zh) * 2013-09-05 2014-01-01 京东方科技集团股份有限公司 一种阵列基板及其制备方法与显示装置
CN105552114A (zh) * 2015-12-14 2016-05-04 华南理工大学 一种基于非晶氧化物半导体材料的薄膜晶体管及其制备方法
CN105552080A (zh) * 2016-01-13 2016-05-04 广州新视界光电科技有限公司 基于金属氧化物薄膜晶体管的非挥发性存储器的制备方法

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