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WO2019066959A1 - Neurones et synapses ferroélectriques - Google Patents

Neurones et synapses ferroélectriques Download PDF

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Publication number
WO2019066959A1
WO2019066959A1 PCT/US2017/054586 US2017054586W WO2019066959A1 WO 2019066959 A1 WO2019066959 A1 WO 2019066959A1 US 2017054586 W US2017054586 W US 2017054586W WO 2019066959 A1 WO2019066959 A1 WO 2019066959A1
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Prior art keywords
voltage
gate
layer
ferroelectric material
ferroelectric
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Dmitri E. Nikonov
Sasikanth Manipatruni
Ian A. Young
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Intel Corp
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Intel Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/049—Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0499—Feedforward networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods

Definitions

  • a neural network is a computing system that performs inferences and learns patterns in the data by processing continuous signals with configurable circuit parameters and generally without task-specific programming. For example, a neural network may learn to identify a certain object from a picture/image.
  • a neural network comprises a collection of processing units, called “neurons,” that communicate with other neurons via connections, generally referred to as “synapses".
  • a neural network generally has a few thousand to a few million units and millions of connections.
  • most neural network algorithms are implemented in digital logic, which is inefficient and slow. Analog neuron circuits are inherently more efficient.
  • forming a neural network using analog techniques and circuits requires numerous transistors to implement a neuron function.
  • spin/nanomagnets based neurons implement a neural network with many fewer elements.
  • existing implementations are slow and power hungry.
  • Fig. 1 illustrates a model of a neural gate comprising multiple input synapses and a neuron.
  • Fig. 2 illustrates a schematic of a neuron implemented with complementary metal oxide semiconductor (CMOS) transistors.
  • CMOS complementary metal oxide semiconductor
  • FIG. 3 illustrates a schematic of a synapse implemented with CMOS transistors.
  • Fig. 4 illustrates a ferroelectric double gate transistor that behaves as a synapse in a neural network, in accordance with some embodiments.
  • Fig. 5A illustrates a plot showing ferroelectric material hysteresis for different ferroelectric crystals.
  • Fig. 5B illustrates a plot showing ferroelectric capacitor hysteresis charge versus voltage.
  • Fig. 6 illustrates a schematic of a ferroelectric neural gate, in accordance with some embodiments.
  • Fig. 7 A illustrates a cross-section of a material stack used for forming a ferroelectric layer of the ferroelectric double gate transistor, according to some embodiments.
  • Fig. 7B illustrates a cross-section of a super-lattice material stack used for forming a ferroelectric layer of the ferroelectric double gate transistor, according to some embodiments.
  • Fig. 8 illustrates a super-lattice of PbTiCb (PTO) with SrTi0 3 (STO) according to some embodiments of the disclosure.
  • Fig. 9 illustrates a smart device or a computer system or a SoC (System-on-
  • Chip having neural network formed of double ferroelectric gate transistors, according to some embodiments.
  • a neural gate circuit comprising double ferroelectric gate transistors as synapses and a ferroelectric capacitor as a neuron.
  • an input to the double ferroelectric gate transistor is encoded as a voltage pulse.
  • inputs are encoded as voltage pulses applied to one of the gates of the ferroelectric transistor synapse.
  • weights are encoded as a conductance of a segment of the transistor channel set by voltages applied to the other gate.
  • the output of the synapse e.g., an output of the double gate transistor that receives an input voltage pulse and an encoded weight
  • the output current pulses from the double gate ferroelectric transistors are summed as a charge in a conventional capacitor. In some embodiments, this charge is enforced on a ferroelectric capacitor which provides the output voltage being a non-linear threshold function of the charge. In some embodiments, the output voltage is used as input to subsequent states of the neural network.
  • the ferroelectric gates of the double ferroelectric gate transistor comprises a super-lattice which is formed with PTO/STO (e.g., repeated 2 to 100 times). In some embodiments, the super-lattice comprises of materials with improper ferroelectricity (e.g., STO/PTO,
  • the neural network formed by the double ferroelectric gate transistors use 20 times fewer number of regular transistors (e.g., complementary metal oxide semiconductor (CMOS) transistors) and thus much smaller area than analog or digital transistor based solutions.
  • CMOS complementary metal oxide semiconductor
  • the operation energy of the neural network formed by the double ferroelectric gate transistors is much smaller than that of a neural network formed by CMOS transistors.
  • the operation delay of the neural network formed by the double ferroelectric gate transistors is much smaller than that of the neural network formed by CMOS transistors.
  • the ferroelectric polarization in the double ferroelectric gate transistor of some embodiments holds weights as non-volatile memory. As such, weight voltages may persist even if the power to a processor is shut off or if a processor is put to a sleep state.
  • the neural network formed by the double ferroelectric gate transistors is also better in performance than spintronic neural networks.
  • the double ferroelectric gate transistor of some embodiments has lower operation energy compared to spintronic neural network gate.
  • the operation energy for a double ferroelectric gate transistor of some embodiments is approximately 1 fJ (femto Joule) instead of approximately 30 f J per spintronic gate.
  • the double ferroelectric gate transistor of some embodiments has lower operation delay compared to spintronic neural network gate.
  • the operation delay of a double ferroelectric gate transistor of some embodiments is approximately 300 picoseconds (ps) instead of approximately 10 nanoseconds (ns) per spintronic neural network gate.
  • the signal in neural network formed by the double ferroelectric gate transistors is carried by charge currents, and as such the distance from the input to the output nodes is not limited as in spin-based interconnects where spins degrade over a very short interconnect distance.
  • signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.
  • connection means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices.
  • coupled means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.
  • circuit or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.
  • signal may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal.
  • the meaning of "a,” “an,” and “the” include plural references.
  • the meaning of "in” includes “in” and "on.”
  • phrases “A and/or B” and “A or B” mean (A), (B), or (A and B).
  • phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
  • the terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.
  • Fig. 1 illustrates a model 100 of a neural gate comprising multiple input synapses and a neuron.
  • a neural gate circuit is a building block of neural networks. It produces an output 'f which is a non-linear function of an array of inputs x with n elements "xi" and an array of stored weights "wi", where is an integer index.
  • Model 100 expresses a neural gate function:
  • g() is a step-like threshold function
  • b is an offset that can be added to the sum.
  • the synapses perform the product of input 'x' with its corresponding weights 'w'.
  • These synapses are elements of the neural gate executing analog multiplication.
  • the neuron is the element performing summation of the synapse inputs and applying the non-linear threshold function.
  • Figs. 2-3 illustrate complex CMOS implementations of neurons that use multiple transistors for a single synapse and single neuron.
  • Fig. 2 illustrates a schematic of a neuron 200 implemented with CMOS transistors. It comprises an input differential pair integrator (DPI) circuit used as a low-pass filter (MLI-3), a spike-event generating amplifier with current-based positive feedback (MAI- ⁇ ), a spike reset circuit with refractory period functionality (MRI-6) and a spike-frequency adaptation mechanism implemented by an additional DPI low-pass filter (MGI-6).
  • DPI input differential pair integrator
  • MMI-3 low-pass filter
  • MAI- ⁇ spike-event generating amplifier with current-based positive feedback
  • MRI-6 spike reset circuit with refractory period functionality
  • MMI-6 additional DPI low-pass filter
  • the DPI block MLI-3 models the neuron's leak conductance; it produces exponential sub-threshold dynamics in response to constant input currents.
  • the neuron's membrane capacitance is represented by the capacitor Cmem while Sodium channel activation and inactivation dynamics are modeled by the positive-feedback circuits in the spike- generation amplifier MAI-6.
  • the spike-generation amplifier MAI-6 implements current-based positive feedback (modeling both sodium activation and inactivation conductances) and produces address-events at extremely low-power operation.
  • the reset MRI-6 block models the Potassium conductance and refractory period functionality.
  • the reset block (MRI-6) resets the neuron and keeps it in a resting state for a refractory period, set by the Vref bias voltage.
  • the spike-frequency adaptation block MGI-6 models the neuron's Calcium conductance that produces the after-hyper-polarizing current Iahp, which is proportional to the neuron's mean firing rate.
  • the spike-frequency adaptation block is a low-pass filter (MGI-6) which integrates the spikes and produces a slow after hyper- polarizing current Iahp responsible for spike-frequency adaptation.
  • Fig. 3 illustrates a schematic of a synapse 300 implemented with CMOS transistors.
  • Synapse 300 is a DPI synapse circuit, including short term plasticity, N-Methyl- D- Aspartate (NMD A) voltage gating, and conductance-based functional blocks.
  • the short- term depression block is implemented by MOSFETs Msi-3; the basic DPI dynamics are implemented by the block MDI- 6 ; the NMDA voltage gated channels are implemented by MNI-2, and conductance based voltage dependence is achieved with MGI-2.
  • neuron 200 and synapse 300 are used in a neural network that includes millions of neuron 200 and synapse 300, the area and power of the integrated circuit becomes prohibitive.
  • the neural network of some embodiments formed by double ferroelectric gate transistors use 20 times fewer the number of regular transistors than those of neuron 200 and synapse 300 and thus a much smaller area and power.
  • the operation energy of the neural network formed by the double ferroelectric gate transistors is much smaller per transistor than neuron 200 and synapse 300.
  • the operation energy for a neuron or synapse implemented by double ferroelectric gate transistor of some embodiments is approximately 1 femto-Joules (fJ) instead of 1 pico- Joules (pJ) per CMOS neuron 200 or synapse 300.
  • the operation delay of the neural network formed by the double ferroelectric gate transistors is much smaller than a CMOS neuron 200 and synapse 300.
  • the operation delay of a double ferroelectric gate neuron or synapse of some embodiments is approximately 300 picoseconds (ps) instead of approximately 10 nanoseconds (ns) per CMOS neuron 200 or synapse 300.
  • Fig. 4 illustrates a cross-section of ferroelectric double gate transistor 400 that behaves as a synapse in a neural network, in accordance with some embodiments.
  • transistor 400 is a five terminal device which comprises substrate 401, source region (or source) 402, drain region (or drain) 403, first gate including ferroelectric material 404a and contact 405a, and second gate including ferroelectric material 404b and contact 405b, and dielectric gate layer 406 (e.g., S1O2, low-k dielectric, or high-k dielectric).
  • the five terminals are the source terminal, drain terminal, first gate terminal, second gate terminal, and bulk/substrate/body terminal.
  • the first and second gates are positioned between the source region and the drain region.
  • the two gates are separated by oxide, and are independently controllable.
  • a channel is formed under the two gates electrically connecting the source and drain when applied voltages on Vgl and Vg2.
  • source voltage Vs is applied to the source terminal
  • drain voltage Vd is applied to the drain terminal
  • first gate voltage Vgl is applied to the first gate terminal
  • Vg2 is applied to the second gate terminal.
  • ferroelectric double gate transistor 400 is shown as a high level double gate transistor, a person skilled in the art can adjust doping of the substrate, drain, and source regions to make the ferroelectric double gate transistor a p-type or n-type transistor.
  • the polarity of the bias voltages Vgl and Vg2 can be adjusted to properly turn on the ferroelectric double gate transistor.
  • the thickness of ferroelectric material 404a is such that it does not exhibit the hysteresis.
  • the polarization Pgl of ferroelectric material 404a and the corresponding charge in the channel under it is a function only of the value of Vgl.
  • the thickness of ferroelectric material 404b is such that it has hysteresis.
  • polarization Pg2 of ferroelectric material 404b can be partially switched between values Ps and -Ps along a vertical direction. In this case, polarization Pg2 is determined by the history of value and duration of pulses of voltage Vg2.
  • a constant voltage Vs is applied to source 402 to create source-to-drain current while drain 403 serves as a current output. Below the threshold of the transistor, the current is approximately given by:
  • Vds is the source-to-drain voltage
  • ⁇ , / ' are constants determined by the transistor parameters
  • ⁇ is the thermal energy.
  • the inputs are encoded as .
  • the input voltage is encoded to be in a range of -1 Volt (V) to 1 V.
  • the voltage of Vgl is below or at the threshold of ferroelectric material 404a or the threshold of the ferroelectric double gate transistor 400.
  • Vgl is applied to the first gate as a short pulse to pass sufficient charge through the transistor channel.
  • a pulse of voltage Vg2 is applied to contact 404b to set channel conductance representing weight wi of equation (1).
  • the weight wi sets a value of conductance of a segment under the second gate.
  • the voltage Vg2 is generated by another voltage source, and the voltage of weight wi (e.g., voltage of Vg2) is below or near the threshold of the ferroelectric material 404b.
  • most of the voltage drop occurs under this segment of the channel formed between source 402 and drain 403.
  • the conductance of the channel under the second gate can be varied over a wide range by Vg2.
  • ferroelectric material 404b holds the charge associated with the weight wi as a non-volatile memory. As such, in some embodiments, additional circuitry and memory devices may not be required to maintain the voltage associated with weight wi.
  • a capacitive device is charged by the drain current from transistor 400.
  • the drain current represents the product of the applied voltages xi and wi.
  • the complexity of circuit 300 of Fig. 3 is reduced to a single double gate ferroelectric transistor in accordance with various embodiments. While the embodiments are described with reference to double gate ferroelectric transistor, other non- ferroelectric double gate transistors can also be used to generate a drain current that represents the product of the applied voltages xi and wi.
  • the ferroelectric material 404a/b can be replaced with a non-ferroelectric high-K dielectric.
  • the first gate is directly coupled or adjacent to dielectric layer 406.
  • a regular high-k dielectric can be used instead of ferroelectric material 404a. All other connections and applications of voltages to the terminals remain the same as discussed above with reference to Fig. 4.
  • Fig. 5A illustrates plot 500 showing ferroelectric material (e.g., material
  • a ferroelectric material exhibits ferroelectricity which is a property by which a spontaneous electric polarization can be revered by an electric field (e.g., applied voltage).
  • an electric field e.g., applied voltage
  • the induced polarization 'P' is almost exactly proportional to the applied external electric field E.
  • the polarization is a linear function of the applied electric field or voltage.
  • Ferroelectric materials demonstrate a spontaneous non-zero polarization even when the applied electric field E is zero. As such, the spontaneous polarization can be reversed by an applied electric field in the opposite direction.
  • the thresholding function of the neuron as described with reference to Fig. 1 (and equation 1) is similar to one of the branches of curve 100 in plot 500 which makes the ferroelectric material a great candidate for mimicking the threshold function of the neural gate function of equation 1.
  • Fig. 5B illustrates plot 520 showing ferroelectric capacitor hysteresis charge versus voltage.
  • Plot 520 shows that there is a non-linear behavior or function of voltage versus charge for a ferroelectric capacitor.
  • one branch of the ferroelectric material hysteresis curve is used for thresholding function of a neuron without the need for polarization reversal.
  • Fig. 6 illustrates a schematic of a ferroelectric neural gate 600, in accordance with some embodiments.
  • a plurality of double gate transistors 601 i- n are organized to receive a plurality of input voltages xi and weights wi.
  • double gate transistor 6011 receives xi and wi in electrodes marked Vgl and Vg2, respectively
  • double gate transistor 6OI2 receives X2 and W2 in electrodes marked Vgl and Vg2, respectively
  • double gate transistor 601 n receives x n and w n in electrodes marked Vgl and Vg2, respectively.
  • Vs for all double gate transistors of the plurality is provided as a constant voltage to generate a source-to-drain current.
  • the output drain current from each double gate transistor is summed as charge by capacitor 602, in accordance with some embodiments.
  • drain current II from double gate transistor 6011, drain current 12 from double gate transistor 6OI2, and drain current In from double gate transistor 601 n are summed at capacitor 603.
  • capacitor 602 is any state of the art or conventional capacitor.
  • a first terminal of capacitor 602 is coupled to drains of each double gate transistor, and a second terminal of capacitor 602 is coupled to a second capacitor 603.
  • the multiplication of input voltage xi and weight wi occurs below the threshold of the double gate transistor, and the drain current from the double gate transistor represents the product of input voltage xi and weight wi.
  • ferroelectric capacitor 603 comprises metal contact 603a (e.g., any suitable conducting material), ferroelectric material 603c (e.g., same as ferroelectric material 404a/b), and metal contact 603b.
  • metal contact 603a e.g., any suitable conducting material
  • ferroelectric material 603c e.g., same as ferroelectric material 404a/b
  • metal contact 603b e.g., metal contact 603b.
  • the output voltage Vo encoding the output value "xo" is used as input to subsequent states of the neural network.
  • the output "xo" is provided as input to a plurality of double gate transistors 604i- m , where 'm' is an integer.
  • double gate transistors 604 belong to different neural gates, or in other words, connected to different neuron elements. As such, a cascaded network of neurons and synapses can be realized in accordance with some embodiments.
  • the voltage Vo is provided to the first gate electrodes of transistors 604.
  • ferroelectric capacitor 603 is formed in the backend of the die.
  • backend generally refers to a section of a die which is opposite of a "frontend” and where an IC package couples to IC die bumps.
  • high level metal layers e.g., metal layer 6 and above in a ten metal stack die
  • vias that are closer to a die package are considered part of the backend of the die.
  • Fig. 7A illustrates a cross-section of a material stack 700 used for forming a ferroelectric layer of the ferroelectric double gate transistor 400 and/or ferroelectric capacitor 604, according to some embodiments.
  • material stack 700 comprises a first conductive layer 701a, a layer 701b comprising perovskite, a second conductive layer 701c, and a conductive seed layer 701 d.
  • first and second conductive layers 701a/c are conductive oxides that include one of the following elements: Sr, Ru, La, Sr, Mn, Nb, Cr, or O.
  • first and second conductive layers 701a/c are conductive oxides which comprise: SrRuC , (La,Sr)Co03 [LSCO], Lao.sSro.sMni xNLO, Cu- doped SrFeo.9Nbo.1O3 , (La,Sr)Cr03.
  • layer 702b comprising perovskite is sandwiched between first and second conductive layers 701a/c such that layer 702b is adjacent to first and second conductive layers 701 a/c.
  • layer 702b comprises a low leakage perovskite.
  • Perovskites have cubic structure with a general formula of ABO3, where 'A' includes one of an alkaline earth or rare earth element (e.g., Sr, Bi, Ba, etc.) while 'B' is one of a 3d, 4d, or 5d transition metal element (e.g., Ti, Fe, etc.).
  • layer 702b includes one of SrTi0 3 , BiFeCb, BiTiCb, or BaTiCb.
  • a seed layer (or starting layer) 701 d is deposited first and then layers 701c, 701b, 701a are deposited.
  • the seed layer 701d is used to template the conductive layer 701c.
  • a seed layer 70 le is deposited in addition to or instead of 701d.
  • seed layer 701d/e includes one of: Ti, Al, Nb, La, or STO (SrTiCb).
  • seed layer 701d/e includes one of: TiAl, Nb doped STO, or La doped STO.
  • Fig. 7B illustrates a cross-section of a super-lattice material stack 720 used for forming a ferroelectric layer of the ferroelectric double gate transistor 400 and/or ferroelectric capacitor 604, according to some embodiments.
  • the capacitor of Fig. 7B is similar to the capacitor of Fig. 7A except that perovskite layer 701b is replaced by super lattice 701b.
  • super lattice 801b includes alternating layers of materials.
  • layer 802 comprises PbTi03
  • layer 803 comprises SrTi03
  • layer 804 comprises PbTi03
  • layer 806 comprises SrTi03, and so on (e.g., 2 to 100 times).
  • one layer can be a non-polar oxide of the type (A +2 B +4 03) such as SrZr03
  • another layer can be a polar oxide of the type (A +1 B +5 03 or A + B + 03) such as LaA103 and LaGa03
  • 'A' can comprise one of: La, Sr, Pb, Pr, Nd, Sm, Gd, Y, Tb, Dy, Ho, Er, Tm, Lu, Ce, Li, Na, K, Rb, or Ag
  • 'B' can comprise Ga, Al, Sc, In, Ta, Ti, or Zr.
  • the two or more layers of super lattice 701b has a thickness that extends from the first metal layer 701a to the second metal layer 701c. In some embodiments the thickness is in a range of 2 nm (nanometers) to 100 nm. In some embodiments, the two or more layers of super lattice 701b have a width which is
  • the super lattice is formed with PTO/STO (e.g., repeated 2 to 100 times) for capacitance enhancement.
  • the super lattice comprises of materials with improper ferroelectricit (e.g., STO/PTO, LuFe03/LuFe204).
  • Fig. 8 illustrates a super lattice 800 (e.g., 720) of PbTiCb (PTO) with SrTiCb
  • the first supper lattice (a) is FEz(T3- mode) giving rise to a polarization P z .
  • the second super lattice (b) is AFD Z0 (M 4 - mode) with oxygen rotation angle ⁇ .
  • the third super lattice is AFDzi (M2+ mode) with oxygen rotation angle ⁇ . Charge is stored in rotational degree of freedom of oxygen atoms indicated by the rotational arrows in super lattice (a) and (c).
  • Fig. 9 illustrates a smart device or a computer system or a SoC (System-on-
  • embodiments can be used to charge any or all blocks of SoC 2100, in accordance with some embodiments.
  • the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals.
  • the transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices.
  • MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here.
  • a TFET device on the other hand, has asymmetric Source and Drain terminals.
  • BJT PNP/NPN Bi-polar junction transistors
  • BiCMOS BiCMOS
  • CMOS complementary metal oxide semiconductor
  • Fig. 9 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used.
  • computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.
  • computing device 1600 includes first processor 1610 and network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant. Any of the various blocks of computing device 1600 can have or use the super capacitor of various embodiments.
  • processor 1610 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means.
  • processor 1610 includes neural network formed of double ferroelectric gate transistors.
  • other blocks of SoC 1600 can also include neural network formed of double ferroelectric gate transistors.
  • the processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed.
  • the processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device.
  • the processing operations may also include operations related to audio I/O and/or display I/O.
  • computing device 1600 includes audio subsystem
  • Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.
  • computing device 1600 comprises display subsystem
  • Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600.
  • Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user.
  • display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display.
  • display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.
  • computing device 1600 comprises I/O controller 1640.
  • I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.
  • I/O controller 1640 can interact with audio subsystem
  • display subsystem 1630 For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.
  • I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600.
  • the input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).
  • computing device 1600 includes power management
  • Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600. In some embodiments, Memory subsystem 1660 includes the scheme of analog in-memory partem matching with the use of resistive memory elements.
  • the machine-readable medium may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions.
  • embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).
  • BIOS a computer program
  • a remote computer e.g., a server
  • a requesting computer e.g., a client
  • a communication link e.g., a modem or network connection
  • computing device 1600 comprises connectivity 1670.
  • Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices.
  • the computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.
  • Connectivity 1670 can include multiple different types of connectivity.
  • the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674.
  • Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards.
  • Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.
  • computing device 1600 comprises peripheral connections 1680.
  • Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections.
  • the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from” 1684) connected to it.
  • the computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600.
  • a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.
  • the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors.
  • Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.
  • USB Universal Serial Bus
  • MDP MiniDisplayPort
  • HDMI High Definition Multimedia Interface
  • Firewire or other types.
  • Example 1 An apparatus comprising: a substrate; a source; a drain; a first gate including a ferroelectric material, wherein the first gate is adj acent to the source; and a second gate including the ferroelectric material, wherein the second gate is adjacent to the drain.
  • Example 2 The apparatus of example 1 comprises a first voltage source to apply a voltage to the source.
  • Example 3 The apparatus of example 2, wherein the first voltage source is to apply the voltage as a constant voltage.
  • Example 4 The apparatus according to any one of examples 1 to 3 comprises a second voltage source to apply a first encoded voltage to the first gate, wherein the first encoded voltage is above a threshold level of the ferroelectric material.
  • Example 5 The apparatus of example 4, wherein the second voltage source is to apply the first encoded voltage as a pulse.
  • Example 6 The apparatus according to any one of examples 1 to 4 comprises a third voltage source to apply a third encoded voltage to the second gate, wherein the third encoded voltage is close to the threshold level of the ferroelectric material.
  • Example 7 The apparatus of example 6, wherein the drain is to provide a current which is proportional to a product of the first encoded voltage and the second encoded voltage.
  • Example 8 The apparatus according to any of the preceding examples, wherein the ferroelectric material includes: a first layer comprising metal; a second layer comprising metal; and two or more layers coupled between the first and second layers, wherein the two or more layers include a first layer comprising a conductive oxide, a second layer comprising a conductive oxide, and a third layer comprising a perovskite, wherein the third layer is adjacent to the first and second layers.
  • Example 9 The apparatus of example 8, wherein the two or more layers comprises a fourth layer adjacent to one of the first or second layers, wherein the fourth layer comprises a conductive seed layer.
  • Example 10 The apparatus of example 9, wherein the fourth layer includes one of: Ti, Al, Nb, La, or STO.
  • Example 11 The apparatus of example 9, wherein the fourth layer includes one of: TiAl, Nb doped STO, or La doped STO.
  • Example 12 The apparatus according to any of examples 8 to 9, wherein the first and second layers include one of: Sr, Ru, La, Sr, Mn, Nb, Cr, or O.
  • Example 13 The apparatus according to any of examples 8 to 9, wherein the first and second layers include one of: SrRu03, (La,Sr)Co03 [LSCO], Lao sSro sMni xNLO, Cu-doped SrFeo.9Nbo.1O3, or (La,Sr)Cr0 3 .
  • Example 14 The apparatus according to any of examples 8 to 9, wherein the third layer includes one of: Sr, Ti, O, Bi, Fe, or Ba.
  • Example 15 The apparatus according to any of examples 8 to 9, wherein the third layer includes one of: SrTi03, BiFe03, BiTe03, or BaTi03.
  • Example 16 The apparatus of example 8, wherein the third layer includes a super lattice of PbTi0 3 (PTO) and SrTi0 3 (STO).
  • PTO PbTi0 3
  • STO SrTi0 3
  • Example 17 The apparatus of example 16, wherein the super lattice of PTO and STO are repeated in a range of 2 to 100 times.
  • Example 18 An apparatus comprising: a plurality of double gate transistors wherein each double gate transistor is to receive a first voltage and a second voltage on its respective gates; and a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to one of source or drain terminals of each double gate transistor of the plurality of double gate transistors.
  • Example 19 The apparatus of example 18 comprises a second capacitor including ferroelectric material, wherein the second capacitor is coupled to the second terminal of the capacitor.
  • Example 20 The apparatus of example 19 comprises a second plurality of double gate transistors, wherein one of gate terminals of each double gate transistor of the second plurality is coupled to the second capacitor.
  • Example 21 The apparatus of example 18, wherein each double gate transistor comprises a first gate and a second gate which include ferroelectric material.
  • Example 22 The apparatus of example 18 comprises a first voltage source to apply a first encoded voltage to a first gate of a first double gate transistor of the plurality, wherein the first gate comprises a ferroelectric material, and wherein the first encoded voltage is above a threshold level of a ferroelectric material.
  • Example 23 The apparatus of example 22, wherein the first voltage source is to apply the first encoded voltage as a pulse.
  • Example 24 The apparatus of example 22 comprises a second voltage source to apply a second encoded voltage to a second gate of the first double grate transistor of the plurality, wherein the second gate comprises a ferroelectric material, and wherein the second encoded voltage is close to the threshold level of the ferroelectric material.
  • Example 25 The apparatus of example 24, wherein the ferroelectric material is according to any one of examples 8 to 17.
  • Example 26 A system comprising: a memory; a processor coupled to the memory, the processor including an apparatus according to any one of apparatus examples 1 to 17 or any one of apparatus examples 18 to 25; and a wireless interface to allow the processor to communicate with another device.
  • Example 27 A method comprising: forming a substrate; forming a source; forming a drain; forming a first gate including a ferroelectric material, wherein the first gate is adjacent to the source; and forming a second gate including the ferroelectric material, wherein the second gate is adjacent to the drain.
  • Example 28 The method of example 27 comprises applying a voltage to the source as a constant voltage.
  • Example 29 The method according to any one of examples 27 to 28 comprises applying a first encoded voltage to the first gate, wherein the first encoded voltage is above a threshold level of the ferroelectric material.
  • Example 30 The method of example 29 comprises applying the first encoded voltage as a pulse.
  • Example 31 The method according to any one of examples 27 to 29 comprises applying a third encoded voltage to the second gate, wherein the third encoded voltage is close to the threshold level of the ferroelectric material.
  • Example 32 The method of example 31 comprises providing a current through the drain which is proportional to a product of the first encoded voltage and the second encoded voltage.
  • Example 33 The method according to any one of examples 27 to 32 comprises forming the ferroelectric material by: forming a first layer comprising metal; forming a second layer comprising metal; and forming two or more layers coupled between the first and second layers, wherein the two or more layers include a first layer comprising a conductive oxide, a second layer comprising a conductive oxide, and a third layer comprising a perovskite, wherein the third layer is adjacent to the first and second layers.
  • Example 34 The method of example 33, wherein forming the two or more layers comprises forming a fourth layer adjacent to one of the first or second layers, wherein the fourth layer comprises a conductive seed layer.
  • Example 35 The method of example 34, wherein the fourth layer includes one of: Ti, Al, Nb, La, or STO.
  • Example 36 The method of example 34, wherein the fourth layer includes one of: TiAl, Nb doped STO, or La doped STO.
  • Example 37 The method according to any of examples 33 to 34, wherein the first and second layers include one of: Sr, Ru, La, Sr, Mn, Nb, Cr, or O.
  • Example 38 The method according to any of examples 33 to 34, wherein the first and second layers include one of: SrRu03, (La,Sr)Co03 [LSCO], Lao sSro sMni xNLO, Cu-doped SrFeo.9Nbo.1O3, or (La,Sr)Cr0 3 .
  • Example 39 The method according to any of examples 33 to 34, wherein the third layer includes one of: Sr, Ti, O, Bi, Fe, or Ba.
  • Example 40 The method according to any of examples 33 to 34, wherein the third layer includes one of: SrTi03, BiFe03, BiTe03, or BaTi03.
  • Example 41 The method of example 33, wherein the third layer includes a super lattice of PbTi0 3 (PTO) and SrTi0 3 (STO).
  • PTO PbTi0 3
  • STO SrTi0 3
  • Example 42 The method of example 41, wherein the super lattice of PTO and
  • Example 43 An apparatus comprising: a substrate; a source; a drain; a first gate adjacent to the source; and a second gate including a ferroelectric material, wherein the second gate is adjacent to the drain and the layer.
  • Example 44 The apparatus of example 43, wherein the first gate is directly adjacent to a layer comprising dielectric.
  • Example 45 The apparatus of example 43 comprises a first voltage source which is to apply a constant voltage to the source.
  • Example 46 The apparatus according to any one of examples 43 to 45 comprises a second voltage source to apply a first encoded voltage to the first gate.
  • Example 47 The apparatus of example 46, wherein the second voltage source is to apply the first encoded voltage as a pulse.
  • Example 48 The apparatus according to any one of examples 43 to 47 comprises a third voltage source to apply a third encoded voltage to the second gate, wherein the third encoded voltage is close to the threshold level of the ferroelectric material.
  • Example 49 The apparatus of example 48, wherein the drain is to provide a current which is proportional to a product of the first encoded voltage and the second encoded voltage.
  • Example 50 The apparatus according to any of the preceding claims, wherein the ferroelectric material includes: a first layer comprising metal; a second layer comprising metal; and two or more layers coupled between the first and second layers, wherein the two or more layers include a first layer comprising a conductive oxide, a second layer comprising a conductive oxide, and a third layer comprising a perovskite, wherein the third layer is adjacent to the first and second layers.
  • Example 51 The apparatus of example 50, wherein the two or more layers comprises a fourth layer adj acent to one of the first or second layers, wherein the fourth layer comprises a conductive seed layer.
  • Example 52 The apparatus of example 51, wherein the fourth layer includes one of: Ti, Al, Nb, La, or STO.
  • Example 53 The apparatus of example 51, wherein the fourth layer includes one of: TiAl, Nb doped STO, or La doped STO.
  • Example 54 The apparatus according to any of examples 50 to 51 , wherein the first and second layers include one of: Sr, Ru, La, Sr, Mn, Nb, Cr, or O.
  • Example 55 The apparatus according to any of examples 50 to 51, wherein the first and second layers include one of: SrRuCb, (La,Sr)CoCb [LSCO], Lao.5Sro.5Mn1- JMixO, Cu-doped SrFeo.9Nbo.1O3, or (La,Sr)Cr0 3 .
  • Example 56 The apparatus according to any of examples 50 to 51, wherein the third layer includes one of: Sr, Ti, O, Bi, Fe, or Ba.
  • Example 57 The apparatus according to any of examples 51 to 51, wherein the third layer includes one of: SrTiC , BiFeCb, BiTeCb, or BaTiC .
  • Example 58 The apparatus of example 50, wherein the third layer includes a super lattice of PbTiCb (PTO) and SrTiCb (STO).
  • PTO PbTiCb
  • STO SrTiCb
  • Example 59 The apparatus of example 58, wherein the super lattice of PTO and STO are repeated in a range of 2 to 100 times.

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Abstract

L'invention concerne un appareil qui comprend : un substrat ; une source ; un drain ; une première grille comprenant un matériau ferroélectrique, la première grille étant adjacente à la source ; et une seconde grille comprenant le matériau ferroélectrique, la seconde grille étant adjacente au drain.
PCT/US2017/054586 2017-09-29 2017-09-29 Neurones et synapses ferroélectriques Ceased WO2019066959A1 (fr)

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US20230231030A1 (en) * 2020-06-16 2023-07-20 Forschungszentrum Jülich GmbH Neurons and synapses with ferroelectrically modulated metal-semiconductor schottky diodes and method

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