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WO2019049980A1 - Circuit de reconfiguration - Google Patents

Circuit de reconfiguration Download PDF

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Publication number
WO2019049980A1
WO2019049980A1 PCT/JP2018/033178 JP2018033178W WO2019049980A1 WO 2019049980 A1 WO2019049980 A1 WO 2019049980A1 JP 2018033178 W JP2018033178 W JP 2018033178W WO 2019049980 A1 WO2019049980 A1 WO 2019049980A1
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WO
WIPO (PCT)
Prior art keywords
switch
wiring
circuit
crossbar
lut
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2018/033178
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English (en)
Japanese (ja)
Inventor
幸秀 辻
阪本　利司
信 宮村
竜介 根橋
あゆ香 多田
旭 白
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NEC Corp
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NEC Corp
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Publication date
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Publication of WO2019049980A1 publication Critical patent/WO2019049980A1/fr
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention relates to a reconfiguration circuit whose logic circuit can be reconfigured.
  • the programmable logic integrated circuit (also referred to as a reconfiguration circuit) can reconfigure various logic circuits by rewriting internal setting information.
  • FIG. 29 is a circuit diagram of a general reconstruction circuit 100.
  • the reconfiguration circuit 100 includes a plurality of reconfiguration circuits 101 (hereinafter, referred to as LB: Logic Block) and a plurality of routing units 102 (hereinafter, referred to as RB: Routing Block).
  • the LB includes a look-up table (hereinafter referred to as LUT) and a flip-flop FF.
  • LUT look-up table
  • FF flip-flop FF
  • the number of configurable logics can be adjusted by designing a logic block (hereinafter, CLB: Configurable Logic Block) having LBs and RBs of a certain size. And, by adjusting the number of CLBs arranged to interconnect, it is possible to manufacture a semiconductor chip including reconfiguration circuits of different circuit sizes in accordance with customer needs. In the fields of image processing and communication, various semiconductor chips including reconstruction circuits have been developed.
  • CLB Configurable Logic Block
  • SRAM switches including pass transistors and static random access memories (SRAMs) have been developed as reconfiguration circuits or CLBs.
  • SRAMs static random access memories
  • Patent Document 1 discloses a programmable logic integrated circuit having a crossbar switch including a variable resistance element and a logic circuit logically configured by the crossbar switch. According to the circuit of Patent Document 1, since the transistor and the memory can be formed in different layers by using the resistance change element, the chip area can be reduced.
  • Patent Document 2 discloses an arithmetic processing unit having two identical arithmetic units in an arithmetic processing unit and capable of performing arithmetic processing on different operand input data at the same time.
  • Patent Document 3 image values from an image signal source are sequentially stored in a frame memory, and image values stored in a frame memory are sequentially read at a speed faster than the writing speed to the frame memory and displayed on a display device.
  • An image processing apparatus is disclosed.
  • the devices of Patent Document 2 and Patent Document 3 can detect a defect caused by the aged deterioration of the element.
  • the application is interrupted due to the switching process to the alternative process in another circuit block, and the chip before and after the fault occurs. Performance degradation may occur.
  • it is necessary to simultaneously operate at least triple redundant circuits in parallel, which increases the overhead of the circuit area.
  • the object of the present invention is to solve the above-mentioned problems, and while implementing an application at a high density as a reconfiguration circuit without redundant bits, provide redundancy with a small circuit overhead to enable continuous application operation.
  • An object of the present invention is to provide a reconstruction circuit.
  • a reconfiguration circuit includes a crossbar memory configured of a crossbar switch circuit including a plurality of switch cells including complementary elements, and at least one of a plurality of signals input from the crossbar memory.
  • a first lookup table configured by a multiplexer that selects and outputs the second lookup table configured by the crossbar memory and the multiplexer; an output node of the first lookup table; And a switch connected to the output node of the second look-up table and electrically switching the output node of the first look-up table and the output node of the second look-up table to a conductive or non-conductive state.
  • a reconfiguration circuit which enables continuous application operation by providing redundancy with a small amount of circuit overhead while mounting an application at high density as a reconfiguration circuit without redundant bits. Becomes possible.
  • FIG. 1 is a block diagram showing a configuration of a reconfiguration circuit according to a first embodiment of the present invention. It is a block diagram which shows the structure of the look-up table (LUT: Lookup Table) comprised by the reconstruction circuit which concerns on the 1st Embodiment of this invention.
  • FIG. 6 is a conceptual diagram showing a configuration of a resistance change element included in a switch cell of a crossbar switch circuit for configuring a crossbar memory of a LUT included in the reconfiguration circuit according to the first embodiment of the present invention. It is a symbolic expression of the resistance change element contained in the switch cell of the crossbar switch circuit which comprises the crossbar memory of LUT contained in the reconfiguration
  • FIG. 3 is a circuit diagram showing a connection state of a crossbar switch circuit and a switching control circuit included in the reconfiguration circuit according to the first embodiment of the present invention. It is a conceptual diagram which shows the structure of the interface of the crossbar switch circuit which comprises the crossbar memory of LUT comprised by the reconfiguration
  • FIG. 1 It is a conceptual diagram which shows the structure of the interface of the crossbar switch circuit which comprises the crossbar memory of LUT comprised by the reconfiguration
  • FIG. 7 is a circuit diagram for describing a switch cell redundant in an operation (reliable mode) of the reconfiguration circuit according to the first embodiment of the present invention.
  • FIG. 2 is a conceptual view of a large scale logic integrated circuit in which logic cells (hereinafter, CLB: Configurable Logic Block) including LUTs included in the reconfiguration circuit according to the first embodiment of the present invention are arranged. It is a conceptual diagram which shows LUT using the crossbar switch circuit which made the switch cell redundant.
  • FIG. 6 is a conceptual diagram showing an example of making a LUT highly reliable using a crossbar switch circuit in which switch cells are made redundant.
  • FIG. 6 is a conceptual diagram showing a LUT in which two crossbar switch circuits are connected to make them redundant.
  • FIG. 6 is a circuit diagram showing a connection state of a crossbar switch circuit and a switching control circuit included in a reconfiguration circuit according to a second embodiment of the present invention. It is a conceptual diagram which shows the structure of LUT comprised by the reconstruction circuit which concerns on the 2nd Embodiment of this invention. It is a conceptual diagram which shows the structure of the reconfiguration
  • LUTs look-up tables
  • FIG. 1 is a block diagram showing a configuration of a reconfiguration circuit 1 configured in the reconfiguration circuit of the present embodiment.
  • the reconstruction circuit 1 includes a first LUT 10-1, a second LUT 10-2, and a switch 17.
  • the output node (first output node 15-1) of the first LUT 10-1 and the output node (second output node 15-2) of the second LUT 10-2 are mutually connected via the switch 17 Be done.
  • the LUT 10 is configured using a crossbar switch circuit.
  • the switch cells connecting the cross points of the crossbar switch circuit included in the reconfiguration circuit of the present embodiment include a resistance change element.
  • the first LUT 10-1 outputs a signal via the first output node 15-1.
  • the first LUT 10-1 is connected to the switch 17 via the first output node 15-1.
  • the second LUT 10-2 outputs a signal via the second output node 15-2.
  • the second LUT 10-2 is connected to the switch 17 via the second output node 15-2.
  • the switch 17 is connected to the first LUT 10-1 via the first output node 15-1, and connected to the second LUT 10-2 via the second output node 15-2.
  • the switch 17 has a configuration of a complementary element in which two semiconductor elements having different polarities are combined.
  • the switch 17 is realized by a selection transistor in which an NMOS (N-type Metal-Oxide-Semiconductor) and a PMOS (P-type Metal-Oxide-Semiconductor) are combined.
  • the switch 17 is connected to the first output node 15-1 of the first LUT 10-1 and the second output node 15-2 of the second LUT 10-2.
  • the switch 17 switches the first output node 15-1 of the first LUT 10-1 and the second output node 15-2 of the second LUT 10-2 to the electrically conductive or non-conductive state.
  • FIG. 2 is a block diagram showing the configuration of the LUT 10.
  • the LUT 10 includes a crossbar memory 11 and a multiplexer 13. Although only one crossbar memory 11 and one multiplexer 13 are illustrated in FIG. 2, the LUT 10 can be configured by combining an arbitrary number of crossbar memories 11 and multiplexers 13.
  • the crossbar memory 11 is a storage circuit configured using a crossbar switch circuit.
  • the crossbar memory 11 is configured as a crossbar switch circuit having a plurality of switch cells including complementary elements.
  • the crossbar memory 11 is configured by a crossbar switch circuit 12 of 2 inputs and K outputs (K is a natural number).
  • the multiplexer 13 is a selection circuit that receives a plurality of signals output from the crossbar memory 11 and selects and outputs one of the input signals. In other words, the multiplexer 13 outputs one of the plurality of signals input from the crossbar switch circuit to the output node 15 in response to the selection control signal (not shown).
  • the multiplexer 13 can be configured by combining a plurality of complementary elements in multiple stages.
  • a complementary element including a p-type metal oxide semiconductor device (PMOS) and an n-type metal oxide semiconductor device (NMOS) is exemplified.
  • the reconfiguration circuit 1 of the present embodiment is connected to the crossbar switch circuit 12 in which the crossbar memory 11 is configured, the multiplexer 13 connected to the crossbar switch circuit, and the output node 15 of at least two LUTs 10.
  • the LUT 10 is configured of a crossbar memory 11 configured using a crossbar switch circuit and a multiplexer 13.
  • the switch 17 When the switch 17 is in the ON state, one node is included in the crossbar memory 11 in which the first LUT 10-1 is configured, and one in the crossbar memory 11 in which the second LUT 10-2 is configured. Electrically connect with the node. When the switch 17 is in the off state, the switch 17 disconnects the electrical connection between the first LUT 10-1 and the second LUT 10-2.
  • FIG. 3 is a conceptual view showing a configuration of the variable resistance element 50 included in a switch cell configuring the crossbar switch circuit included in the reconfiguration circuit of the present embodiment.
  • FIG. 4 is a symbolic representation of the resistance change element 50.
  • the variable resistance element 50 includes a first wiring layer 51 (also described as T1), a solid electrolyte layer 52 (also described as IC), and a second wiring layer 53 (also described as T2). And.
  • the solid electrolyte layer 52 contains metal ions and is disposed between the first wiring layer 51 and the second wiring layer 53.
  • the resistance change element 50 can change the resistance value by applying a forward bias or a reverse bias to both terminals of the first wiring layer 51 and the second wiring layer 53.
  • variable resistance element 50 one that can change its resistance by applying a predetermined voltage or more for a predetermined time and can hold the changed resistance is used.
  • ReRAM Resistance Random Access Memory
  • NanoBridge registered trademark
  • ion conductor or the like
  • the variable resistance element 50 may include two bipolar variable resistance elements having a polarity in the application direction of the voltage for changing the resistance.
  • the variable resistance element 50 has a configuration in which two bipolar variable resistance elements are opposed and connected in series, and a switch (transistor) is disposed at a connection point of two switches. This is because the variable resistance element 50 having such a configuration has high disturbance resistance when using a signal continuously passing through.
  • the resistance change element 50 may be a resistance change element utilizing movement of metal ions and an electrochemical reaction in a solid (ion conductor) in which ions can freely move by application of an electric field or the like.
  • variable resistance element 50 can be used as a switch element that can distinguish whether or not a signal passes between electrodes because the amount of change in resistance is large.
  • the solid electrolyte layer 52 used for the resistance change element 50 receives metal ions from the first wiring layer 51 but does not receive metal ions from the second wiring layer 53.
  • the resistance value of the solid electrolyte layer 52 largely changes, and the voltage between the first wiring layer 51 and the second wiring layer 53 is changed.
  • the conduction state can be controlled.
  • FIG. 5 is a table 500 showing the correspondence between the voltage applied to both terminals of the variable resistance element 50 and the resistance state.
  • a voltage higher than that of the second wiring layer 53 is applied to the first wiring layer 51 (forward bias)
  • the variable resistance element 50 is in a low resistance state (on).
  • a voltage higher than that of the first wiring layer 51 is applied to the second wiring layer 53 (reverse bias)
  • the variable resistance element 50 is in a high resistance state (off).
  • the ratio of the resistance value in the low resistance state (on) to the high resistance state (off) is set to be larger than 10 5.
  • FIG. 6 is a symbolic representation of the switch cell 120 disposed at the cross point of the crossbar switch circuit for realizing the reconfiguration circuit of this embodiment.
  • Switch cell 120 includes a first resistance change element 125-1, a second resistance change element 125-2, and a selection transistor 126.
  • the first resistance change element 125-1 includes the solid electrolyte layer 152-1
  • the second resistance change element 125-2 includes the solid electrolyte layer 152-2.
  • Each of the first resistance change element 125-1 and the second resistance change element 125-2 has the structure of the resistance change element 50 of FIG.
  • the switch cell 120 uses one transistor (selection transistor 126) and two pairs of resistance change elements (first resistance change element 125-1 and second resistance change element 125-2). It is a switch cell of a complementary type (1T2R) structure.
  • One electrodes of the first resistance change element 125-1 and the second resistance change element 125-2 are connected to each other to form a shared node (hereinafter, common node 127).
  • the common node 127 is connected to one diffusion layer (source or drain) of the selection transistor 126.
  • the other electrode TR1 of the first resistance change element 125-1 is connected to the first signal line.
  • the resistance value of the first resistance change element 125-1 changes in accordance with the voltage applied to the electrode TR1 and the common node 127.
  • the other electrode TR2 of the second resistance change element 125-2 is connected to the second signal line.
  • the resistance value of second resistance change element 125-2 changes according to the voltage applied to electrode TR 2 and common node 127.
  • the selection transistor 126 can be configured by a general transistor. One of the diffusion layers (source or drain) of the select transistor 126 is connected to the common node 127. The other (drain or source) electrode TS of the diffusion layer of the selection transistor 126 is connected to a write control line SV described later. The gate electrode TG of the selection transistor 126 is connected to a write control line GH described later.
  • the switch cell 120 includes the first resistance change element 125-1 and the second resistance change element 125-2, which can switch the resistance state according to the applied voltage, and at least one selection transistor 126.
  • One terminal of the first resistance change element 125-1 and one terminal of the second resistance change element 125-2 are connected to one of the diffusion layers of the selection transistor 126.
  • the first resistance change element 125-1 and the second resistance change element 125-2 are bipolar type resistance change elements, and are arranged such that the resistance change polarity faces each other.
  • the first resistance change element 125-1 and the second resistance change element 125-2 include an ion conductive solid electrolyte layer.
  • FIG. 7 is a circuit diagram showing a connection relationship between the switch cell 120 and each wire.
  • the switch cell 120 is used as a switch of the crossbar switch circuit 12.
  • the switch cell 120 is a signal line RH [k] which is a wiring along the x direction (also referred to as a first direction) and a signal which is a wiring along ay direction (also referred to as a second direction). It is arranged near the cross point of line RV [j] (j, k: natural number).
  • the electrode TR1 is connected to the signal line RH [k].
  • the electrode TR2 of the second resistance change element 125-2 is connected to the signal line RV [j]. That is, the signal line RV [j] and the signal line RH [k] are connected to the electrode not shared by the first resistance change element 125-1 and the second resistance change element 125-2, respectively.
  • the write control line GH [k] is connected to the gate electrode TG of the selection transistor 126.
  • the write control line SV [j] is connected to the electrode TS of the diffusion layer (drain or source) on the side to which the first resistance change element 125-1 and the second resistance change element 125-2 are not connected. Ru.
  • the write control line GH [k] and the write control line SV [j] are wired independently of the signal line RH [k] and the signal line RV [j], and other switches positioned in the wiring direction Shared with.
  • FIG. 8 is a three-dimensional schematic view of the switch cell 120 shown in FIG. 6 and FIG.
  • the common node 127 is connected to the solid electrolyte layer 152-1 via the via 128-1, and connected to the solid electrolyte layer 152-2 via the via 128-2. In addition, the common node 127 is connected to one (source or drain) of the diffusion layer of the selection transistor 126 through the via 128-3 and the electrode 129.
  • the signal line RH [k] is located in the + z direction of the electrode TR1.
  • the signal line RH [k] and the electrode TR1 are electrically connected via the via 128-4.
  • the signal line RV [j] is electrically connected to the electrode TR2 in the same xy plane.
  • the electrode TR1 and the electrode TR2 are located in the same xy plane.
  • FIG. 9 is a circuit diagram of the crossbar switch circuit 12.
  • the crossbar switch circuit 12 shown in FIG. 9 is a crossbar switch circuit for signal switching of J input and K output (J, K: natural number).
  • FIG. 9 is a diagram including a control transistor for controlling a voltage / current source supplied from a writing power source (PS: Power Source) and a control wiring when the resistance change element is rewritten (at the time of writing). It shows.
  • the circuit configuration shown in FIG. 9 conceptually illustrates a part of the configuration of the crossbar switch circuit 12 and does not represent all.
  • the crossbar switch circuit 12 for realizing the reconstruction circuit 1 of the present embodiment is not limited to the number of elements and signal lines shown in FIG.
  • the crossbar switch circuit 12 includes switch cells 120-1 to 9.
  • Each of switch cells 120-1 to 9 includes a switch element.
  • a pair of resistance change elements are used as switch elements will be described. Further, hereinafter, when the switch cells 120-1 to 9 are not distinguished from one another, the hyphen and the number at the end are omitted and the switch cell 120 is described.
  • Switch cells 120-1 to 3 have write control line GH [k-1] (also referred to as first write control line) and signal line RH [k-1], which are wirings in the x direction (also referred to as first direction). ] (Also referred to as first wiring).
  • the write control line GH [k ⁇ 1] and the signal line RH [k ⁇ 1] are wires independent of each other.
  • the signal line RH [k ⁇ 1] is connected to one diffusion layer of the first control transistor 121 a connected to the switch cells 120-1 to 3.
  • a power supply line PS [0] (also referred to as a first power supply line) is connected to the other diffusion layer of the first control transistor 121a.
  • a write control line GSH [k ⁇ 1] (also referred to as a second write control line) is connected to the gate electrode of the first control transistor 121a.
  • the write control line GSH [k ⁇ 1] is a wiring used to change the resistance of the switch elements included in the switch cells 120-1 to 3.
  • the switch cells 120-4 to 6 share the write control line GH [k] and the signal line RH [k], which are wirings in the x direction.
  • the write control line GH [k] and the signal line RH [k] are wires independent of each other.
  • the signal line RH [k] is connected to one diffusion layer of the first control transistor 121 b connected to the switch cells 120-4 to 6.
  • the power supply line PS [0] is connected to the other diffusion layer of the first control transistor 121b.
  • the write control line GSH [k] is connected to the gate electrode of the first control transistor 121b.
  • the write control line GSH [k] is a wiring used to change the resistance of the switch elements included in the switch cells 120-4 to 6.
  • the switch cells 120-7 to 9 share the write control line GH [k + 1] and the signal line RH [k + 1], which are wirings in the x direction.
  • the write control line GH [k + 1] and the signal line RH [k + 1] are wires independent of each other.
  • the signal line RH [k + 1] is connected to one of the diffusion layers of the first control transistor 121c connected to the switch cells 120-7 to 9.
  • the power supply line PS [0] is connected to the other diffusion layer of the first control transistor 121c.
  • the write control line GSH [k + 1] is connected to the gate electrode of the first control transistor 121c.
  • the write control line GSH [k + 1] is a wiring used to change the resistance of the switch elements included in the switch cells 120-7 to 9.
  • the switch cells 120-1, 4 and 7 have the write control line SV [j-1] (also referred to as a second write control line) and the signal line RV [j], which are wirings in the y direction (also referred to as a second direction). -1] (also referred to as second wiring).
  • the write control line SV [j-1] and the signal line RV [j-1] are wires independent of each other.
  • the write control line SV [j ⁇ 1] is connected to one diffusion layer of the second control transistor 122 a connected to the switch cells 120-1, 4, 7.
  • a power supply line PS [1] (also referred to as a second power supply line) is connected to the other diffusion layer of the second control transistor 122a.
  • the driver control line PGV [j-1] is connected to the gate electrode of the second control transistor 122a. Further, the signal line RV [j ⁇ 1] is connected to one diffusion layer of the third control transistor 123 a connected to the switch cells 120-1, 4, 7.
  • a power supply line PS [2] (also referred to as a third power supply line) is connected to the other diffusion layer of the third control transistor 123a.
  • the driver control line PGV [j-1] is connected to the gate electrode of the third control transistor 123a.
  • the switch cells 120-2, 5, 8 share the write control line SV [j] and the signal line RV [j], which are wirings in the y direction.
  • the write control line SV [j] and the signal line RV [j] are wires independent of each other.
  • the write control line SV [j] is connected to one diffusion layer of the second control transistor 122 b connected to the switch cells 120-2, 5 and 8.
  • the power supply line PS [1] is connected to the other diffusion layer of the second control transistor 122b.
  • the driver control line PGV [j] is connected to the gate electrode of the second control transistor 122b.
  • the signal line RV [j] is connected to one diffusion layer of the third control transistor 123 b connected to the switch cells 120-2, 5, 8.
  • the power supply line PS [2] is connected to the other diffusion layer of the third control transistor 123b.
  • the driver control line PGV [j] is connected to the gate electrode of the third control transistor 123b.
  • the switch cells 120-3, 6, 9 share the write control line SV [j + 1] and the signal line RV [j + 1], which are wirings in the y direction.
  • the write control line SV [j + 1] and the signal line RV [j + 1] are wires independent of each other.
  • the write control line SV [j + 1] is connected to one diffusion layer of the second control transistor 122 c connected to the switch cells 120-3, 6, 9.
  • the power supply line PS [1] is connected to the other diffusion layer of the second control transistor 122c.
  • the driver control line PGV [j + 1] is connected to the gate electrode of the second control transistor 122c.
  • the signal line RV [j + 1] is connected to one diffusion layer of the third control transistor 123c connected to the switch cells 120-3, 6, 9.
  • the power supply line PS [2] is connected to the other diffusion layer of the third control transistor 123c.
  • the driver control line PGV [j + 1] is connected to the gate electrode of the third control transistor 123c.
  • FIG. 10 is a conceptual diagram showing an I / O interface, with the J input / K output crossbar switch circuit 12 as one block.
  • the signal line RV and the driver control line PGV are arranged on one side corresponding to the x direction.
  • the write control line GH, the write control line GSH, and the power supply line PS are disposed on one side corresponding to the y direction, and the signal line RH is disposed on the other side.
  • the conceptual diagram of the cross bar shown in FIG. 10 is an illustration, and does not limit the scope of the present invention.
  • FIG. 11 is a conceptual diagram showing an input / output interface of a crossbar switch circuit (crossbar memory 11) modified for memory.
  • crossbar memory 11 on one side corresponding to the x direction, a signal line RV to which each of the power supply level (VDD) or the ground level (GND) is input and a driver control line PGV are arranged.
  • the write control line GH, the write control line GSH, and the power supply line PS are disposed on one side corresponding to the y direction, and the signal line RH is disposed on the other side.
  • the crossbar memory 11 can function as a memory by inputting a power supply level (hereinafter, VDD) and a ground level (hereinafter, GND) to the two RV ports in the crossbar switch configuration. By turning on the switch cell of VDD or GND, the output level of the output node of the crossbar memory 11 can be controlled to VDD or GND.
  • VDD power supply level
  • GND ground level
  • the multiplexer 13 has a configuration in which a plurality of complementary elements (switches 130) are combined.
  • FIG. 12 shows an example in which the switches 130-1 to 6 in which a pair of CMOS and NMOS are connected in parallel are combined.
  • FIG. 12 shows an example in which six switches 130-1 to 6 are combined and subjected to two inputs, the number of switches 130 and the number of inputs are set according to the scale of the logic circuit to be configured.
  • the gate lines connected to the gate electrodes of the CMOS and NMOS of the switches 130-1 to 6 are omitted.
  • FIG. 13 is a conceptual diagram showing the configuration of the reconfiguration circuit 1 of the present embodiment.
  • an example is shown in which the output node 15 of the LUT 10 of FIG. 11 is connected via a complementary element (switch 17).
  • switch 17 the gate lines connected to the CMOS and NMOS gate electrodes of the switch 17 are omitted.
  • the reconfiguration circuit 1 can switch the mode by turning on and off the switch 17.
  • the switch 17 When the switch 17 is off (normal mode), the first output node 15-1 and the second output node 15-2 are not short-circuited.
  • the switch 17 when the switch 17 is on (high reliability mode), the first output node 15-1 and the second output node 15-2 are shorted.
  • the switch 17 when the switch 17 is off (normal mode), the first LUT 10-1 and the second LUT 10-2 execute different logical operations independently of each other. Therefore, the operation result of the first LUT 10-1 is output from the first output node 15-1, and the operation result of the second LUT 10-2 is output from the second output node 15-2.
  • the switch 17 when the switch 17 is in the on state (reliable mode), the switch 17 is shorted.
  • the reconfiguration circuit 1 executes the same logical operation as the first LUT 10-1 and the second LUT 10-2. Therefore, the same calculation result calculated by the redundant first LUT 10-1 and the second LUT 10-2 is output from the first output node 15-1 and the second output node 15-2.
  • a high reliability LUT 110 is formed in which two LUTs performing the same logical operation are redundant.
  • the switch 17 When the same logical operation is performed on the first LUT 10-1 and the second LUT 10-2 using the high reliability mode, the switch 17 is turned on to connect the two LUTs to each other. At this time, the memory state of the two LUTs 10 and the input signal are made identical and operated as one LUT to operate a desired application. As a result, in the high reliability mode, high reliability can be obtained for the holding failure of the variable resistance element 50.
  • the on / off of the switch 17 can be controlled by, for example, an IO (Input Output) pin of the chip. Further, the on / off of the switch 17 may be controlled by preparing a memory that holds the on / off state for each switch 17, for example.
  • IO Input Output
  • each node in two different LUTs 10 (FIG. 15) is electrically connected to the corresponding switch cell 120 in crossbar memory 11 via switch 130 constituting multiplexer 13. Be done.
  • One node inside the LUT 10 (FIG. 15) is pulled up to VDD or pulled down to GND through the two switch cells 120 in the on state. For this reason, even if one switch cell corresponding to the same node causes a holding failure and the state transitions, the potential of the node can be kept the same.
  • the retention failure rate of the variable resistance element when stored for 10 years at a temperature of 150 degrees is 1/6 of 10
  • the probability that the circuit malfunctions is equal to 10 6 6 before redundancy. In contrast to being 1, it can be improved to one tenth of a factor of 10 by redundancy.
  • a plurality of reconfiguration circuits 1 (hereinafter, CLBs: Configurable Logic Blocks) can be arranged side by side and connected to each other, whereby a larger scale reconfiguration circuit 1000 (also referred to as an integrated circuit) can be configured.
  • CLBs Configurable Logic Blocks
  • one memory can be configured by sharing on / off states of a plurality of switches 17 included in a plurality of CLBs.
  • the memory configured in this way is redundantly redundant and has high reliability.
  • the write control line of the crossbar memory 11 included in each reconfiguration circuit 1 is shared.
  • on / off states are shared by a plurality of switches 17 included in a plurality of CLBs, control can be performed using one memory.
  • the on / off state is shared by a plurality of switches included in a plurality of CLBs, it is desirable to use a redundant memory.
  • the output nodes of the two LUTs are connected by the switch including the complementary element.
  • the switch is turned off and each LUT is used as a different logical operation circuit.
  • the switch is turned on, and the state of the LUT memory and the input signal to the multiplexer in the LUT are the same between the two LUTs connected by the switch. Do. As a result, even if a holding failure occurs in a switch cell included in one of the LUTs and a transition is made to a high resistance state, the switch cell used in the other LUT is pulled down or pulled up. You can
  • the reconfiguration circuit of this embodiment can implement two applications while being a single circuit.
  • One is an application that implements an application at high density as a reconfigurable circuit without redundant bits.
  • the other is an application requiring high reliability that enables continuous application operation even when the resistance change element causes a holding failure.
  • the circuit area required for application operation can be suppressed as compared with high density mounting. That is, according to the present embodiment, it is possible to implement a continuous application operation by providing redundancy with a small amount of circuit overhead while mounting an application at high density as a reconfiguration circuit having no redundant bits. It becomes possible to offer.
  • the reconstruction circuit For example, three same application patterns are prepared on the reconstruction circuit, the same signal is input to each pattern, and majority decision circuit is inserted to the output node, thereby improving the retention reliability as a chip can do.
  • this method using the majority circuit it is possible to improve the reliability only by changing the switch pattern (configuration pattern) for mounting the application pattern on the reconfiguration circuit, and therefore, it is not necessary to change the circuit of the reconfiguration circuit itself.
  • the use of a majority circuit requires three times or more of the circuit area required for the application operation.
  • FIGS. 18 to 20 there is a method of connecting redundantly the number of switches of the crossbar switch circuit constituting the LUT memory to a signal switching point to make it redundant.
  • FIG. 18 and FIG. 19 are examples of multiplexing RV (VDD and GND) and PGV.
  • FIG. 20 shows an example of multiplexing the crossbar memory.
  • FIG. 21 is a conceptual diagram showing the configuration of the reconfiguration circuit 2 included in the reconfiguration circuit of the present embodiment.
  • the reconstruction circuit 2 includes a first LUT 20-1, a second LUT 20-2, and a switch 27.
  • the output node (first output node 25-1) of the first LUT 20-1 and the output node (second output node 25-2) of the second LUT 20-2 are mutually connected via the switch 27. Be done.
  • the first LUT 20-1 and the second LUT 20-2 are not distinguished from one another, they are referred to as the LUT 20.
  • the first LUT 20-1 outputs a signal via the first output node 25-1.
  • the first LUT 20-1 is connected to the switch 27 via the first output node 25-1.
  • the second LUT 20-2 outputs a signal via the second output node 25-2.
  • the second LUT 20-2 is connected to the switch 27 via the second output node 25-2.
  • the switch 27 is connected to the first LUT 20-1 through the first output node 25-1, and is output to the second LUT 20-2 through the second output node 25-2.
  • the switch 27 is similar to the switch 17 of the first embodiment.
  • FIG. 22 is a block diagram showing the configuration of the LUT 20. As shown in FIG. As shown in FIG. 22, the LUT 20 includes a first crossbar memory 21A, a second crossbar memory 21B, a first multiplexer 23, and a second multiplexer 24.
  • the first crossbar memory 21A and the second crossbar memory 21B are storage circuits configured by crossbar switch circuits.
  • the first crossbar memory 21A and the second crossbar memory 21B have nodes at the same signal level or high impedance state as the input signal.
  • the first crossbar memory 21A and the second crossbar memory 21B are realized by a two-input K-output crossbar switch circuit (K is a natural number).
  • the first multiplexer 23 is a selection circuit which receives a plurality of signals output from the first crossbar memory 21A, selects one of the input signals, and outputs the selected one.
  • the first multiplexer 23 has a configuration in which a plurality of PMOSs are combined in multiple stages, and selects at least one of the plurality of signals input from the first crossbar memory 21A.
  • the second multiplexer 24 is a selection circuit which receives a plurality of signals output from the second crossbar memory 21B as input, and selects and outputs any one of the input signals.
  • the second multiplexer 24 has a configuration in which a plurality of NMOSs are combined in multiple stages, and selects at least one of the plurality of signals input from the second crossbar memory 21B.
  • the first multiplexer 23 and the second multiplexer 24 output any one of the plurality of signals input from the crossbar switch circuit to the common output node 25 in response to a selection control signal (not shown).
  • FIG. 23 is a circuit diagram showing a circuit configuration of the crossbar switch circuit 22 included in the reconfiguration circuit of the present embodiment.
  • FIG. 23 also includes a control transistor for controlling a voltage / current source supplied from a writing power source (PS: Power Source) and a control wiring when rewriting the resistance change element (during writing). It shows.
  • the circuit configuration shown in FIG. 23 is a conceptual diagram illustrating a part of the configuration of the crossbar switch circuit 22 and does not represent all.
  • the crossbar switch circuit 22 for realizing the reconstruction circuit 2 of the present embodiment is not limited to the number of elements and signal lines shown in FIG.
  • Crossbar switch circuit 22 includes switch cells 220-1-6. Each of switch cells 220-1 to 6 includes a switch element. In the present embodiment, an example in which a pair of resistance change elements are used as switch elements will be described. Further, hereinafter, when the switch cells 220-1 to 6 are not distinguished from one another, the hyphens and numbers at the end are omitted and described as the switch cell 220.
  • the output ports of the crossbar switch circuit 22 are provided on the left and right (x direction) of the crossbar switch circuit 22.
  • the power supply line PS [0] (also referred to as a first power supply line) for writing installed along the y direction shares the switch cells 220-1 to 6 positioned on the left and right of the power supply line PS [0]. Power source.
  • Switch cells 220-1 to 3 and first control transistors 221-1 to 22-3 are arranged along the y direction between the left output port and the power supply line PS [0].
  • Switch cells 220-1 to 220-3 are write control lines GH [k-1] to GH [k + 1] (also referred to as first write control lines), which are wirings in the x direction (also referred to as the first direction), and signal lines It is connected to RH1 [k-1] to RH1 [k + 1] (also referred to as first wiring).
  • the write control lines GH [k ⁇ 1] to GH [k + 1] and the signal lines RH1 [k ⁇ 1] to RH1 [k + 1] are wires independent of each other.
  • the signal lines RH1 [k ⁇ 1] to RH1 [k + 1] are connected to one of the diffusion layers of the first control transistors 221a to 221c connected to the switch cells 220-1 to 220-3.
  • a power supply line PS [0] (also referred to as a first power supply line) is connected to the other diffusion layer of the first control transistors 221a to 221c.
  • Switch cells 220-1 to 220-3 have a write control line SV [1] (also referred to as a second write control line) and a signal line RV [1] (a second line), which are wirings in the y direction (also referred to as a second direction). Share the wiring).
  • the write control line SV [1] and the signal line RV [1] are wires independent of each other.
  • the write control line SV [1] is connected to one diffusion layer of the second control transistor 222 a connected to the switch cells 220-1 to 3.
  • a power supply line PS [1] (also referred to as a second power supply line) is connected to the other diffusion layer of the second control transistor 222a.
  • the driver control line PGV [1] is connected to the gate electrode of the second control transistor 222a.
  • the driver control line PGV [1] is shared by the first control transistors 221a, 221b, and 221c.
  • the driver control line PGV [1] is a second control transistor provided to control the power supply line for writing from the power supply line PS [1] and the power supply line PS [2] (also referred to as a third power supply line). It is shared as a gate line of 222a and the third control transistor 223a.
  • the signal line RV [1] is connected to one diffusion layer of the third control transistor 223a connected to the switch cells 220-1 to 2.
  • the power supply line PS [2] is connected to the other diffusion layer of the third control transistor 223a.
  • Switch cells 220-4 to 6 and first control transistors 221d, 221e, and 221f are disposed along the y direction between the output port on the right side and PS [0].
  • the switch cells 220-4 to 6 are connected to write control lines GH [k-1] to GH [k + 1] and signal lines RH2 [k-1] to RH2 [k + 1], which are wirings in the x direction.
  • the write control lines GH [k ⁇ 1] to GH [k + 1] are shared by the switch cells 220-1 to 3 and the switch cells 220-4 to 6, respectively.
  • the write control lines GH [k ⁇ 1] to GH [k + 1] and the signal lines RH2 [k ⁇ 1] to RH2 [k + 1] are wires independent of each other.
  • the signal lines RH2 [k-1] to RH2 [k + 1] are connected to one of the diffusion layers of the first control transistors 221d to 221f connected to the switch cells 220-4 to 6, respectively.
  • the power supply line PS [0] is connected to the other diffusion layer of the first control transistors 221d to 221f.
  • the switch cells 220-4 to 6 share the write control line SV [2] and the signal line RV [2], which are wirings in the y direction.
  • the write control line SV [2] and the signal line RV [2] are wires independent of each other.
  • the write control line SV [2] is connected to one diffusion layer of the second control transistor 222 b connected to the switch cells 220-4 to 6.
  • the power supply line PS [1] is connected to the other diffusion layer of the second control transistor 222b.
  • the driver control line PGV [2] is connected to the gate electrode of the second control transistor 222b.
  • the driver control line PGV [2] is shared by the first control transistors 221d, 221e, and 221f.
  • the driver control line PGV [2] is a second control transistor 222b and a third control transistor 223b provided to control the power supply line for writing from the power supply line PS [1] and the power supply line PS [2].
  • the signal line RV [2] is connected to one diffusion layer of the third control transistor 223b connected to the switch cells 220-4 to 6.
  • the power supply line PS [2] is connected to the other diffusion layer of the third control transistor 223b.
  • FIG. 24 is a conceptual diagram showing an input / output interface of a crossbar switch circuit (crossbar memory 21) modified for memory.
  • the signal line RV and the driver control line PGV are arranged on one side corresponding to the x direction.
  • the signal line RH1, the write control line GH, and the power supply line PS are disposed on one side corresponding to the y direction, and the signal line RH2 is disposed on the other side.
  • the crossbar memory 21 can function as a memory by inputting a power supply level (hereinafter, VDD) or a ground level (hereinafter, GND) to one RV port of the crossbar switch configuration.
  • VDD power supply level
  • GND ground level
  • the output of the crossbar memory 21 can be controlled by rewriting either the VDD or the high resistance state (High-z) switch cell.
  • the input to the crossbar switch circuit 22 is GND
  • the output to the crossbar switch circuit 22 can be controlled by rewriting either the GND or the high resistance state (High-z) switch cell.
  • FIG. 25 is a conceptual diagram showing a circuit configuration of the reconfiguration circuit 2 (FIG. 21) of the present embodiment.
  • the first output node 25-1 of the first LUT 20-1 and the second output node 25-2 of the second LUT 20-2 are connected via the complementary element (switch 27).
  • switch 27 An example of connecting
  • the first LUT 20-1 includes a first crossbar memory 21A-1, a second crossbar memory 21B-1, a first multiplexer 23-1, a second multiplexer 24-1, and a first output node 25. It has -1.
  • the first crossbar memory 21A-1 and the second crossbar memory 21B-1 are, for example, 1-input 2K-output crossbar switch circuits.
  • the first multiplexer 23-1 has a configuration in which a plurality of PMOSs are combined.
  • the second multiplexer 24-1 has a configuration in which a plurality of NMOSs are combined.
  • the first LUT 20-1 has input ports separated and disposed to the left and right across the first output node 25-1.
  • the left input port of the first LUT 20-1 is connected to one output port of the first crossbar memory 21A-1 disposed on the left.
  • the input port on the right side of the first LUT 20-1 is connected to one output port of the second crossbar memory 21B-1 disposed on the right side.
  • the input signals to the first multiplexer 23-1 and the second multiplexer 24-1 included in the first LUT 20-1 are related.
  • One conduction path is selected from each of the first multiplexer 23-1 and the second multiplexer 24-1 for the gate input signal set to the first LUT 20-1.
  • the second LUT 20-2 includes a first crossbar memory 21A-2, a second crossbar memory 21B-2, a first multiplexer 23-2, a second multiplexer 24-2, and a second output node 25. It has -2.
  • the first crossbar memory 21A-2 and the second crossbar memory 21B-2 are, for example, 1-input 2K-output crossbar switch circuits.
  • the first multiplexer 23-2 has a configuration in which a plurality of PMOSs are combined.
  • the second multiplexer 24-2 has a configuration in which a plurality of NMOSs are combined.
  • the second LUT 20-2 has input ports separated and disposed to the left and right across the second output node 25-2.
  • the left input port of the second LUT 20-2 is connected to one output port of the first crossbar memory 21A-2 disposed on the left.
  • the input port on the right side of the second LUT 20-2 is connected to one output port of the second crossbar memory 21B-2 disposed on the right side.
  • the input signals to the first multiplexer 23-2 and the second multiplexer 24-2 included in the second LUT 20-2 are related.
  • One conduction path is selected from each of the first multiplexer 23-2 and the second multiplexer 24-2 for the gate input signal set to the second LUT 20-2.
  • the method of changing the value output from the first output node 25-1 will be described.
  • the method of changing the value output from the second output node 25-2 is the same as that of the first output node 25-1, and thus the description thereof is omitted.
  • the switch cell 220 included in the first crossbar memory 21A-1 connected to the source of the PMOS included in the first multiplexer 23-1 is turned on to start the first crossbar memory 21A-1
  • the case of outputting VDD will be described.
  • the switch cell 220 in the second crossbar memory 21B-1 connected to the drain of the NMOS included in the second multiplexer 24-1 is turned off to output High-Z.
  • the VDD level is output at a node where the internal source and drain of the first multiplexer 23-1 and the second multiplexer 24-1 are connected to each other.
  • the switch cell 220 included in the first crossbar memory 21A-1 connected to the source of the PMOS included in the first multiplexer 23-1 is turned off, and the first crossbar memory 21A-1 is opened.
  • the switch cell included in the second crossbar memory 21B-1 connected to the drain of the NMOS included in the second multiplexer 24-1 is turned on to output GND.
  • the GND level can be output at the node where the sources and drains of the NMOS and PMOS inside the first multiplexer 23-1 and the second multiplexer 24-1 are connected to each other.
  • Desired logic operation is performed as a LUT by rewriting the switch cell 220 on the conduction path selected for the gate input signal set to the first LUT 20-1 and the second LUT 20-2 while paying attention to the complementarity Be done.
  • the first output node 25-1 of the first LUT 20-1 and the second of the second LUT 20-2 are connected via the switch 27 which is a complementary element. And the output node 25-2 of the
  • the switch 27 When different logical operations are performed on the first LUT 20-1 and the second LUT 20-2 in the circuit configuration of the reconstruction circuit 2 (FIG. 21) shown in FIG. 25, the switch 27 is used as shown in FIG. Turn off. When the switch 27 is turned off, desired memory states and input signals can be selected for each of the first LUT 20-1 and the second LUT 20-2, and a desired application can be operated. In this case, since the use efficiency of the LUT is high and logic can be implemented at high density, performances such as power and delay become high.
  • the switch 27 is turned on and the first LUT 20-1 and the second LUT 20-2 are mutually switched. Connect to At this time, the memory states of the first LUT 20-1 and the second LUT 20-2 and the input signals are made identical and operated as one LUT to operate a desired application.
  • each node in the first LUT 20-1 (FIG. 25) and the second LUT 20-2 (FIG. 25) passes through the first multiplexer 23 and the second multiplexer 24, respectively. It is electrically connected to the corresponding switch cell.
  • One node is pulled up to VDD or pulled down to GND through two switch cells in the on state. For this reason, even if one switch cell causes a holding failure and the state transitions, the potential of the node can be kept the same.
  • the retention failure rate of the variable resistance element when stored for 10 years at a temperature of 150 degrees is 1/6 of 10
  • the probability that the circuit malfunctions is equal to 10 6 6 before redundancy. In contrast to being 1, it can be improved to 1/12 to the tenth by redundancy.
  • the desired logic operation can be performed by rewriting the switch cells on the path selected for each gate input signal set to the LUT while paying attention to the complementarity.
  • An executable LUT can be realized.
  • the operating voltage is alternatively applied to one of the switch cells in the off state. Therefore, according to the present embodiment, the LUT (FIG. 12) using the crossbar switch circuit (FIG. 11) of the first embodiment in which operating voltages are applied to all the switch cells (2 ⁇ N) Leakage current can be reduced to 1/2 ⁇ N in comparison with.

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Abstract

La présente invention a pour objet d'atteindre une mise en œuvre à haute densité d'applications sous la forme d'un circuit de reconfiguration sans bit de redondance ainsi que la capacité d'exécuter en continu des applications avec redondance. Plus particulièrement, l'invention concerne un circuit de reconfiguration comprenant : une première table de consultation composée d'une mémoire à barres croisées formée dans un circuit de commutation à barres croisées ayant une pluralité de cellules de commutation comprenant un élément complémentaire et un multiplexeur pour sélectionner et délivrer en sortie au moins l'un d'une pluralité de signaux entrés à partir de la mémoire à barres croisées ; une seconde table de consultation composée d'une mémoire à barres croisées et d'un multiplexeur ; et un commutateur qui est connecté à un nœud de sortie de la première table de consultation et à un nœud de sortie de la seconde table de consultation et qui commute le nœud de sortie de la première table de consultation et le nœud de sortie de la seconde table de consultation vers un état conducteur ou un état non conducteur.
PCT/JP2018/033178 2017-09-11 2018-09-07 Circuit de reconfiguration Ceased WO2019049980A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003177935A (ja) * 2002-08-26 2003-06-27 Hitachi Ltd 冗長システム
US20080288758A1 (en) * 2004-10-25 2008-11-20 Robert Bosch Gmbh Method and Device for Switching Over in a Computer System Having at Least Two Execution Units
WO2017126544A1 (fr) * 2016-01-20 2017-07-27 日本電気株式会社 Circuit reconfigurable, système de circuit reconfigurable et procédé de fonctionnement de circuit reconfigurable

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003177935A (ja) * 2002-08-26 2003-06-27 Hitachi Ltd 冗長システム
US20080288758A1 (en) * 2004-10-25 2008-11-20 Robert Bosch Gmbh Method and Device for Switching Over in a Computer System Having at Least Two Execution Units
WO2017126544A1 (fr) * 2016-01-20 2017-07-27 日本電気株式会社 Circuit reconfigurable, système de circuit reconfigurable et procédé de fonctionnement de circuit reconfigurable

Non-Patent Citations (1)

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Title
ZHENG, MEISONG ET AL.: "DAO; Dual Module Redundancy with AND/OR Logic Voter for FPGA Hardening", 2015 FIRST INTERNATIONAL CONFERENCE ON RELIABILITY SYSTEMS ENGINEERING (ICRSE, 2015, China, pages 1 - 5, XP032838656, DOI: doi:10.1109/ICRSE.2015.7366414 *

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